1 | /* cpu.h |
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2 | * |
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3 | * This include file contains information pertaining to the PowerPC |
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4 | * processor. |
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5 | * |
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6 | * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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7 | * Surrey Satellite Technology Limited (SSTL), 2001 |
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8 | * |
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9 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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10 | * |
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11 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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12 | * |
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13 | * To anyone who acknowledges that this file is provided "AS IS" |
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14 | * without any express or implied warranty: |
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15 | * permission to use, copy, modify, and distribute this file |
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16 | * for any purpose is hereby granted without fee, provided that |
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17 | * the above copyright notice and this notice appears in all |
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18 | * copies, and that the name of i-cubed limited not be used in |
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19 | * advertising or publicity pertaining to distribution of the |
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20 | * software without specific, written prior permission. |
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21 | * i-cubed limited makes no representations about the suitability |
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22 | * of this software for any purpose. |
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23 | * |
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24 | * Derived from c/src/exec/cpu/no_cpu/cpu.h: |
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25 | * |
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26 | * COPYRIGHT (c) 1989-1997. |
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27 | * On-Line Applications Research Corporation (OAR). |
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28 | * |
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29 | * The license and distribution terms for this file may be found in |
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30 | * the file LICENSE in this distribution or at |
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31 | * http://www.rtems.com/license/LICENSE. |
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32 | * |
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33 | * $Id$ |
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34 | */ |
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35 | |
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36 | #ifndef _RTEMS_NEW_EXCEPTIONS_CPU_H |
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37 | #define _RTEMS_NEW_EXCEPTIONS_CPU_H |
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38 | |
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39 | #ifndef _RTEMS_SCORE_CPU_H |
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40 | #error "You should include <rtems/score/cpu.h>" |
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41 | #endif |
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42 | |
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43 | #include <rtems/powerpc/registers.h> |
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44 | |
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45 | #ifdef __cplusplus |
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46 | extern "C" { |
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47 | #endif |
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48 | |
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49 | /* conditional compilation parameters */ |
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50 | |
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51 | /* |
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52 | * Does RTEMS manage a dedicated interrupt stack in software? |
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53 | * |
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54 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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55 | * If FALSE, nothing is done. |
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56 | * |
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57 | * If the CPU supports a dedicated interrupt stack in hardware, |
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58 | * then it is generally the responsibility of the BSP to allocate it |
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59 | * and set it up. |
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60 | * |
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61 | * If the CPU does not support a dedicated interrupt stack, then |
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62 | * the porter has two options: (1) execute interrupts on the |
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63 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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64 | * interrupt stack. |
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65 | * |
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66 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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67 | * |
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68 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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69 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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70 | * possible that both are FALSE for a particular CPU. Although it |
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71 | * is unclear what that would imply about the interrupt processing |
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72 | * procedure on that CPU. |
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73 | */ |
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74 | |
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75 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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76 | |
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77 | /* |
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78 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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79 | * |
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80 | * If TRUE, then it must be installed during initialization. |
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81 | * If FALSE, then no installation is performed. |
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82 | * |
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83 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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84 | * |
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85 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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86 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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87 | * possible that both are FALSE for a particular CPU. Although it |
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88 | * is unclear what that would imply about the interrupt processing |
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89 | * procedure on that CPU. |
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90 | */ |
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91 | |
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92 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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93 | |
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94 | /* |
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95 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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96 | * |
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97 | * If TRUE, then the memory is allocated during initialization. |
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98 | * If FALSE, then the memory is allocated during initialization. |
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99 | * |
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100 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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101 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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102 | */ |
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103 | |
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104 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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105 | |
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106 | /* |
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107 | * Does the RTEMS invoke the user's ISR with the vector number and |
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108 | * a pointer to the saved interrupt frame (1) or just the vector |
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109 | * number (0)? |
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110 | */ |
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111 | |
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112 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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113 | |
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114 | /* |
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115 | * Should the saving of the floating point registers be deferred |
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116 | * until a context switch is made to another different floating point |
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117 | * task? |
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118 | * |
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119 | * If TRUE, then the floating point context will not be stored until |
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120 | * necessary. It will remain in the floating point registers and not |
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121 | * disturned until another floating point task is switched to. |
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122 | * |
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123 | * If FALSE, then the floating point context is saved when a floating |
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124 | * point task is switched out and restored when the next floating point |
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125 | * task is restored. The state of the floating point registers between |
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126 | * those two operations is not specified. |
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127 | * |
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128 | * If the floating point context does NOT have to be saved as part of |
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129 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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130 | * |
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131 | * Setting this flag to TRUE results in using a different algorithm |
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132 | * for deciding when to save and restore the floating point context. |
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133 | * The deferred FP switch algorithm minimizes the number of times |
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134 | * the FP context is saved and restored. The FP context is not saved |
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135 | * until a context switch is made to another, different FP task. |
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136 | * Thus in a system with only one FP task, the FP context will never |
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137 | * be saved or restored. |
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138 | * |
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139 | * Note, however that compilers may use floating point registers/ |
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140 | * instructions for optimization or they may save/restore FP registers |
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141 | * on the stack. You must not use deferred switching in these cases |
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142 | * and on the PowerPC attempting to do so will raise a "FP unavailable" |
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143 | * exception. |
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144 | */ |
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145 | /* |
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146 | * ACB Note: This could make debugging tricky.. |
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147 | */ |
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148 | |
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149 | /* conservative setting (FALSE); probably doesn't affect performance too much */ |
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150 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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151 | |
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152 | /* |
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153 | * Processor defined structures required for cpukit/score. |
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154 | */ |
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155 | |
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156 | #ifndef ASM |
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157 | |
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158 | /* |
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159 | * The following table contains the information required to configure |
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160 | * the PowerPC processor specific parameters. |
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161 | */ |
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162 | |
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163 | typedef struct { |
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164 | void (*pretasking_hook)( void ); |
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165 | void (*predriver_hook)( void ); |
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166 | void (*postdriver_hook)( void ); |
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167 | void (*idle_task)( void ); |
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168 | boolean do_zero_of_workspace; |
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169 | uint32_t idle_task_stack_size; |
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170 | uint32_t interrupt_stack_size; |
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171 | uint32_t extra_mpci_receive_server_stack; |
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172 | void * (*stack_allocate_hook)( uint32_t ); |
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173 | void (*stack_free_hook)( void* ); |
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174 | /* end of fields required on all CPUs */ |
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175 | |
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176 | uint32_t clicks_per_usec; /* Timer clicks per microsecond */ |
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177 | boolean exceptions_in_RAM; /* TRUE if in RAM */ |
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178 | |
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179 | #if (defined(ppc403) || defined(ppc405) \ |
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180 | || defined(mpc860) || defined(mpc821) || defined(mpc8260)) |
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181 | uint32_t serial_per_sec; /* Serial clocks per second */ |
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182 | boolean serial_external_clock; |
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183 | boolean serial_xon_xoff; |
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184 | boolean serial_cts_rts; |
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185 | uint32_t serial_rate; |
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186 | uint32_t timer_average_overhead; /* Average overhead of timer in ticks */ |
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187 | uint32_t timer_least_valid; /* Least valid number from timer */ |
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188 | boolean timer_internal_clock; /* TRUE, when timer runs with CPU clk */ |
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189 | #endif |
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190 | |
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191 | #if (defined(mpc555) \ |
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192 | || defined(mpc860) || defined(mpc821) || defined(mpc8260)) |
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193 | uint32_t clock_speed; /* Speed of CPU in Hz */ |
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194 | #endif |
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195 | } rtems_cpu_table; |
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196 | |
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197 | /* |
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198 | * Macros to access required entires in the CPU Table are in |
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199 | * the file rtems/system.h. |
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200 | */ |
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201 | |
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202 | /* |
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203 | * This variable is optional. It is used on CPUs on which it is difficult |
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204 | * to generate an "uninitialized" FP context. It is filled in by |
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205 | * _CPU_Initialize and copied into the task's FP context area during |
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206 | * _CPU_Context_Initialize. |
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207 | */ |
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208 | |
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209 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
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210 | |
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211 | /* |
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212 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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213 | * This stack is allocated by the Interrupt Manager and the switch |
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214 | * is performed in _ISR_Handler. These variables contain pointers |
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215 | * to the lowest and highest addresses in the chunk of memory allocated |
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216 | * for the interrupt stack. Since it is unknown whether the stack |
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217 | * grows up or down (in general), this give the CPU dependent |
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218 | * code the option of picking the version it wants to use. |
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219 | * |
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220 | * NOTE: These two variables are required if the macro |
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221 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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222 | */ |
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223 | |
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224 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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225 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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226 | |
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227 | #endif /* ndef ASM */ |
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228 | |
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229 | /* |
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230 | * This defines the number of levels and the mask used to pick those |
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231 | * bits out of a thread mode. |
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232 | */ |
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233 | |
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234 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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235 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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236 | |
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237 | /* |
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238 | * With some compilation systems, it is difficult if not impossible to |
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239 | * call a high-level language routine from assembly language. This |
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240 | * is especially true of commercial Ada compilers and name mangling |
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241 | * C++ ones. This variable can be optionally defined by the CPU porter |
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242 | * and contains the address of the routine _Thread_Dispatch. This |
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243 | * can make it easier to invoke that routine at the end of the interrupt |
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244 | * sequence (if a dispatch is necessary). |
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245 | */ |
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246 | |
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247 | /* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ |
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248 | |
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249 | /* |
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250 | * Nothing prevents the porter from declaring more CPU specific variables. |
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251 | */ |
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252 | |
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253 | #ifndef ASM |
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254 | |
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255 | SCORE_EXTERN struct { |
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256 | uint32_t *Disable_level; |
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257 | void *Stack; |
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258 | volatile boolean *Switch_necessary; |
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259 | boolean *Signal; |
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260 | |
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261 | } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; |
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262 | |
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263 | #endif /* ndef ASM */ |
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264 | |
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265 | /* |
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266 | * The size of the floating point context area. On some CPUs this |
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267 | * will not be a "sizeof" because the format of the floating point |
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268 | * area is not defined -- only the size is. This is usually on |
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269 | * CPUs with a "floating point save context" instruction. |
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270 | */ |
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271 | |
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272 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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273 | |
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274 | /* |
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275 | * (Optional) # of bytes for libmisc/stackchk to check |
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276 | * If not specifed, then it defaults to something reasonable |
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277 | * for most architectures. |
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278 | */ |
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279 | |
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280 | #define CPU_STACK_CHECK_SIZE (128) |
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281 | |
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282 | /* |
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283 | * Amount of extra stack (above minimum stack size) required by |
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284 | * MPCI receive server thread. Remember that in a multiprocessor |
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285 | * system this thread must exist and be able to process all directives. |
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286 | */ |
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287 | |
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288 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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289 | |
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290 | /* |
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291 | * This defines the number of entries in the ISR_Vector_table managed |
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292 | * by RTEMS. |
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293 | */ |
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294 | |
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295 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (PPC_INTERRUPT_MAX) |
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296 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1) |
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297 | |
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298 | /* |
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299 | * This is defined if the port has a special way to report the ISR nesting |
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300 | * level. Most ports maintain the variable _ISR_Nest_level. Note that |
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301 | * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
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302 | * being maintained (e.g. watchdog queues). |
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303 | */ |
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304 | |
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305 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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306 | |
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307 | /* |
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308 | * ISR handler macros |
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309 | */ |
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310 | |
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311 | #define _CPU_Initialize_vectors() |
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312 | |
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313 | /* |
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314 | * Disable all interrupts for an RTEMS critical section. The previous |
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315 | * level is returned in _isr_cookie. |
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316 | */ |
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317 | |
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318 | #ifndef ASM |
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319 | |
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320 | static inline uint32_t _CPU_ISR_Get_level( void ) |
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321 | { |
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322 | register unsigned int msr; |
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323 | _CPU_MSR_GET(msr); |
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324 | if (msr & MSR_EE) return 0; |
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325 | else return 1; |
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326 | } |
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327 | |
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328 | static inline void _CPU_ISR_Set_level( uint32_t level ) |
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329 | { |
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330 | register unsigned int msr; |
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331 | _CPU_MSR_GET(msr); |
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332 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
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333 | msr |= MSR_EE; |
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334 | } |
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335 | else { |
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336 | msr &= ~MSR_EE; |
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337 | } |
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338 | _CPU_MSR_SET(msr); |
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339 | } |
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340 | |
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341 | void BSP_panic(char *); |
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342 | |
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343 | /* Fatal Error manager macros */ |
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344 | |
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345 | /* |
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346 | * This routine copies _error into a known place -- typically a stack |
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347 | * location or a register, optionally disables interrupts, and |
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348 | * halts/stops the CPU. |
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349 | */ |
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350 | |
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351 | void _BSP_Fatal_error(unsigned int); |
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352 | |
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353 | #define _CPU_Fatal_halt( _error ) \ |
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354 | _BSP_Fatal_error(_error) |
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355 | |
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356 | /* end of Fatal Error manager macros */ |
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357 | |
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358 | /* |
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359 | * Until all new-exception processing BSPs have fixed |
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360 | * PR288, we let the good BSPs pass |
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361 | * |
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362 | * PPC_BSP_HAS_FIXED_PR288 |
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363 | * |
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364 | * in SPRG0 and let _CPU_Initialize assert this. |
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365 | */ |
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366 | |
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367 | #define PPC_BSP_HAS_FIXED_PR288 0x600dbabe |
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368 | |
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369 | #endif /* ASM */ |
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370 | |
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371 | #ifdef __cplusplus |
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372 | } |
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373 | #endif |
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374 | |
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375 | #endif |
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