source: rtems/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h @ 4a0d87e

4.104.114.84.95
Last change on this file since 4a0d87e was 4a0d87e, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 18, 2002 at 8:54:19 PM

2002-04-18 Ralf Corsepius <corsepiu@…>

  • asm.h: Include cpuopts.h instead of targopts.h.
  • rtems/new-exceptions/cpu.h: Relocated from libbsp/powerpc/support/new_exception_processing/rtems/score/cpu.h
  • rtems/old-exceptions/cpu.h: Relocated from c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/cpu.h
  • rtems/powerpc/registers.h: Relocated and renamed from libcpu/powerpc/shared/include/cpu.h.
  • rtems/score/cpu.h: New.
  • Makefile.am: Reflect changes above.
  • Property mode set to 100644
File size: 31.6 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
7 *  Surrey Satellite Technology Limited (SSTL), 2001
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
25 *
26 *  COPYRIGHT (c) 1989-1997.
27 *  On-Line Applications Research Corporation (OAR).
28 *
29 *  The license and distribution terms for this file may be found in
30 *  the file LICENSE in this distribution or at
31 *  http://www.OARcorp.com/rtems/license.html.
32 *
33 *  $Id$
34 */
35
36#ifndef __CPU_h
37#define __CPU_h
38
39#ifndef _rtems_score_cpu_h
40#error "You should include <rtems/score/cpu.h>"
41#endif
42
43#include <rtems/powerpc/registers.h>
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49/* conditional compilation parameters */
50
51/*
52 *  Should the calls to _Thread_Enable_dispatch be inlined?
53 *
54 *  If TRUE, then they are inlined.
55 *  If FALSE, then a subroutine call is made.
56 *
57 *  Basically this is an example of the classic trade-off of size
58 *  versus speed.  Inlining the call (TRUE) typically increases the
59 *  size of RTEMS while speeding up the enabling of dispatching.
60 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
61 *  only be 0 or 1 unless you are in an interrupt handler and that
62 *  interrupt handler invokes the executive.]  When not inlined
63 *  something calls _Thread_Enable_dispatch which in turns calls
64 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
65 *  one subroutine call is avoided entirely.]
66 */
67
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/*
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 */
87
88#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
89
90/*
91 *  Does RTEMS manage a dedicated interrupt stack in software?
92 *
93 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
94 *  If FALSE, nothing is done.
95 *
96 *  If the CPU supports a dedicated interrupt stack in hardware,
97 *  then it is generally the responsibility of the BSP to allocate it
98 *  and set it up.
99 *
100 *  If the CPU does not support a dedicated interrupt stack, then
101 *  the porter has two options: (1) execute interrupts on the
102 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
103 *  interrupt stack.
104 *
105 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
106 *
107 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
108 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
109 *  possible that both are FALSE for a particular CPU.  Although it
110 *  is unclear what that would imply about the interrupt processing
111 *  procedure on that CPU.
112 */
113
114#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
115
116/*
117 *  Does this CPU have hardware support for a dedicated interrupt stack?
118 *
119 *  If TRUE, then it must be installed during initialization.
120 *  If FALSE, then no installation is performed.
121 *
122 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
123 *
124 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
125 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
126 *  possible that both are FALSE for a particular CPU.  Although it
127 *  is unclear what that would imply about the interrupt processing
128 *  procedure on that CPU.
129 */
130
131#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
132
133/*
134 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
135 *
136 *  If TRUE, then the memory is allocated during initialization.
137 *  If FALSE, then the memory is allocated during initialization.
138 *
139 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
140 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
141 */
142
143#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
144
145/*
146 *  Does the RTEMS invoke the user's ISR with the vector number and
147 *  a pointer to the saved interrupt frame (1) or just the vector
148 *  number (0)?
149 */
150
151#define CPU_ISR_PASSES_FRAME_POINTER 0
152
153/*
154 *  Does the CPU have hardware floating point?
155 *
156 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
157 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
158 *
159 *  If there is a FP coprocessor such as the i387 or mc68881, then
160 *  the answer is TRUE.
161 *
162 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
163 *  It indicates whether or not this CPU model has FP support.  For
164 *  example, it would be possible to have an i386_nofp CPU model
165 *  which set this to false to indicate that you have an i386 without
166 *  an i387 and wish to leave floating point support out of RTEMS.
167 */
168
169#if ( PPC_HAS_FPU == 1 )
170#define CPU_HARDWARE_FP     TRUE
171#else
172#define CPU_HARDWARE_FP     FALSE
173#endif
174
175/*
176 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
177 *
178 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
179 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
180 *
181 *  So far, the only CPU in which this option has been used is the
182 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
183 *  floating point registers to perform integer multiplies.  If
184 *  a function which you would not think utilize the FP unit DOES,
185 *  then one can not easily predict which tasks will use the FP hardware.
186 *  In this case, this option should be TRUE.
187 *
188 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
189 */
190
191#define CPU_ALL_TASKS_ARE_FP     FALSE
192
193/*
194 *  Should the IDLE task have a floating point context?
195 *
196 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
197 *  and it has a floating point context which is switched in and out.
198 *  If FALSE, then the IDLE task does not have a floating point context.
199 *
200 *  Setting this to TRUE negatively impacts the time required to preempt
201 *  the IDLE task from an interrupt because the floating point context
202 *  must be saved as part of the preemption.
203 */
204
205#define CPU_IDLE_TASK_IS_FP      FALSE
206
207/*
208 *  Should the saving of the floating point registers be deferred
209 *  until a context switch is made to another different floating point
210 *  task?
211 *
212 *  If TRUE, then the floating point context will not be stored until
213 *  necessary.  It will remain in the floating point registers and not
214 *  disturned until another floating point task is switched to.
215 *
216 *  If FALSE, then the floating point context is saved when a floating
217 *  point task is switched out and restored when the next floating point
218 *  task is restored.  The state of the floating point registers between
219 *  those two operations is not specified.
220 *
221 *  If the floating point context does NOT have to be saved as part of
222 *  interrupt dispatching, then it should be safe to set this to TRUE.
223 *
224 *  Setting this flag to TRUE results in using a different algorithm
225 *  for deciding when to save and restore the floating point context.
226 *  The deferred FP switch algorithm minimizes the number of times
227 *  the FP context is saved and restored.  The FP context is not saved
228 *  until a context switch is made to another, different FP task.
229 *  Thus in a system with only one FP task, the FP context will never
230 *  be saved or restored.
231 */
232/*
233 *  ACB Note:  This could make debugging tricky..
234 */
235
236#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
237
238/*
239 *  Does this port provide a CPU dependent IDLE task implementation?
240 *
241 *  If TRUE, then the routine _CPU_Thread_Idle_body
242 *  must be provided and is the default IDLE thread body instead of
243 *  _CPU_Thread_Idle_body.
244 *
245 *  If FALSE, then use the generic IDLE thread body if the BSP does
246 *  not provide one.
247 *
248 *  This is intended to allow for supporting processors which have
249 *  a low power or idle mode.  When the IDLE thread is executed, then
250 *  the CPU can be powered down.
251 *
252 *  The order of precedence for selecting the IDLE thread body is:
253 *
254 *    1.  BSP provided
255 *    2.  CPU dependent (if provided)
256 *    3.  generic (if no BSP and no CPU dependent)
257 */
258
259#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
260
261
262/*
263 *  Does the stack grow up (toward higher addresses) or down
264 *  (toward lower addresses)?
265 *
266 *  If TRUE, then the grows upward.
267 *  If FALSE, then the grows toward smaller addresses.
268 */
269
270#define CPU_STACK_GROWS_UP               FALSE
271
272/*
273 *  The following is the variable attribute used to force alignment
274 *  of critical RTEMS structures.  On some processors it may make
275 *  sense to have these aligned on tighter boundaries than
276 *  the minimum requirements of the compiler in order to have as
277 *  much of the critical data area as possible in a cache line.
278 *
279 *  The placement of this macro in the declaration of the variables
280 *  is based on the syntactically requirements of the GNU C
281 *  "__attribute__" extension.  For example with GNU C, use
282 *  the following to force a structures to a 32 byte boundary.
283 *
284 *      __attribute__ ((aligned (32)))
285 *
286 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
287 *         To benefit from using this, the data must be heavily
288 *         used so it will stay in the cache and used frequently enough
289 *         in the executive to justify turning this on.
290 */
291
292#define CPU_STRUCTURE_ALIGNMENT \
293  __attribute__ ((aligned (PPC_CACHE_ALIGNMENT)))
294
295/*
296 *  Define what is required to specify how the network to host conversion
297 *  routines are handled.
298 */
299
300#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
301#define CPU_BIG_ENDIAN                           TRUE
302#define CPU_LITTLE_ENDIAN                        FALSE
303
304
305/*
306 *  Processor defined structures
307 *
308 *  Examples structures include the descriptor tables from the i386
309 *  and the processor control structure on the i960ca.
310 */
311
312/* may need to put some structures here.  */
313
314/*
315 * Contexts
316 *
317 *  Generally there are 2 types of context to save.
318 *     1. Interrupt registers to save
319 *     2. Task level registers to save
320 *
321 *  This means we have the following 3 context items:
322 *     1. task level context stuff::  Context_Control
323 *     2. floating point task stuff:: Context_Control_fp
324 *     3. special interrupt level context :: Context_Control_interrupt
325 *
326 *  On some processors, it is cost-effective to save only the callee
327 *  preserved registers during a task context switch.  This means
328 *  that the ISR code needs to save those registers which do not
329 *  persist across function calls.  It is not mandatory to make this
330 *  distinctions between the caller/callee saves registers for the
331 *  purpose of minimizing context saved during task switch and on interrupts.
332 *  If the cost of saving extra registers is minimal, simplicity is the
333 *  choice.  Save the same context on interrupt entry as for tasks in
334 *  this case.
335 *
336 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
337 *  care should be used in designing the context area.
338 *
339 *  On some CPUs with hardware floating point support, the Context_Control_fp
340 *  structure will not be used or it simply consist of an array of a
341 *  fixed number of bytes.   This is done when the floating point context
342 *  is dumped by a "FP save context" type instruction and the format
343 *  is not really defined by the CPU.  In this case, there is no need
344 *  to figure out the exact format -- only the size.  Of course, although
345 *  this is enough information for RTEMS, it is probably not enough for
346 *  a debugger such as gdb.  But that is another problem.
347 */
348
349#ifndef ASM
350
351typedef struct {
352    unsigned32 gpr1;    /* Stack pointer for all */
353    unsigned32 gpr2;    /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */
354    unsigned32 gpr13;   /* First non volatile PowerOpen, section ptr SVR4/EABI */
355    unsigned32 gpr14;   /* Non volatile for all */
356    unsigned32 gpr15;   /* Non volatile for all */
357    unsigned32 gpr16;   /* Non volatile for all */
358    unsigned32 gpr17;   /* Non volatile for all */
359    unsigned32 gpr18;   /* Non volatile for all */
360    unsigned32 gpr19;   /* Non volatile for all */
361    unsigned32 gpr20;   /* Non volatile for all */
362    unsigned32 gpr21;   /* Non volatile for all */
363    unsigned32 gpr22;   /* Non volatile for all */
364    unsigned32 gpr23;   /* Non volatile for all */
365    unsigned32 gpr24;   /* Non volatile for all */
366    unsigned32 gpr25;   /* Non volatile for all */
367    unsigned32 gpr26;   /* Non volatile for all */
368    unsigned32 gpr27;   /* Non volatile for all */
369    unsigned32 gpr28;   /* Non volatile for all */
370    unsigned32 gpr29;   /* Non volatile for all */
371    unsigned32 gpr30;   /* Non volatile for all */
372    unsigned32 gpr31;   /* Non volatile for all */
373    unsigned32 cr;      /* PART of the CR is non volatile for all */
374    unsigned32 pc;      /* Program counter/Link register */
375    unsigned32 msr;     /* Initial interrupt level */
376} Context_Control;
377
378typedef struct {
379    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
380     * procedure calls.  However, this would mean that the interrupt
381     * frame had to hold f0-f13, and the fpscr.  And as the majority
382     * of tasks will not have an FP context, we will save the whole
383     * context here.
384     */
385#if (PPC_HAS_DOUBLE == 1)
386    double      f[32];
387    double      fpscr;
388#else
389    float       f[32];
390    float       fpscr;
391#endif
392} Context_Control_fp;
393
394typedef struct CPU_Interrupt_frame {
395    unsigned32 stacklink;       /* Ensure this is a real frame (also reg1 save) */
396    unsigned32 calleeLr;        /* link register used by callees: SVR4/EABI */
397  /* This is what is left out of the primary contexts */
398    unsigned32 gpr0;
399    unsigned32 gpr2;            /* play safe */
400    unsigned32 gpr3;
401    unsigned32 gpr4;
402    unsigned32 gpr5;
403    unsigned32 gpr6;
404    unsigned32 gpr7;
405    unsigned32 gpr8;
406    unsigned32 gpr9;
407    unsigned32 gpr10;
408    unsigned32 gpr11;
409    unsigned32 gpr12;
410    unsigned32 gpr13;   /* Play safe */
411    unsigned32 gpr28;   /* For internal use by the IRQ handler */
412    unsigned32 gpr29;   /* For internal use by the IRQ handler */
413    unsigned32 gpr30;   /* For internal use by the IRQ handler */
414    unsigned32 gpr31;   /* For internal use by the IRQ handler */
415    unsigned32 cr;      /* Bits of this are volatile, so no-one may save */
416    unsigned32 ctr;
417    unsigned32 xer;
418    unsigned32 lr;
419    unsigned32 pc;
420    unsigned32 msr;
421    unsigned32 pad[3];
422} CPU_Interrupt_frame;
423 
424/*
425 *  The following table contains the information required to configure
426 *  the PowerPC processor specific parameters.
427 */
428
429typedef struct {
430  void       (*pretasking_hook)( void );
431  void       (*predriver_hook)( void );
432  void       (*postdriver_hook)( void );
433  void       (*idle_task)( void );
434  boolean      do_zero_of_workspace;
435  unsigned32   idle_task_stack_size;
436  unsigned32   interrupt_stack_size;
437  unsigned32   extra_mpci_receive_server_stack;
438  void *     (*stack_allocate_hook)( unsigned32 );
439  void       (*stack_free_hook)( void* );
440  /* end of fields required on all CPUs */
441
442  unsigned32   clicks_per_usec;        /* Timer clicks per microsecond */
443  boolean      exceptions_in_RAM;     /* TRUE if in RAM */
444
445#if (defined(ppc403) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
446  unsigned32   serial_per_sec;         /* Serial clocks per second */
447  boolean      serial_external_clock;
448  boolean      serial_xon_xoff;
449  boolean      serial_cts_rts;
450  unsigned32   serial_rate;
451  unsigned32   timer_average_overhead; /* Average overhead of timer in ticks */
452  unsigned32   timer_least_valid;      /* Least valid number from timer      */
453  boolean      timer_internal_clock;   /* TRUE, when timer runs with CPU clk */
454#endif
455
456#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
457  unsigned32   clock_speed;            /* Speed of CPU in Hz */
458#endif
459}   rtems_cpu_table;
460
461/*
462 *  Macros to access required entires in the CPU Table are in
463 *  the file rtems/system.h.
464 */
465
466/*
467 *  Macros to access PowerPC MPC750 specific additions to the CPU Table
468 */
469
470#define rtems_cpu_configuration_get_clicks_per_usec() \
471   (_CPU_Table.clicks_per_usec)
472
473#define rtems_cpu_configuration_get_exceptions_in_ram() \
474   (_CPU_Table.exceptions_in_RAM)
475
476/*
477 *  This variable is optional.  It is used on CPUs on which it is difficult
478 *  to generate an "uninitialized" FP context.  It is filled in by
479 *  _CPU_Initialize and copied into the task's FP context area during
480 *  _CPU_Context_Initialize.
481 */
482
483/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
484
485/*
486 *  On some CPUs, RTEMS supports a software managed interrupt stack.
487 *  This stack is allocated by the Interrupt Manager and the switch
488 *  is performed in _ISR_Handler.  These variables contain pointers
489 *  to the lowest and highest addresses in the chunk of memory allocated
490 *  for the interrupt stack.  Since it is unknown whether the stack
491 *  grows up or down (in general), this give the CPU dependent
492 *  code the option of picking the version it wants to use.
493 *
494 *  NOTE: These two variables are required if the macro
495 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
496 */
497
498SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
499SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
500
501#endif /* ndef ASM */
502
503/*
504 *  This defines the number of levels and the mask used to pick those
505 *  bits out of a thread mode.
506 */
507
508#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
509#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
510
511/*
512 *  With some compilation systems, it is difficult if not impossible to
513 *  call a high-level language routine from assembly language.  This
514 *  is especially true of commercial Ada compilers and name mangling
515 *  C++ ones.  This variable can be optionally defined by the CPU porter
516 *  and contains the address of the routine _Thread_Dispatch.  This
517 *  can make it easier to invoke that routine at the end of the interrupt
518 *  sequence (if a dispatch is necessary).
519 */
520
521/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
522
523/*
524 *  Nothing prevents the porter from declaring more CPU specific variables.
525 */
526
527#ifndef ASM
528 
529SCORE_EXTERN struct {
530  unsigned32 *Disable_level;
531  void *Stack;
532  volatile boolean *Switch_necessary;
533  boolean *Signal;
534
535} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
536
537#endif /* ndef ASM */
538
539/*
540 *  The size of the floating point context area.  On some CPUs this
541 *  will not be a "sizeof" because the format of the floating point
542 *  area is not defined -- only the size is.  This is usually on
543 *  CPUs with a "floating point save context" instruction.
544 */
545
546#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
547
548/*
549 * (Optional) # of bytes for libmisc/stackchk to check
550 * If not specifed, then it defaults to something reasonable
551 * for most architectures.
552 */
553
554#define CPU_STACK_CHECK_SIZE    (128)
555
556/*
557 *  Amount of extra stack (above minimum stack size) required by
558 *  MPCI receive server thread.  Remember that in a multiprocessor
559 *  system this thread must exist and be able to process all directives.
560 */
561
562#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
563
564/*
565 *  This defines the number of entries in the ISR_Vector_table managed
566 *  by RTEMS.
567 */
568
569#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (PPC_INTERRUPT_MAX)
570#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (PPC_INTERRUPT_MAX - 1)
571
572/*
573 *  This is defined if the port has a special way to report the ISR nesting
574 *  level.  Most ports maintain the variable _ISR_Nest_level.
575 */
576
577#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
578
579/*
580 *  Should be large enough to run all RTEMS tests.  This insures
581 *  that a "reasonable" small application should not have any problems.
582 */
583
584#define CPU_STACK_MINIMUM_SIZE          (1024*8)
585
586/*
587 *  CPU's worst alignment requirement for data types on a byte boundary.  This
588 *  alignment does not take into account the requirements for the stack.
589 */
590
591#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
592
593/*
594 *  This number corresponds to the byte alignment requirement for the
595 *  heap handler.  This alignment requirement may be stricter than that
596 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
597 *  common for the heap to follow the same alignment requirement as
598 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
599 *  then this should be set to CPU_ALIGNMENT.
600 *
601 *  NOTE:  This does not have to be a power of 2.  It does have to
602 *         be greater or equal to than CPU_ALIGNMENT.
603 */
604
605#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
606
607/*
608 *  This number corresponds to the byte alignment requirement for memory
609 *  buffers allocated by the partition manager.  This alignment requirement
610 *  may be stricter than that for the data types alignment specified by
611 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
612 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
613 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
614 *
615 *  NOTE:  This does not have to be a power of 2.  It does have to
616 *         be greater or equal to than CPU_ALIGNMENT.
617 */
618
619#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
620
621/*
622 *  This number corresponds to the byte alignment requirement for the
623 *  stack.  This alignment requirement may be stricter than that for the
624 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
625 *  is strict enough for the stack, then this should be set to 0.
626 *
627 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
628 */
629
630#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
631
632/*
633 * Needed for Interrupt stack
634 */
635#define CPU_MINIMUM_STACK_FRAME_SIZE 8
636
637
638/*
639 *  ISR handler macros
640 */
641
642#define _CPU_Initialize_vectors()
643
644/*
645 *  Disable all interrupts for an RTEMS critical section.  The previous
646 *  level is returned in _isr_cookie.
647 */
648
649#ifndef ASM
650 
651static inline unsigned32 _CPU_ISR_Get_level( void )
652{
653  register unsigned int msr;
654  _CPU_MSR_GET(msr);
655  if (msr & MSR_EE) return 0;
656  else  return 1;
657}
658
659static inline void _CPU_ISR_Set_level( unsigned32 level )
660{
661  register unsigned int msr;
662  _CPU_MSR_GET(msr);
663  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
664    msr |= MSR_EE;
665  }
666  else {
667    msr &= ~MSR_EE;
668  }
669  _CPU_MSR_SET(msr);
670}
671 
672#define _CPU_ISR_install_vector(irq, new, old) {BSP_panic("_CPU_ISR_install_vector called\n");}
673
674/* Context handler macros */
675
676/*
677 *  Initialize the context to a state suitable for starting a
678 *  task after a context restore operation.  Generally, this
679 *  involves:
680 *
681 *     - setting a starting address
682 *     - preparing the stack
683 *     - preparing the stack and frame pointers
684 *     - setting the proper interrupt level in the context
685 *     - initializing the floating point context
686 *
687 *  This routine generally does not set any unnecessary register
688 *  in the context.  The state of the "general data" registers is
689 *  undefined at task start time.
690 *
691 *  NOTE:  Implemented as a subroutine for the SPARC port.
692 */
693
694void _CPU_Context_Initialize(
695  Context_Control  *the_context,
696  unsigned32       *stack_base,
697  unsigned32        size,
698  unsigned32        new_level,
699  void             *entry_point,
700  boolean           is_fp
701);
702
703/*
704 *  This routine is responsible for somehow restarting the currently
705 *  executing task.  If you are lucky, then all that is necessary
706 *  is restoring the context.  Otherwise, there will need to be
707 *  a special assembly routine which does something special in this
708 *  case.  Context_Restore should work most of the time.  It will
709 *  not work if restarting self conflicts with the stack frame
710 *  assumptions of restoring a context.
711 */
712
713#define _CPU_Context_Restart_self( _the_context ) \
714   _CPU_Context_restore( (_the_context) );
715
716/*
717 *  The purpose of this macro is to allow the initial pointer into
718 *  a floating point context area (used to save the floating point
719 *  context) to be at an arbitrary place in the floating point
720 *  context area.
721 *
722 *  This is necessary because some FP units are designed to have
723 *  their context saved as a stack which grows into lower addresses.
724 *  Other FP units can be saved by simply moving registers into offsets
725 *  from the base of the context area.  Finally some FP units provide
726 *  a "dump context" instruction which could fill in from high to low
727 *  or low to high based on the whim of the CPU designers.
728 */
729
730#define _CPU_Context_Fp_start( _base, _offset ) \
731   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
732
733/*
734 *  This routine initializes the FP context area passed to it to.
735 *  There are a few standard ways in which to initialize the
736 *  floating point context.  The code included for this macro assumes
737 *  that this is a CPU in which a "initial" FP context was saved into
738 *  _CPU_Null_fp_context and it simply copies it to the destination
739 *  context passed to it.
740 *
741 *  Other models include (1) not doing anything, and (2) putting
742 *  a "null FP status word" in the correct place in the FP context.
743 */
744
745#define _CPU_Context_Initialize_fp( _destination ) \
746  { \
747   ((Context_Control_fp *) *((void **) _destination))->fpscr = PPC_INIT_FPSCR; \
748  }
749
750/* end of Context handler macros */
751
752/* Fatal Error manager macros */
753
754/*
755 *  This routine copies _error into a known place -- typically a stack
756 *  location or a register, optionally disables interrupts, and
757 *  halts/stops the CPU.
758 */
759
760#define _CPU_Fatal_halt( _error ) \
761  _BSP_Fatal_error(_error)
762
763/* end of Fatal Error manager macros */
764
765/* Bitfield handler macros */
766
767/*
768 *  This routine sets _output to the bit number of the first bit
769 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
770 *  This type may be either 16 or 32 bits wide although only the 16
771 *  least significant bits will be used.
772 *
773 *  There are a number of variables in using a "find first bit" type
774 *  instruction.
775 *
776 *    (1) What happens when run on a value of zero?
777 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
778 *    (3) The numbering may be zero or one based.
779 *    (4) The "find first bit" instruction may search from MSB or LSB.
780 *
781 *  RTEMS guarantees that (1) will never happen so it is not a concern.
782 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
783 *  _CPU_Priority_Bits_index().  These three form a set of routines
784 *  which must logically operate together.  Bits in the _value are
785 *  set and cleared based on masks built by _CPU_Priority_mask().
786 *  The basic major and minor values calculated by _Priority_Major()
787 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
788 *  to properly range between the values returned by the "find first bit"
789 *  instruction.  This makes it possible for _Priority_Get_highest() to
790 *  calculate the major and directly index into the minor table.
791 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
792 *  is the first bit found.
793 *
794 *  This entire "find first bit" and mapping process depends heavily
795 *  on the manner in which a priority is broken into a major and minor
796 *  components with the major being the 4 MSB of a priority and minor
797 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
798 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
799 *  to the lowest priority.
800 *
801 *  If your CPU does not have a "find first bit" instruction, then
802 *  there are ways to make do without it.  Here are a handful of ways
803 *  to implement this in software:
804 *
805 *    - a series of 16 bit test instructions
806 *    - a "binary search using if's"
807 *    - _number = 0
808 *      if _value > 0x00ff
809 *        _value >>=8
810 *        _number = 8;
811 *
812 *      if _value > 0x0000f
813 *        _value >=8
814 *        _number += 4
815 *
816 *      _number += bit_set_table[ _value ]
817 *
818 *    where bit_set_table[ 16 ] has values which indicate the first
819 *      bit set
820 */
821
822#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
823  { \
824    asm volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
825                  "1" ((_value))); \
826  }
827
828/* end of Bitfield handler macros */
829
830/*
831 *  This routine builds the mask which corresponds to the bit fields
832 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
833 *  for that routine.
834 */
835
836#define _CPU_Priority_Mask( _bit_number ) \
837  ( 0x80000000 >> (_bit_number) )
838
839/*
840 *  This routine translates the bit numbers returned by
841 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
842 *  a major or minor component of a priority.  See the discussion
843 *  for that routine.
844 */
845
846#define _CPU_Priority_bits_index( _priority ) \
847  (_priority)
848
849/* end of Priority handler macros */
850
851/* variables */
852
853extern const unsigned32 _CPU_msrs[4];
854
855/* functions */
856
857/*
858 *  _CPU_Initialize
859 *
860 *  This routine performs CPU dependent initialization.
861 */
862
863void _CPU_Initialize(
864  rtems_cpu_table  *cpu_table,
865  void            (*thread_dispatch)
866);
867
868
869/*
870 *  _CPU_Install_interrupt_stack
871 *
872 *  This routine installs the hardware interrupt stack pointer.
873 *
874 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
875 *         is TRUE.
876 */
877
878void _CPU_Install_interrupt_stack( void );
879
880/*
881 *  _CPU_Context_switch
882 *
883 *  This routine switches from the run context to the heir context.
884 */
885
886void _CPU_Context_switch(
887  Context_Control  *run,
888  Context_Control  *heir
889);
890
891/*
892 *  _CPU_Context_restore
893 *
894 *  This routine is generallu used only to restart self in an
895 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
896 *
897 *  NOTE: May be unnecessary to reload some registers.
898 */
899
900void _CPU_Context_restore(
901  Context_Control *new_context
902);
903
904/*
905 *  _CPU_Context_save_fp
906 *
907 *  This routine saves the floating point context passed to it.
908 */
909
910void _CPU_Context_save_fp(
911  void **fp_context_ptr
912);
913
914/*
915 *  _CPU_Context_restore_fp
916 *
917 *  This routine restores the floating point context passed to it.
918 */
919
920void _CPU_Context_restore_fp(
921  void **fp_context_ptr
922);
923
924void _CPU_Fatal_error(
925  unsigned32 _error
926);
927
928/*  The following routine swaps the endian format of an unsigned int.
929 *  It must be static because it is referenced indirectly.
930 *
931 *  This version will work on any processor, but if there is a better
932 *  way for your CPU PLEASE use it.  The most common way to do this is to:
933 *
934 *     swap least significant two bytes with 16-bit rotate
935 *     swap upper and lower 16-bits
936 *     swap most significant two bytes with 16-bit rotate
937 *
938 *  Some CPUs have special instructions which swap a 32-bit quantity in
939 *  a single instruction (e.g. i486).  It is probably best to avoid
940 *  an "endian swapping control bit" in the CPU.  One good reason is
941 *  that interrupts would probably have to be disabled to insure that
942 *  an interrupt does not try to access the same "chunk" with the wrong
943 *  endian.  Another good reason is that on some CPUs, the endian bit
944 *  endianness for ALL fetches -- both code and data -- so the code
945 *  will be fetched incorrectly.
946 */
947 
948static inline unsigned int CPU_swap_u32(
949  unsigned int value
950)
951{
952  unsigned32 swapped;
953 
954  asm volatile("rlwimi %0,%1,8,24,31;"
955               "rlwimi %0,%1,24,16,23;"
956               "rlwimi %0,%1,8,8,15;"
957               "rlwimi %0,%1,24,0,7;" :
958               "=&r" ((swapped)) : "r" ((value)));
959
960  return( swapped );
961}
962
963#define CPU_swap_u16( value ) \
964  (((value&0xff) << 8) | ((value >> 8)&0xff))
965
966#endif /* ndef ASM */
967
968#ifdef __cplusplus
969}
970#endif
971
972#endif
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