source: rtems/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h @ 334b3c1e

4.104.114.9
Last change on this file since 334b3c1e was 334b3c1e, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 5, 2008 at 1:32:27 PM

2008-08-04 Sebastian Huber <sebastian.huber@…>

  • rtems/new-exceptions/cpu.h: Changed define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER to UINT32_MAX to avoid comparison between signed and unsigned.
  • Property mode set to 100644
File size: 9.9 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the PowerPC
4 *  processor.
5 *
6 *  Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk>
7 *  Surrey Satellite Technology Limited (SSTL), 2001
8 *
9 *  Author:     Andrew Bray <andy@i-cubed.co.uk>
10 *
11 *  COPYRIGHT (c) 1995 by i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Derived from c/src/exec/cpu/no_cpu/cpu.h:
25 *
26 *  COPYRIGHT (c) 1989-2007.
27 *  On-Line Applications Research Corporation (OAR).
28 *
29 *  The license and distribution terms for this file may be found in
30 *  the file LICENSE in this distribution or at
31 *  http://www.rtems.com/license/LICENSE.
32 *
33 *  $Id$
34 */
35
36#ifndef _RTEMS_NEW_EXCEPTIONS_CPU_H
37#define _RTEMS_NEW_EXCEPTIONS_CPU_H
38
39#ifndef _RTEMS_SCORE_CPU_H
40#error "You should include <rtems/score/cpu.h>"
41#endif
42
43#include <rtems/powerpc/registers.h>
44
45#ifdef __cplusplus
46extern "C" {
47#endif
48
49/* conditional compilation parameters */
50
51/*
52 *  Does RTEMS manage a dedicated interrupt stack in software?
53 *
54 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
55 *  If FALSE, nothing is done.
56 *
57 *  If the CPU supports a dedicated interrupt stack in hardware,
58 *  then it is generally the responsibility of the BSP to allocate it
59 *  and set it up.
60 *
61 *  If the CPU does not support a dedicated interrupt stack, then
62 *  the porter has two options: (1) execute interrupts on the
63 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
64 *  interrupt stack.
65 *
66 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
67 *
68 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
69 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
70 *  possible that both are FALSE for a particular CPU.  Although it
71 *  is unclear what that would imply about the interrupt processing
72 *  procedure on that CPU.
73 */
74
75#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
76
77/*
78 *  Does this CPU have hardware support for a dedicated interrupt stack?
79 *
80 *  If TRUE, then it must be installed during initialization.
81 *  If FALSE, then no installation is performed.
82 *
83 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
84 *
85 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
86 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
87 *  possible that both are FALSE for a particular CPU.  Although it
88 *  is unclear what that would imply about the interrupt processing
89 *  procedure on that CPU.
90 */
91
92#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
93
94/*
95 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
96 *
97 *  If TRUE, then the memory is allocated during initialization.
98 *  If FALSE, then the memory is allocated during initialization.
99 *
100 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
101 */
102
103#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
104
105/*
106 *  Does the RTEMS invoke the user's ISR with the vector number and
107 *  a pointer to the saved interrupt frame (1) or just the vector
108 *  number (0)?
109 */
110
111#define CPU_ISR_PASSES_FRAME_POINTER 0
112
113/*
114 *  Should the saving of the floating point registers be deferred
115 *  until a context switch is made to another different floating point
116 *  task?
117 *
118 *  If TRUE, then the floating point context will not be stored until
119 *  necessary.  It will remain in the floating point registers and not
120 *  disturned until another floating point task is switched to.
121 *
122 *  If FALSE, then the floating point context is saved when a floating
123 *  point task is switched out and restored when the next floating point
124 *  task is restored.  The state of the floating point registers between
125 *  those two operations is not specified.
126 *
127 *  If the floating point context does NOT have to be saved as part of
128 *  interrupt dispatching, then it should be safe to set this to TRUE.
129 *
130 *  Setting this flag to TRUE results in using a different algorithm
131 *  for deciding when to save and restore the floating point context.
132 *  The deferred FP switch algorithm minimizes the number of times
133 *  the FP context is saved and restored.  The FP context is not saved
134 *  until a context switch is made to another, different FP task.
135 *  Thus in a system with only one FP task, the FP context will never
136 *  be saved or restored.
137 *
138 *  Note, however that compilers may use floating point registers/
139 *  instructions for optimization or they may save/restore FP registers
140 *  on the stack. You must not use deferred switching in these cases
141 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
142 *  exception.
143 */
144/*
145 *  ACB Note:  This could make debugging tricky..
146 */
147
148/* conservative setting (FALSE); probably doesn't affect performance too much */
149#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
150
151/*
152 *  Processor defined structures required for cpukit/score.
153 */
154
155#ifndef ASM
156 
157/*
158 *  This variable is optional.  It is used on CPUs on which it is difficult
159 *  to generate an "uninitialized" FP context.  It is filled in by
160 *  _CPU_Initialize and copied into the task's FP context area during
161 *  _CPU_Context_Initialize.
162 */
163
164/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
165
166/*
167 *  On some CPUs, RTEMS supports a software managed interrupt stack.
168 *  This stack is allocated by the Interrupt Manager and the switch
169 *  is performed in _ISR_Handler.  These variables contain pointers
170 *  to the lowest and highest addresses in the chunk of memory allocated
171 *  for the interrupt stack.  Since it is unknown whether the stack
172 *  grows up or down (in general), this give the CPU dependent
173 *  code the option of picking the version it wants to use.
174 *
175 *  NOTE: These two variables are required if the macro
176 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
177 */
178
179SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
180SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
181
182#endif /* ndef ASM */
183
184/*
185 *  This defines the number of levels and the mask used to pick those
186 *  bits out of a thread mode.
187 */
188
189#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
190#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
191
192/*
193 *  With some compilation systems, it is difficult if not impossible to
194 *  call a high-level language routine from assembly language.  This
195 *  is especially true of commercial Ada compilers and name mangling
196 *  C++ ones.  This variable can be optionally defined by the CPU porter
197 *  and contains the address of the routine _Thread_Dispatch.  This
198 *  can make it easier to invoke that routine at the end of the interrupt
199 *  sequence (if a dispatch is necessary).
200 */
201
202/* EXTERN void           (*_CPU_Thread_dispatch_pointer)(); */
203
204/*
205 *  Nothing prevents the porter from declaring more CPU specific variables.
206 */
207
208#ifndef ASM
209 
210SCORE_EXTERN struct {
211  uint32_t   *Disable_level;
212  void *Stack;
213  volatile boolean *Switch_necessary;
214  boolean *Signal;
215
216} _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT;
217
218#endif /* ndef ASM */
219
220/*
221 *  The size of the floating point context area.  On some CPUs this
222 *  will not be a "sizeof" because the format of the floating point
223 *  area is not defined -- only the size is.  This is usually on
224 *  CPUs with a "floating point save context" instruction.
225 */
226
227#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
228
229/*
230 * (Optional) # of bytes for libmisc/stackchk to check
231 * If not specifed, then it defaults to something reasonable
232 * for most architectures.
233 */
234
235#define CPU_STACK_CHECK_SIZE    (128)
236
237/*
238 *  Amount of extra stack (above minimum stack size) required by
239 *  MPCI receive server thread.  Remember that in a multiprocessor
240 *  system this thread must exist and be able to process all directives.
241 */
242
243#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
244
245/*
246 *  This defines the number of entries in the ISR_Vector_table managed
247 *  by RTEMS.
248 */
249
250#define CPU_INTERRUPT_NUMBER_OF_VECTORS     (0)
251#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (UINT32_MAX)
252
253/*
254 *  This is defined if the port has a special way to report the ISR nesting
255 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
256 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
257 *  being maintained (e.g. watchdog queues).
258 */
259
260#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
261
262/*
263 *  ISR handler macros
264 */
265
266#define _CPU_Initialize_vectors()
267
268/*
269 *  Disable all interrupts for an RTEMS critical section.  The previous
270 *  level is returned in _isr_cookie.
271 */
272
273#ifndef ASM
274 
275static inline uint32_t   _CPU_ISR_Get_level( void )
276{
277  register unsigned int msr;
278  _CPU_MSR_GET(msr);
279  if (msr & MSR_EE) return 0;
280  else  return 1;
281}
282
283static inline void _CPU_ISR_Set_level( uint32_t   level )
284{
285  register unsigned int msr;
286  _CPU_MSR_GET(msr);
287  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
288    msr |= ppc_interrupt_get_disable_mask();
289  }
290  else {
291    msr &= ~ppc_interrupt_get_disable_mask();
292  }
293  _CPU_MSR_SET(msr);
294}
295 
296void BSP_panic(char *);
297
298/* Fatal Error manager macros */
299
300/*
301 *  This routine copies _error into a known place -- typically a stack
302 *  location or a register, optionally disables interrupts, and
303 *  halts/stops the CPU.
304 */
305
306void _BSP_Fatal_error(unsigned int);
307
308#define _CPU_Fatal_halt( _error ) \
309  _BSP_Fatal_error(_error)
310
311/* end of Fatal Error manager macros */
312
313/*
314 * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug.
315 * Now SPRG0 is devoted to the interrupt disable mask.
316 */
317
318#define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask
319
320#endif /* ASM */
321
322#ifdef __cplusplus
323}
324#endif
325
326#endif
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