[a862d15] | 1 | /* cpu.h |
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| 2 | * |
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| 3 | * This include file contains information pertaining to the PowerPC |
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| 4 | * processor. |
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| 5 | * |
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| 6 | * Modified for MPC8260 Andy Dachs <a.dachs@sstl.co.uk> |
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| 7 | * Surrey Satellite Technology Limited (SSTL), 2001 |
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| 8 | * |
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| 9 | * Author: Andrew Bray <andy@i-cubed.co.uk> |
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| 10 | * |
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| 11 | * COPYRIGHT (c) 1995 by i-cubed ltd. |
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| 12 | * |
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| 13 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 14 | * without any express or implied warranty: |
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| 15 | * permission to use, copy, modify, and distribute this file |
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| 16 | * for any purpose is hereby granted without fee, provided that |
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| 17 | * the above copyright notice and this notice appears in all |
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| 18 | * copies, and that the name of i-cubed limited not be used in |
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| 19 | * advertising or publicity pertaining to distribution of the |
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| 20 | * software without specific, written prior permission. |
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| 21 | * i-cubed limited makes no representations about the suitability |
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| 22 | * of this software for any purpose. |
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| 23 | * |
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| 24 | * Derived from c/src/exec/cpu/no_cpu/cpu.h: |
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| 25 | * |
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[e34ac1f] | 26 | * COPYRIGHT (c) 1989-2007. |
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[a862d15] | 27 | * On-Line Applications Research Corporation (OAR). |
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| 28 | * |
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| 29 | * The license and distribution terms for this file may be found in |
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| 30 | * the file LICENSE in this distribution or at |
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[90e393f] | 31 | * http://www.rtems.com/license/LICENSE. |
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[a862d15] | 32 | * |
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| 33 | * $Id$ |
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| 34 | */ |
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| 35 | |
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[a30a08a] | 36 | #ifndef _RTEMS_NEW_EXCEPTIONS_CPU_H |
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| 37 | #define _RTEMS_NEW_EXCEPTIONS_CPU_H |
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[a862d15] | 38 | |
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[a30a08a] | 39 | #ifndef _RTEMS_SCORE_CPU_H |
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[4a0d87e] | 40 | #error "You should include <rtems/score/cpu.h>" |
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[a862d15] | 41 | #endif |
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| 42 | |
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[4a0d87e] | 43 | #include <rtems/powerpc/registers.h> |
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| 44 | |
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| 45 | #ifdef __cplusplus |
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| 46 | extern "C" { |
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[a862d15] | 47 | #endif |
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| 48 | |
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| 49 | /* conditional compilation parameters */ |
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| 50 | |
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| 51 | /* |
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| 52 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 53 | * |
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| 54 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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| 55 | * If FALSE, nothing is done. |
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| 56 | * |
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| 57 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 58 | * then it is generally the responsibility of the BSP to allocate it |
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| 59 | * and set it up. |
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| 60 | * |
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| 61 | * If the CPU does not support a dedicated interrupt stack, then |
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| 62 | * the porter has two options: (1) execute interrupts on the |
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| 63 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 64 | * interrupt stack. |
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| 65 | * |
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| 66 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 67 | * |
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| 68 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 69 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 70 | * possible that both are FALSE for a particular CPU. Although it |
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| 71 | * is unclear what that would imply about the interrupt processing |
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| 72 | * procedure on that CPU. |
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| 73 | */ |
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| 74 | |
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| 75 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 76 | |
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| 77 | /* |
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| 78 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 79 | * |
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| 80 | * If TRUE, then it must be installed during initialization. |
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| 81 | * If FALSE, then no installation is performed. |
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| 82 | * |
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| 83 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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| 84 | * |
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| 85 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 86 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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| 87 | * possible that both are FALSE for a particular CPU. Although it |
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| 88 | * is unclear what that would imply about the interrupt processing |
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| 89 | * procedure on that CPU. |
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| 90 | */ |
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| 91 | |
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| 92 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 93 | |
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| 94 | /* |
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| 95 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 96 | * |
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| 97 | * If TRUE, then the memory is allocated during initialization. |
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| 98 | * If FALSE, then the memory is allocated during initialization. |
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| 99 | * |
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[5961b4c7] | 100 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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[a862d15] | 101 | */ |
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| 102 | |
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| 103 | #define CPU_ALLOCATE_INTERRUPT_STACK FALSE |
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| 104 | |
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| 105 | /* |
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| 106 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 107 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 108 | * number (0)? |
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| 109 | */ |
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| 110 | |
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| 111 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 112 | |
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| 113 | /* |
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| 114 | * Should the saving of the floating point registers be deferred |
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| 115 | * until a context switch is made to another different floating point |
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| 116 | * task? |
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| 117 | * |
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| 118 | * If TRUE, then the floating point context will not be stored until |
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| 119 | * necessary. It will remain in the floating point registers and not |
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| 120 | * disturned until another floating point task is switched to. |
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| 121 | * |
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| 122 | * If FALSE, then the floating point context is saved when a floating |
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| 123 | * point task is switched out and restored when the next floating point |
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| 124 | * task is restored. The state of the floating point registers between |
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| 125 | * those two operations is not specified. |
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| 126 | * |
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| 127 | * If the floating point context does NOT have to be saved as part of |
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| 128 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 129 | * |
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| 130 | * Setting this flag to TRUE results in using a different algorithm |
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| 131 | * for deciding when to save and restore the floating point context. |
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| 132 | * The deferred FP switch algorithm minimizes the number of times |
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| 133 | * the FP context is saved and restored. The FP context is not saved |
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| 134 | * until a context switch is made to another, different FP task. |
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| 135 | * Thus in a system with only one FP task, the FP context will never |
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| 136 | * be saved or restored. |
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[19131e97] | 137 | * |
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| 138 | * Note, however that compilers may use floating point registers/ |
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| 139 | * instructions for optimization or they may save/restore FP registers |
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| 140 | * on the stack. You must not use deferred switching in these cases |
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| 141 | * and on the PowerPC attempting to do so will raise a "FP unavailable" |
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| 142 | * exception. |
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[a862d15] | 143 | */ |
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| 144 | /* |
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| 145 | * ACB Note: This could make debugging tricky.. |
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| 146 | */ |
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| 147 | |
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[19131e97] | 148 | /* conservative setting (FALSE); probably doesn't affect performance too much */ |
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| 149 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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[a862d15] | 150 | |
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| 151 | /* |
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[9428e23] | 152 | * Processor defined structures required for cpukit/score. |
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[a862d15] | 153 | */ |
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| 154 | |
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| 155 | #ifndef ASM |
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| 156 | |
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| 157 | /* |
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| 158 | * This variable is optional. It is used on CPUs on which it is difficult |
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| 159 | * to generate an "uninitialized" FP context. It is filled in by |
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| 160 | * _CPU_Initialize and copied into the task's FP context area during |
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| 161 | * _CPU_Context_Initialize. |
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| 162 | */ |
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| 163 | |
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| 164 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
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| 165 | |
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| 166 | /* |
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| 167 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
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| 168 | * This stack is allocated by the Interrupt Manager and the switch |
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| 169 | * is performed in _ISR_Handler. These variables contain pointers |
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| 170 | * to the lowest and highest addresses in the chunk of memory allocated |
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| 171 | * for the interrupt stack. Since it is unknown whether the stack |
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| 172 | * grows up or down (in general), this give the CPU dependent |
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| 173 | * code the option of picking the version it wants to use. |
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| 174 | * |
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| 175 | * NOTE: These two variables are required if the macro |
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| 176 | * CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
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| 177 | */ |
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| 178 | |
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| 179 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
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| 180 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
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| 181 | |
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| 182 | #endif /* ndef ASM */ |
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| 183 | |
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| 184 | /* |
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| 185 | * This defines the number of levels and the mask used to pick those |
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| 186 | * bits out of a thread mode. |
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| 187 | */ |
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| 188 | |
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| 189 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
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| 190 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
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| 191 | |
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| 192 | /* |
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| 193 | * With some compilation systems, it is difficult if not impossible to |
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| 194 | * call a high-level language routine from assembly language. This |
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| 195 | * is especially true of commercial Ada compilers and name mangling |
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| 196 | * C++ ones. This variable can be optionally defined by the CPU porter |
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| 197 | * and contains the address of the routine _Thread_Dispatch. This |
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| 198 | * can make it easier to invoke that routine at the end of the interrupt |
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| 199 | * sequence (if a dispatch is necessary). |
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| 200 | */ |
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| 201 | |
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| 202 | /* EXTERN void (*_CPU_Thread_dispatch_pointer)(); */ |
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| 203 | |
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| 204 | /* |
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| 205 | * Nothing prevents the porter from declaring more CPU specific variables. |
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| 206 | */ |
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| 207 | |
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| 208 | #ifndef ASM |
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| 209 | |
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| 210 | SCORE_EXTERN struct { |
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[30b1016] | 211 | uint32_t *Disable_level; |
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[a862d15] | 212 | void *Stack; |
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| 213 | volatile boolean *Switch_necessary; |
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| 214 | boolean *Signal; |
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| 215 | |
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| 216 | } _CPU_IRQ_info CPU_STRUCTURE_ALIGNMENT; |
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| 217 | |
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| 218 | #endif /* ndef ASM */ |
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| 219 | |
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| 220 | /* |
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| 221 | * The size of the floating point context area. On some CPUs this |
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| 222 | * will not be a "sizeof" because the format of the floating point |
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| 223 | * area is not defined -- only the size is. This is usually on |
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| 224 | * CPUs with a "floating point save context" instruction. |
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| 225 | */ |
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| 226 | |
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| 227 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
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| 228 | |
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| 229 | /* |
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| 230 | * (Optional) # of bytes for libmisc/stackchk to check |
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| 231 | * If not specifed, then it defaults to something reasonable |
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| 232 | * for most architectures. |
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| 233 | */ |
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| 234 | |
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| 235 | #define CPU_STACK_CHECK_SIZE (128) |
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| 236 | |
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| 237 | /* |
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| 238 | * Amount of extra stack (above minimum stack size) required by |
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| 239 | * MPCI receive server thread. Remember that in a multiprocessor |
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| 240 | * system this thread must exist and be able to process all directives. |
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| 241 | */ |
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| 242 | |
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| 243 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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| 244 | |
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| 245 | /* |
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| 246 | * This defines the number of entries in the ISR_Vector_table managed |
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| 247 | * by RTEMS. |
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| 248 | */ |
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| 249 | |
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[06aab39] | 250 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS (0) |
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[334b3c1e] | 251 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (UINT32_MAX) |
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[a862d15] | 252 | |
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[75ad7376] | 253 | /* |
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| 254 | * This is defined if the port has a special way to report the ISR nesting |
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[1ede24c] | 255 | * level. Most ports maintain the variable _ISR_Nest_level. Note that |
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| 256 | * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
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| 257 | * being maintained (e.g. watchdog queues). |
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[75ad7376] | 258 | */ |
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| 259 | |
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[1ede24c] | 260 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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[75ad7376] | 261 | |
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[a862d15] | 262 | /* |
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| 263 | * ISR handler macros |
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| 264 | */ |
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| 265 | |
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| 266 | #define _CPU_Initialize_vectors() |
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| 267 | |
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| 268 | /* |
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| 269 | * Disable all interrupts for an RTEMS critical section. The previous |
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| 270 | * level is returned in _isr_cookie. |
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| 271 | */ |
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| 272 | |
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| 273 | #ifndef ASM |
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| 274 | |
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[30b1016] | 275 | static inline uint32_t _CPU_ISR_Get_level( void ) |
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[a862d15] | 276 | { |
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| 277 | register unsigned int msr; |
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| 278 | _CPU_MSR_GET(msr); |
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| 279 | if (msr & MSR_EE) return 0; |
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| 280 | else return 1; |
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| 281 | } |
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| 282 | |
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[30b1016] | 283 | static inline void _CPU_ISR_Set_level( uint32_t level ) |
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[a862d15] | 284 | { |
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| 285 | register unsigned int msr; |
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| 286 | _CPU_MSR_GET(msr); |
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| 287 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
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[3d28361d] | 288 | msr |= ppc_interrupt_get_disable_mask(); |
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[a862d15] | 289 | } |
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| 290 | else { |
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[3d28361d] | 291 | msr &= ~ppc_interrupt_get_disable_mask(); |
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[a862d15] | 292 | } |
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| 293 | _CPU_MSR_SET(msr); |
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| 294 | } |
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| 295 | |
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[1c3ea41] | 296 | void BSP_panic(char *); |
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[a862d15] | 297 | |
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| 298 | /* Fatal Error manager macros */ |
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| 299 | |
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| 300 | /* |
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| 301 | * This routine copies _error into a known place -- typically a stack |
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| 302 | * location or a register, optionally disables interrupts, and |
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| 303 | * halts/stops the CPU. |
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| 304 | */ |
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| 305 | |
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[1c3ea41] | 306 | void _BSP_Fatal_error(unsigned int); |
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| 307 | |
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[a862d15] | 308 | #define _CPU_Fatal_halt( _error ) \ |
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| 309 | _BSP_Fatal_error(_error) |
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| 310 | |
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| 311 | /* end of Fatal Error manager macros */ |
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| 312 | |
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| 313 | /* |
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[767cdd8] | 314 | * SPRG0 was previously used to make sure that the BSP fixed the PR288 bug. |
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| 315 | * Now SPRG0 is devoted to the interrupt disable mask. |
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[a862d15] | 316 | */ |
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| 317 | |
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[767cdd8] | 318 | #define PPC_BSP_HAS_FIXED_PR288 ppc_this_is_now_the_interrupt_disable_mask |
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[1ede24c] | 319 | |
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[1b6e9b7] | 320 | #endif /* ASM */ |
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[a862d15] | 321 | |
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| 322 | #ifdef __cplusplus |
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| 323 | } |
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| 324 | #endif |
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| 325 | |
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| 326 | #endif |
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