source: rtems/cpukit/score/cpu/powerpc/rtems/asm.h @ 9da42fb

4.115
Last change on this file since 9da42fb was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/03/12 at 15:09:24

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1/**
2 * @file rtems/asm.h
3 *
4 *  This include file attempts to address the problems
5 *  caused by incompatible flavors of assemblers and
6 *  toolsets.  It primarily addresses variations in the
7 *  use of leading underscores on symbols and the requirement
8 *  that register names be preceded by a %.
9 */
10
11/*
12 *  NOTE: The spacing in the use of these macros
13 *        is critical to them working as advertised.
14 *
15 *  COPYRIGHT:
16 *
17 *  This file is based on similar code found in newlib available
18 *  from ftp.cygnus.com.  The file which was used had no copyright
19 *  notice.  This file is freely distributable as long as the source
20 *  of the file is noted.  This file is:
21 *
22 *  COPYRIGHT (c) 1995.
23 *  i-cubed ltd.
24 *
25 *  COPYRIGHT (c) 1994.
26 *  On-Line Applications Research Corporation (OAR).
27 */
28
29#ifndef _RTEMS_ASM_H
30#define _RTEMS_ASM_H
31
32/*
33 *  Indicate we are in an assembly file and get the basic CPU definitions.
34 */
35
36#ifndef ASM
37#define ASM
38#endif
39#include <rtems/score/cpuopts.h>
40#include <rtems/score/powerpc.h>
41
42/*
43 *  Recent versions of GNU cpp define variables which indicate the
44 *  need for underscores and percents.  If not using GNU cpp or
45 *  the version does not support this, then you will obviously
46 *  have to define these as appropriate.
47 */
48
49#ifndef __USER_LABEL_PREFIX__
50#define __USER_LABEL_PREFIX__
51#endif
52
53#ifndef __REGISTER_PREFIX__
54#define __REGISTER_PREFIX__
55#endif
56
57#ifndef __FLOAT_REGISTER_PREFIX__
58#define __FLOAT_REGISTER_PREFIX__  __REGISTER_PREFIX__
59#endif
60
61#ifndef __PROC_LABEL_PREFIX__
62#define __PROC_LABEL_PREFIX__  __USER_LABEL_PREFIX__
63#endif
64
65#include <rtems/concat.h>
66
67/* Use the right prefix for global labels.  */
68
69#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
70
71/* Use the right prefix for procedure labels.  */
72
73#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
74
75/* Use the right prefix for registers.  */
76
77#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
78
79/* Use the right prefix for floating point registers.  */
80
81#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
82
83/*
84 *  define macros for all of the registers on this CPU
85 *
86 *  EXAMPLE:     #define d0 REG (d0)
87 */
88#define r0 REG(0)
89#define r1 REG(1)
90#define r2 REG(2)
91#define r3 REG(3)
92#define r4 REG(4)
93#define r5 REG(5)
94#define r6 REG(6)
95#define r7 REG(7)
96#define r8 REG(8)
97#define r9 REG(9)
98#define r10 REG(10)
99#define r11 REG(11)
100#define r12 REG(12)
101#define r13 REG(13)
102#define r14 REG(14)
103#define r15 REG(15)
104#define r16 REG(16)
105#define r17 REG(17)
106#define r18 REG(18)
107#define r19 REG(19)
108#define r20 REG(20)
109#define r21 REG(21)
110#define r22 REG(22)
111#define r23 REG(23)
112#define r24 REG(24)
113#define r25 REG(25)
114#define r26 REG(26)
115#define r27 REG(27)
116#define r28 REG(28)
117#define r29 REG(29)
118#define r30 REG(30)
119#define r31 REG(31)
120#define f0 FREG(0)
121#define f1 FREG(1)
122#define f2 FREG(2)
123#define f3 FREG(3)
124#define f4 FREG(4)
125#define f5 FREG(5)
126#define f6 FREG(6)
127#define f7 FREG(7)
128#define f8 FREG(8)
129#define f9 FREG(9)
130#define f10 FREG(10)
131#define f11 FREG(11)
132#define f12 FREG(12)
133#define f13 FREG(13)
134#define f14 FREG(14)
135#define f15 FREG(15)
136#define f16 FREG(16)
137#define f17 FREG(17)
138#define f18 FREG(18)
139#define f19 FREG(19)
140#define f20 FREG(20)
141#define f21 FREG(21)
142#define f22 FREG(22)
143#define f23 FREG(23)
144#define f24 FREG(24)
145#define f25 FREG(25)
146#define f26 FREG(26)
147#define f27 FREG(27)
148#define f28 FREG(28)
149#define f29 FREG(29)
150#define f30 FREG(30)
151#define f31 FREG(31)
152
153/*
154 * Some special purpose registers (SPRs).
155 */
156#define srr0    0x01a
157#define srr1    0x01b
158#define srr2    0x3de /* IBM 400 series only */
159#define srr3    0x3df /* IBM 400 series only */
160#define csrr0   58 /* Book E */
161#define csrr1   59 /* Book E */
162#define mcsrr0  570 /* e500 */
163#define mcsrr1  571 /* e500 */
164#define dsrr0   574 /* e200 */
165#define dsrr1   575 /* e200 */
166
167#define sprg0   0x110
168#define sprg1   0x111
169#define sprg2   0x112
170#define sprg3   0x113
171#define sprg4   276
172#define sprg5   277
173#define sprg6   278
174#define sprg7   279
175
176#define usprg0  256
177
178#define dar     0x013   /* Data Address Register */
179#define dec             0x016   /* Decrementer Register */
180
181#if defined(ppc403) || defined(ppc405)
182/* the following SPR/DCR registers exist only in IBM 400 series */
183#define dear    0x3d5   
184#define evpr    0x3d6   /* SPR: exception vector prefix register   */
185#define iccr    0x3fb   /* SPR: instruction cache control reg.     */
186#define dccr    0x3fa   /* SPR: data cache control reg.            */
187
188#if defined (ppc403)
189#define exisr   0x040   /* DCR: external interrupt status register */
190#define exier   0x042   /* DCR: external interrupt enable register */
191#endif /* ppc403 */
192#if defined(ppc405)
193#define exisr   0x0C0   /* DCR: external interrupt status register */
194#define exier   0x0C2   /* DCR: external interrupt enable register */
195#endif /* ppc405 */
196
197#define br0     0x080   /* DCR: memory bank register 0             */
198#define br1     0x081   /* DCR: memory bank register 1             */
199#define br2     0x082   /* DCR: memory bank register 2             */
200#define br3     0x083   /* DCR: memory bank register 3             */
201#define br4     0x084   /* DCR: memory bank register 4             */
202#define br5     0x085   /* DCR: memory bank register 5             */
203#define br6     0x086   /* DCR: memory bank register 6             */
204#define br7     0x087   /* DCR: memory bank register 7             */
205
206#elif defined(ppc440)
207#define xer     0x001   /* SPR: Integer Exception Register                */
208#define lr      0x008   /* SPR: Link Register                             */
209#define ctr     0x009   /* SPR: Count Register                            */
210#define pid     0x030   /* SPR: Process ID                                */
211#define decar   0x036   /* SPR: Decrementer Auto-Reload                   */
212#define dear    0x03d   /* SPR: Data Exception Address Register           */
213#define esr     0x03e   /* SPR: Exception Syndrome Register               */
214#define ivpr    0x03f   /* SPR: Interrupt Vector Prefix Register          */
215#define sprg4_w 0x104   /* SPR: Special Purpose Register General 4 (WO)   */
216#define sprg5_w 0x105   /* SPR: Special Purpose Register General 5 (WO)   */
217#define sprg6_w 0x107   /* SPR: Special Purpose Register General 6 (WO)   */
218#define sprg7_w 0x108   /* SPR: Special Purpose Register General 7 (WO)   */
219#define tbl     0x10c   /* SPR: Time Base Lower                           */
220#define tbu     0x10d   /* SPR: Time Base Upper                           */
221#define pir     0x11e   /* SPR: Processor ID Register                     */
222#define pvr     0x11f   /* SPR: Processor Version Register                */
223#define dbsr    0x130   /* SPR: Debug Status Register                     */
224#define dbcr0   0x134   /* SPR: Debug Control Register 0                  */
225#define dbcr1   0x135   /* SPR: Debug Control Register 1                  */
226#define dbcr2   0x136   /* SPR: Debug Control Register 2                  */
227#define iac1    0x138   /* SPR: Instruction Address Compare 1             */
228#define iac2    0x139   /* SPR: Instruction Address Compare 2             */
229#define iac3    0x13a   /* SPR: Instruction Address Compare 3             */
230#define iac4    0x13b   /* SPR: Instruction Address Compare 4             */
231#define dac1    0x13c   /* SPR: Data Address Compare 1                    */
232#define dac2    0x13d   /* SPR: Data Address Compare 2                    */
233#define dvc1    0x13e   /* SPR: Data Value Compare 1                      */
234#define dvc2    0x13f   /* SPR: Data Value Compare 2                      */
235#define tsr     0x150   /* SPR: Timer Status Register                     */
236#define tcr     0x154   /* SPR: Timer Control Register                    */
237#define ivor0   0x190   /* SPR: Interrupt Vector Offset Register 0        */
238#define ivor1   0x191   /* SPR: Interrupt Vector Offset Register 1        */
239#define ivor2   0x192   /* SPR: Interrupt Vector Offset Register 2        */
240#define ivor3   0x193   /* SPR: Interrupt Vector Offset Register 3        */
241#define ivor4   0x194   /* SPR: Interrupt Vector Offset Register 4        */
242#define ivor5   0x195   /* SPR: Interrupt Vector Offset Register 5        */
243#define ivor6   0x196   /* SPR: Interrupt Vector Offset Register 6        */
244#define ivor7   0x197   /* SPR: Interrupt Vector Offset Register 7        */
245#define ivor8   0x198   /* SPR: Interrupt Vector Offset Register 8        */
246#define ivor9   0x199   /* SPR: Interrupt Vector Offset Register 9        */
247#define ivor10  0x19a   /* SPR: Interrupt Vector Offset Register 10       */
248#define ivor11  0x19b   /* SPR: Interrupt Vector Offset Register 11       */
249#define ivor12  0x19c   /* SPR: Interrupt Vector Offset Register 12       */
250#define ivor13  0x19d   /* SPR: Interrupt Vector Offset Register 13       */
251#define ivor14  0x19e   /* SPR: Interrupt Vector Offset Register 14       */
252#define ivor15  0x19f   /* SPR: Interrupt Vector Offset Register 15       */
253#define mcsr    0x23c   /* SPR: Machine Check Status Register             */
254#define inv0    0x370   /* SPR: Instruction Cache Normal Victim 0         */
255#define inv1    0x371   /* SPR: Instruction Cache Normal Victim 1         */
256#define inv2    0x372   /* SPR: Instruction Cache Normal Victim 2         */
257#define inv3    0x373   /* SPR: Instruction Cache Normal Victim 3         */
258#define itv0    0x374   /* SPR: Instruction Cache Transient Victim 0      */
259#define itv1    0x375   /* SPR: Instruction Cache Transient Victim 1      */
260#define itv2    0x376   /* SPR: Instruction Cache Transient Victim 2      */
261#define itv3    0x377   /* SPR: Instruction Cache Transient Victim 3      */
262#define ccr1    0x378   /* SPR: Core Configuration Register 1             */
263#define dnv0    0x390   /* SPR: Data Cache Normal Victim 0                */
264#define dnv1    0x391   /* SPR: Data Cache Normal Victim 1                */
265#define dnv2    0x392   /* SPR: Data Cache Normal Victim 2                */
266#define dnv3    0x393   /* SPR: Data Cache Normal Victim 3                */
267#define dtv0    0x394   /* SPR: Data Cache Transient Victim 0             */
268#define dtv1    0x395   /* SPR: Data Cache Transient Victim 1             */
269#define dtv2    0x396   /* SPR: Data Cache Transient Victim 2             */
270#define dtv3    0x397   /* SPR: Data Cache Transient Victim 3             */
271#define dvlim   0x398   /* SPR: Data Cache Victim Limit                   */
272#define ivlim   0x399   /* SPR: Instruction Cache Victim Limit            */
273#define rstcfg  0x39b   /* SPR: Reset Configuration                       */
274#define dcdbtrl 0x39c   /* SPR: Data Cache Debug Tag Register Low         */
275#define dcdbtrh 0x39d   /* SPR: Data Cache Debug Tag Register High        */
276#define icdbtrl 0x39e   /* SPR: Instruction Cache Debug Tag Register Low  */
277#define icdbtrh 0x39f   /* SPR: Instruction Cache Debug Tag Register High */
278#define mmucr   0x3b2   /* SPR: Memory Management Unit Control Register   */
279#define ccr0    0x3b3   /* SPR: Core Configuration Register 0             */
280#define icdbdr  0x3d3   /* SPR: Instruction Cache Debug Data Register     */
281#define dbdr    0x3f3   /* SPR: Debug Data Register                       */
282/* end of IBM400 series register definitions */
283
284#elif defined(mpc555)
285/* The following registers are for the MPC5xx */
286#define eie     0x050   /* External Interrupt Enable Register */
287#define eid     0x051   /* External Interrupt Disable Register */
288#define nri     0x052   /* Non-Recoverable Interrupt Register */
289
290#elif defined(mpc860) || defined(mpc821)
291/* The following registers are for the MPC8x0 */
292#define der     0x095   /* Debug Enable Register */
293#define ictrl   0x09E   /* Instruction Support Control Register */
294#define immr    0x27E   /* Internal Memory Map Register */
295/* end of MPC8x0 registers */
296#endif
297
298/*
299 *  Following must be tailor for a particular flavor of the C compiler.
300 *  They may need to put underscores in front of the symbols.
301 */
302
303#define PUBLIC_VAR(sym) .globl SYM (sym)
304#define EXTERN_VAR(sym) .extern SYM (sym)
305#define PUBLIC_PROC(sym) .globl PROC (sym)
306#define EXTERN_PROC(sym) .extern PROC (sym)
307
308/* Other potentially assembler specific operations */
309#if PPC_ASM == PPC_ASM_ELF
310#define ALIGN(n,p)      .align  p
311#define DESCRIPTOR(x)   \
312        .section .descriptors,"aw";     \
313        PUBLIC_VAR (x);                 \
314SYM (x):;                               \
315        .long   PROC (x);               \
316        .long   s.got;                  \
317        .long   0
318
319#define EXT_SYM_REF(x)  .long x
320#define EXT_PROC_REF(x) .long x
321
322/*
323 *  Define macros to handle section beginning and ends.
324 */
325
326#define BEGIN_CODE_DCL .text
327#define END_CODE_DCL
328#define BEGIN_DATA_DCL .data
329#define END_DATA_DCL
330#define BEGIN_CODE .text
331#define END_CODE
332#define BEGIN_DATA .data
333#define END_DATA
334#define BEGIN_BSS  .bss
335#define END_BSS
336#define END
337
338#else
339#error "PPC_ASM_TYPE is not properly defined"
340#endif
341#ifndef PPC_ASM
342#error "PPC_ASM_TYPE is not properly defined"
343#endif
344
345
346#endif
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