source: rtems/cpukit/score/cpu/powerpc/rtems/asm.h @ 4a0d87e

4.104.114.84.95
Last change on this file since 4a0d87e was 4a0d87e, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 18, 2002 at 8:54:19 PM

2002-04-18 Ralf Corsepius <corsepiu@…>

  • asm.h: Include cpuopts.h instead of targopts.h.
  • rtems/new-exceptions/cpu.h: Relocated from libbsp/powerpc/support/new_exception_processing/rtems/score/cpu.h
  • rtems/old-exceptions/cpu.h: Relocated from c/src/lib/libbsp/powerpc/support/old_exception_processing/rtems/score/cpu.h
  • rtems/powerpc/registers.h: Relocated and renamed from libcpu/powerpc/shared/include/cpu.h.
  • rtems/score/cpu.h: New.
  • Makefile.am: Reflect changes above.
  • Property mode set to 100644
File size: 7.1 KB
Line 
1/*  asm.h
2 *
3 *  This include file attempts to address the problems
4 *  caused by incompatible flavors of assemblers and
5 *  toolsets.  It primarily addresses variations in the
6 *  use of leading underscores on symbols and the requirement
7 *  that register names be preceded by a %.
8 *
9 *
10 *  NOTE: The spacing in the use of these macros
11 *        is critical to them working as advertised.
12 *
13 *  COPYRIGHT:
14 *
15 *  This file is based on similar code found in newlib available
16 *  from ftp.cygnus.com.  The file which was used had no copyright
17 *  notice.  This file is freely distributable as long as the source
18 *  of the file is noted.  This file is:
19 *
20 *  COPYRIGHT (c) 1995.
21 *  i-cubed ltd.
22 *
23 *  COPYRIGHT (c) 1994.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  $Id$
27 */
28
29#ifndef __PPC_ASM_h
30#define __PPC_ASM_h
31
32/*
33 *  Indicate we are in an assembly file and get the basic CPU definitions.
34 */
35
36#ifndef ASM
37#define ASM
38#endif
39#include <rtems/score/cpuopts.h>
40#include <rtems/score/ppc.h>
41
42/*
43 *  Recent versions of GNU cpp define variables which indicate the
44 *  need for underscores and percents.  If not using GNU cpp or
45 *  the version does not support this, then you will obviously
46 *  have to define these as appropriate.
47 */
48
49#ifndef __USER_LABEL_PREFIX__
50#define __USER_LABEL_PREFIX__
51#endif
52
53#ifndef __REGISTER_PREFIX__
54#define __REGISTER_PREFIX__
55#endif
56
57#ifndef __FLOAT_REGISTER_PREFIX__
58#define __FLOAT_REGISTER_PREFIX__  __REGISTER_PREFIX__
59#endif
60
61#if (PPC_ABI == PPC_ABI_POWEROPEN)
62#ifndef __PROC_LABEL_PREFIX__
63#define __PROC_LABEL_PREFIX__ .
64#endif
65#endif
66
67#ifndef __PROC_LABEL_PREFIX__
68#define __PROC_LABEL_PREFIX__  __USER_LABEL_PREFIX__
69#endif
70
71/* ANSI concatenation macros.  */
72
73#define CONCAT1(a, b) CONCAT2(a, b)
74#define CONCAT2(a, b) a ## b
75
76/* Use the right prefix for global labels.  */
77
78#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
79
80/* Use the right prefix for procedure labels.  */
81
82#define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x)
83
84/* Use the right prefix for registers.  */
85
86#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
87
88/* Use the right prefix for floating point registers.  */
89
90#define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x)
91
92/*
93 *  define macros for all of the registers on this CPU
94 *
95 *  EXAMPLE:     #define d0 REG (d0)
96 */
97#define r0 REG(0)
98#define r1 REG(1)
99#define r2 REG(2)
100#define r3 REG(3)
101#define r4 REG(4)
102#define r5 REG(5)
103#define r6 REG(6)
104#define r7 REG(7)
105#define r8 REG(8)
106#define r9 REG(9)
107#define r10 REG(10)
108#define r11 REG(11)
109#define r12 REG(12)
110#define r13 REG(13)
111#define r14 REG(14)
112#define r15 REG(15)
113#define r16 REG(16)
114#define r17 REG(17)
115#define r18 REG(18)
116#define r19 REG(19)
117#define r20 REG(20)
118#define r21 REG(21)
119#define r22 REG(22)
120#define r23 REG(23)
121#define r24 REG(24)
122#define r25 REG(25)
123#define r26 REG(26)
124#define r27 REG(27)
125#define r28 REG(28)
126#define r29 REG(29)
127#define r30 REG(30)
128#define r31 REG(31)
129#define f0 FREG(0)
130#define f1 FREG(1)
131#define f2 FREG(2)
132#define f3 FREG(3)
133#define f4 FREG(4)
134#define f5 FREG(5)
135#define f6 FREG(6)
136#define f7 FREG(7)
137#define f8 FREG(8)
138#define f9 FREG(9)
139#define f10 FREG(10)
140#define f11 FREG(11)
141#define f12 FREG(12)
142#define f13 FREG(13)
143#define f14 FREG(14)
144#define f15 FREG(15)
145#define f16 FREG(16)
146#define f17 FREG(17)
147#define f18 FREG(18)
148#define f19 FREG(19)
149#define f20 FREG(20)
150#define f21 FREG(21)
151#define f22 FREG(22)
152#define f23 FREG(23)
153#define f24 FREG(24)
154#define f25 FREG(25)
155#define f26 FREG(26)
156#define f27 FREG(27)
157#define f28 FREG(28)
158#define f29 FREG(29)
159#define f30 FREG(30)
160#define f31 FREG(31)
161
162/*
163 * Some special purpose registers (SPRs).
164 */
165#define srr0    0x01a
166#define srr1    0x01b
167#if defined(ppc403) || defined(ppc405)
168#define srr2    0x3de   /* IBM 400 series only */
169#define srr3    0x3df   /* IBM 400 series only */
170#endif /* ppc403 or ppc405 */
171
172#define sprg0   0x110
173#define sprg1   0x111
174#define sprg2   0x112
175#define sprg3   0x113
176
177#define dar     0x013   /* Data Address Register */
178#define dec             0x016   /* Decrementer Register */
179
180#if defined(ppc403) || defined(ppc405)
181/* the following SPR/DCR registers exist only in IBM 400 series */
182#define dear    0x3d5   
183#define evpr    0x3d6   /* SPR: exception vector prefix register   */
184#define iccr    0x3fb   /* SPR: instruction cache control reg.     */
185#define dccr    0x3fa   /* SPR: data cache control reg.            */
186
187#if defined (ppc403)
188#define exisr   0x040   /* DCR: external interrupt status register */
189#define exier   0x042   /* DCR: external interrupt enable register */
190#endif /* ppc403 */
191#if defined(ppc405)
192#define exisr   0x0C0   /* DCR: external interrupt status register */
193#define exier   0x0C2   /* DCR: external interrupt enable register */
194#endif /* ppc405 */
195
196#define br0     0x080   /* DCR: memory bank register 0             */
197#define br1     0x081   /* DCR: memory bank register 1             */
198#define br2     0x082   /* DCR: memory bank register 2             */
199#define br3     0x083   /* DCR: memory bank register 3             */
200#define br4     0x084   /* DCR: memory bank register 4             */
201#define br5     0x085   /* DCR: memory bank register 5             */
202#define br6     0x086   /* DCR: memory bank register 6             */
203#define br7     0x087   /* DCR: memory bank register 7             */
204/* end of IBM400 series register definitions */
205
206#elif defined(mpc860) || defined(mpc821)
207/* The following registers are for the MPC8x0 */
208#define der     0x095   /* Debug Enable Register */
209#define ictrl   0x09E   /* Instruction Support Control Register */
210#define immr    0x27E   /* Internal Memory Map Register */
211/* end of MPC8x0 registers */
212#endif
213
214/*
215 *  Following must be tailor for a particular flavor of the C compiler.
216 *  They may need to put underscores in front of the symbols.
217 */
218
219#define PUBLIC_VAR(sym) .globl SYM (sym)
220#define EXTERN_VAR(sym) .extern SYM (sym)
221#define PUBLIC_PROC(sym) .globl PROC (sym)
222#define EXTERN_PROC(sym) .extern PROC (sym)
223
224/* Other potentially assembler specific operations */
225#if PPC_ASM == PPC_ASM_ELF
226#define ALIGN(n,p)      .align  p
227#define DESCRIPTOR(x)   \
228        .section .descriptors,"aw";     \
229        PUBLIC_VAR (x);                 \
230SYM (x):;                               \
231        .long   PROC (x);               \
232        .long   s.got;                  \
233        .long   0
234
235#define EXT_SYM_REF(x)  .long x
236#define EXT_PROC_REF(x) .long x
237
238/*
239 *  Define macros to handle section beginning and ends.
240 */
241
242#define BEGIN_CODE_DCL .text
243#define END_CODE_DCL
244#define BEGIN_DATA_DCL .data
245#define END_DATA_DCL
246#define BEGIN_CODE .text
247#define END_CODE
248#define BEGIN_DATA .data
249#define END_DATA
250#define BEGIN_BSS  .bss
251#define END_BSS
252#define END
253
254#elif PPC_ASM == PPC_ASM_XCOFF
255#define ALIGN(n,p)      .align  p
256#define DESCRIPTOR(x)   \
257        .csect  x[DS];          \
258        .globl  x[DS];          \
259        .long   PROC (x)[PR];   \
260        .long   TOC[tc0]
261
262#define EXT_SYM_REF(x)  .long x[RW]
263#define EXT_PROC_REF(x) .long x[DS]
264
265/*
266 *  Define macros to handle section beginning and ends.
267 */
268
269#define BEGIN_CODE_DCL .csect .text[PR]
270#define END_CODE_DCL
271#define BEGIN_DATA_DCL .csect .data[RW]
272#define END_DATA_DCL
273#define BEGIN_CODE .csect .text[PR]
274#define END_CODE
275#define BEGIN_DATA .csect .data[RW]
276#define END_DATA
277#define BEGIN_BSS  .bss
278#define END_BSS
279#define END
280
281#else
282#error "PPC_ASM_TYPE is not properly defined"
283#endif
284#ifndef PPC_ASM
285#error "PPC_ASM_TYPE is not properly defined"
286#endif
287
288
289#endif
290/* end of include file */
291
292
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