[b8ed8a9f] | 1 | /** |
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| 2 | * @file rtems/asm.h |
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[ba46ffa6] | 3 | * |
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| 4 | * This include file attempts to address the problems |
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| 5 | * caused by incompatible flavors of assemblers and |
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| 6 | * toolsets. It primarily addresses variations in the |
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| 7 | * use of leading underscores on symbols and the requirement |
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| 8 | * that register names be preceded by a %. |
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[b8ed8a9f] | 9 | */ |
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| 10 | |
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| 11 | /* |
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[ba46ffa6] | 12 | * NOTE: The spacing in the use of these macros |
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| 13 | * is critical to them working as advertised. |
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| 14 | * |
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| 15 | * COPYRIGHT: |
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| 16 | * |
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| 17 | * This file is based on similar code found in newlib available |
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| 18 | * from ftp.cygnus.com. The file which was used had no copyright |
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| 19 | * notice. This file is freely distributable as long as the source |
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| 20 | * of the file is noted. This file is: |
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| 21 | * |
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| 22 | * COPYRIGHT (c) 1995. |
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| 23 | * i-cubed ltd. |
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| 24 | * |
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| 25 | * COPYRIGHT (c) 1994. |
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| 26 | * On-Line Applications Research Corporation (OAR). |
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| 27 | */ |
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| 28 | |
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[7f70d1b7] | 29 | #ifndef _RTEMS_ASM_H |
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| 30 | #define _RTEMS_ASM_H |
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[ba46ffa6] | 31 | |
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| 32 | /* |
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| 33 | * Indicate we are in an assembly file and get the basic CPU definitions. |
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| 34 | */ |
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| 35 | |
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| 36 | #ifndef ASM |
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| 37 | #define ASM |
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| 38 | #endif |
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[4a0d87e] | 39 | #include <rtems/score/cpuopts.h> |
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[3411bac] | 40 | #include <rtems/score/powerpc.h> |
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[ba46ffa6] | 41 | |
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| 42 | /* |
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| 43 | * Recent versions of GNU cpp define variables which indicate the |
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| 44 | * need for underscores and percents. If not using GNU cpp or |
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| 45 | * the version does not support this, then you will obviously |
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| 46 | * have to define these as appropriate. |
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| 47 | */ |
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| 48 | |
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| 49 | #ifndef __USER_LABEL_PREFIX__ |
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[5bb38e15] | 50 | #define __USER_LABEL_PREFIX__ |
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[ba46ffa6] | 51 | #endif |
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| 52 | |
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| 53 | #ifndef __REGISTER_PREFIX__ |
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| 54 | #define __REGISTER_PREFIX__ |
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| 55 | #endif |
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| 56 | |
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| 57 | #ifndef __FLOAT_REGISTER_PREFIX__ |
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| 58 | #define __FLOAT_REGISTER_PREFIX__ __REGISTER_PREFIX__ |
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| 59 | #endif |
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| 60 | |
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| 61 | #ifndef __PROC_LABEL_PREFIX__ |
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| 62 | #define __PROC_LABEL_PREFIX__ __USER_LABEL_PREFIX__ |
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| 63 | #endif |
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| 64 | |
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[c6ea319] | 65 | #include <rtems/concat.h> |
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[ba46ffa6] | 66 | |
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| 67 | /* Use the right prefix for global labels. */ |
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| 68 | |
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| 69 | #define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x) |
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| 70 | |
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| 71 | /* Use the right prefix for procedure labels. */ |
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| 72 | |
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| 73 | #define PROC(x) CONCAT1 (__PROC_LABEL_PREFIX__, x) |
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| 74 | |
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| 75 | /* Use the right prefix for registers. */ |
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| 76 | |
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| 77 | #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) |
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| 78 | |
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| 79 | /* Use the right prefix for floating point registers. */ |
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| 80 | |
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| 81 | #define FREG(x) CONCAT1 (__FLOAT_REGISTER_PREFIX__, x) |
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| 82 | |
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| 83 | /* |
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| 84 | * define macros for all of the registers on this CPU |
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| 85 | * |
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| 86 | * EXAMPLE: #define d0 REG (d0) |
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| 87 | */ |
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| 88 | #define r0 REG(0) |
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| 89 | #define r1 REG(1) |
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| 90 | #define r2 REG(2) |
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| 91 | #define r3 REG(3) |
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| 92 | #define r4 REG(4) |
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| 93 | #define r5 REG(5) |
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| 94 | #define r6 REG(6) |
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| 95 | #define r7 REG(7) |
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| 96 | #define r8 REG(8) |
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| 97 | #define r9 REG(9) |
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| 98 | #define r10 REG(10) |
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| 99 | #define r11 REG(11) |
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| 100 | #define r12 REG(12) |
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| 101 | #define r13 REG(13) |
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| 102 | #define r14 REG(14) |
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| 103 | #define r15 REG(15) |
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| 104 | #define r16 REG(16) |
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| 105 | #define r17 REG(17) |
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| 106 | #define r18 REG(18) |
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| 107 | #define r19 REG(19) |
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| 108 | #define r20 REG(20) |
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| 109 | #define r21 REG(21) |
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| 110 | #define r22 REG(22) |
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| 111 | #define r23 REG(23) |
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| 112 | #define r24 REG(24) |
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| 113 | #define r25 REG(25) |
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| 114 | #define r26 REG(26) |
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| 115 | #define r27 REG(27) |
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| 116 | #define r28 REG(28) |
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| 117 | #define r29 REG(29) |
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| 118 | #define r30 REG(30) |
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| 119 | #define r31 REG(31) |
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| 120 | #define f0 FREG(0) |
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| 121 | #define f1 FREG(1) |
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| 122 | #define f2 FREG(2) |
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| 123 | #define f3 FREG(3) |
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| 124 | #define f4 FREG(4) |
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| 125 | #define f5 FREG(5) |
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| 126 | #define f6 FREG(6) |
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| 127 | #define f7 FREG(7) |
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| 128 | #define f8 FREG(8) |
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| 129 | #define f9 FREG(9) |
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| 130 | #define f10 FREG(10) |
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| 131 | #define f11 FREG(11) |
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| 132 | #define f12 FREG(12) |
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| 133 | #define f13 FREG(13) |
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| 134 | #define f14 FREG(14) |
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| 135 | #define f15 FREG(15) |
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| 136 | #define f16 FREG(16) |
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| 137 | #define f17 FREG(17) |
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| 138 | #define f18 FREG(18) |
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| 139 | #define f19 FREG(19) |
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| 140 | #define f20 FREG(20) |
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| 141 | #define f21 FREG(21) |
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| 142 | #define f22 FREG(22) |
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| 143 | #define f23 FREG(23) |
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| 144 | #define f24 FREG(24) |
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| 145 | #define f25 FREG(25) |
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| 146 | #define f26 FREG(26) |
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| 147 | #define f27 FREG(27) |
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| 148 | #define f28 FREG(28) |
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| 149 | #define f29 FREG(29) |
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| 150 | #define f30 FREG(30) |
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| 151 | #define f31 FREG(31) |
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| 152 | |
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| 153 | /* |
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| 154 | * Some special purpose registers (SPRs). |
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| 155 | */ |
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| 156 | #define srr0 0x01a |
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| 157 | #define srr1 0x01b |
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[767cdd8] | 158 | #define srr2 0x3de /* IBM 400 series only */ |
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| 159 | #define srr3 0x3df /* IBM 400 series only */ |
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| 160 | #define csrr0 58 /* Book E */ |
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| 161 | #define csrr1 59 /* Book E */ |
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| 162 | #define mcsrr0 570 /* e500 */ |
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| 163 | #define mcsrr1 571 /* e500 */ |
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| 164 | #define dsrr0 574 /* e200 */ |
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| 165 | #define dsrr1 575 /* e200 */ |
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[8ef3818] | 166 | |
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[ba46ffa6] | 167 | #define sprg0 0x110 |
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| 168 | #define sprg1 0x111 |
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| 169 | #define sprg2 0x112 |
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| 170 | #define sprg3 0x113 |
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[767cdd8] | 171 | #define sprg4 276 |
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| 172 | #define sprg5 277 |
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| 173 | #define sprg6 278 |
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| 174 | #define sprg7 279 |
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| 175 | |
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| 176 | #define usprg0 256 |
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[ba46ffa6] | 177 | |
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[8ef3818] | 178 | #define dar 0x013 /* Data Address Register */ |
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| 179 | #define dec 0x016 /* Decrementer Register */ |
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[ba46ffa6] | 180 | |
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[95e0ca93] | 181 | #if defined(ppc403) || defined(ppc405) |
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[ba46ffa6] | 182 | /* the following SPR/DCR registers exist only in IBM 400 series */ |
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| 183 | #define dear 0x3d5 |
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| 184 | #define evpr 0x3d6 /* SPR: exception vector prefix register */ |
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| 185 | #define iccr 0x3fb /* SPR: instruction cache control reg. */ |
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| 186 | #define dccr 0x3fa /* SPR: data cache control reg. */ |
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| 187 | |
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[95e0ca93] | 188 | #if defined (ppc403) |
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[ba46ffa6] | 189 | #define exisr 0x040 /* DCR: external interrupt status register */ |
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| 190 | #define exier 0x042 /* DCR: external interrupt enable register */ |
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[95e0ca93] | 191 | #endif /* ppc403 */ |
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| 192 | #if defined(ppc405) |
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| 193 | #define exisr 0x0C0 /* DCR: external interrupt status register */ |
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| 194 | #define exier 0x0C2 /* DCR: external interrupt enable register */ |
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| 195 | #endif /* ppc405 */ |
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| 196 | |
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[ba46ffa6] | 197 | #define br0 0x080 /* DCR: memory bank register 0 */ |
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| 198 | #define br1 0x081 /* DCR: memory bank register 1 */ |
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| 199 | #define br2 0x082 /* DCR: memory bank register 2 */ |
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| 200 | #define br3 0x083 /* DCR: memory bank register 3 */ |
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| 201 | #define br4 0x084 /* DCR: memory bank register 4 */ |
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| 202 | #define br5 0x085 /* DCR: memory bank register 5 */ |
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| 203 | #define br6 0x086 /* DCR: memory bank register 6 */ |
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| 204 | #define br7 0x087 /* DCR: memory bank register 7 */ |
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[16a8616] | 205 | |
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| 206 | #elif defined(ppc440) |
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| 207 | #define xer 0x001 /* SPR: Integer Exception Register */ |
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| 208 | #define lr 0x008 /* SPR: Link Register */ |
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| 209 | #define ctr 0x009 /* SPR: Count Register */ |
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| 210 | #define pid 0x030 /* SPR: Process ID */ |
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| 211 | #define decar 0x036 /* SPR: Decrementer Auto-Reload */ |
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| 212 | #define dear 0x03d /* SPR: Data Exception Address Register */ |
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| 213 | #define esr 0x03e /* SPR: Exception Syndrome Register */ |
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| 214 | #define ivpr 0x03f /* SPR: Interrupt Vector Prefix Register */ |
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| 215 | #define sprg4_w 0x104 /* SPR: Special Purpose Register General 4 (WO) */ |
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| 216 | #define sprg5_w 0x105 /* SPR: Special Purpose Register General 5 (WO) */ |
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| 217 | #define sprg6_w 0x107 /* SPR: Special Purpose Register General 6 (WO) */ |
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| 218 | #define sprg7_w 0x108 /* SPR: Special Purpose Register General 7 (WO) */ |
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| 219 | #define tbl 0x10c /* SPR: Time Base Lower */ |
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| 220 | #define tbu 0x10d /* SPR: Time Base Upper */ |
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| 221 | #define pir 0x11e /* SPR: Processor ID Register */ |
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| 222 | #define pvr 0x11f /* SPR: Processor Version Register */ |
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| 223 | #define dbsr 0x130 /* SPR: Debug Status Register */ |
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| 224 | #define dbcr0 0x134 /* SPR: Debug Control Register 0 */ |
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| 225 | #define dbcr1 0x135 /* SPR: Debug Control Register 1 */ |
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| 226 | #define dbcr2 0x136 /* SPR: Debug Control Register 2 */ |
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| 227 | #define iac1 0x138 /* SPR: Instruction Address Compare 1 */ |
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| 228 | #define iac2 0x139 /* SPR: Instruction Address Compare 2 */ |
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| 229 | #define iac3 0x13a /* SPR: Instruction Address Compare 3 */ |
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| 230 | #define iac4 0x13b /* SPR: Instruction Address Compare 4 */ |
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| 231 | #define dac1 0x13c /* SPR: Data Address Compare 1 */ |
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| 232 | #define dac2 0x13d /* SPR: Data Address Compare 2 */ |
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| 233 | #define dvc1 0x13e /* SPR: Data Value Compare 1 */ |
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| 234 | #define dvc2 0x13f /* SPR: Data Value Compare 2 */ |
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| 235 | #define tsr 0x150 /* SPR: Timer Status Register */ |
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| 236 | #define tcr 0x154 /* SPR: Timer Control Register */ |
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| 237 | #define ivor0 0x190 /* SPR: Interrupt Vector Offset Register 0 */ |
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| 238 | #define ivor1 0x191 /* SPR: Interrupt Vector Offset Register 1 */ |
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| 239 | #define ivor2 0x192 /* SPR: Interrupt Vector Offset Register 2 */ |
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| 240 | #define ivor3 0x193 /* SPR: Interrupt Vector Offset Register 3 */ |
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| 241 | #define ivor4 0x194 /* SPR: Interrupt Vector Offset Register 4 */ |
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| 242 | #define ivor5 0x195 /* SPR: Interrupt Vector Offset Register 5 */ |
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| 243 | #define ivor6 0x196 /* SPR: Interrupt Vector Offset Register 6 */ |
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| 244 | #define ivor7 0x197 /* SPR: Interrupt Vector Offset Register 7 */ |
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| 245 | #define ivor8 0x198 /* SPR: Interrupt Vector Offset Register 8 */ |
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| 246 | #define ivor9 0x199 /* SPR: Interrupt Vector Offset Register 9 */ |
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| 247 | #define ivor10 0x19a /* SPR: Interrupt Vector Offset Register 10 */ |
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| 248 | #define ivor11 0x19b /* SPR: Interrupt Vector Offset Register 11 */ |
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| 249 | #define ivor12 0x19c /* SPR: Interrupt Vector Offset Register 12 */ |
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| 250 | #define ivor13 0x19d /* SPR: Interrupt Vector Offset Register 13 */ |
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| 251 | #define ivor14 0x19e /* SPR: Interrupt Vector Offset Register 14 */ |
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| 252 | #define ivor15 0x19f /* SPR: Interrupt Vector Offset Register 15 */ |
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| 253 | #define mcsr 0x23c /* SPR: Machine Check Status Register */ |
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| 254 | #define inv0 0x370 /* SPR: Instruction Cache Normal Victim 0 */ |
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| 255 | #define inv1 0x371 /* SPR: Instruction Cache Normal Victim 1 */ |
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| 256 | #define inv2 0x372 /* SPR: Instruction Cache Normal Victim 2 */ |
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| 257 | #define inv3 0x373 /* SPR: Instruction Cache Normal Victim 3 */ |
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| 258 | #define itv0 0x374 /* SPR: Instruction Cache Transient Victim 0 */ |
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| 259 | #define itv1 0x375 /* SPR: Instruction Cache Transient Victim 1 */ |
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| 260 | #define itv2 0x376 /* SPR: Instruction Cache Transient Victim 2 */ |
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| 261 | #define itv3 0x377 /* SPR: Instruction Cache Transient Victim 3 */ |
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| 262 | #define ccr1 0x378 /* SPR: Core Configuration Register 1 */ |
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| 263 | #define dnv0 0x390 /* SPR: Data Cache Normal Victim 0 */ |
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| 264 | #define dnv1 0x391 /* SPR: Data Cache Normal Victim 1 */ |
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| 265 | #define dnv2 0x392 /* SPR: Data Cache Normal Victim 2 */ |
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| 266 | #define dnv3 0x393 /* SPR: Data Cache Normal Victim 3 */ |
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| 267 | #define dtv0 0x394 /* SPR: Data Cache Transient Victim 0 */ |
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| 268 | #define dtv1 0x395 /* SPR: Data Cache Transient Victim 1 */ |
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| 269 | #define dtv2 0x396 /* SPR: Data Cache Transient Victim 2 */ |
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| 270 | #define dtv3 0x397 /* SPR: Data Cache Transient Victim 3 */ |
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| 271 | #define dvlim 0x398 /* SPR: Data Cache Victim Limit */ |
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| 272 | #define ivlim 0x399 /* SPR: Instruction Cache Victim Limit */ |
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| 273 | #define rstcfg 0x39b /* SPR: Reset Configuration */ |
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| 274 | #define dcdbtrl 0x39c /* SPR: Data Cache Debug Tag Register Low */ |
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| 275 | #define dcdbtrh 0x39d /* SPR: Data Cache Debug Tag Register High */ |
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| 276 | #define icdbtrl 0x39e /* SPR: Instruction Cache Debug Tag Register Low */ |
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| 277 | #define icdbtrh 0x39f /* SPR: Instruction Cache Debug Tag Register High */ |
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| 278 | #define mmucr 0x3b2 /* SPR: Memory Management Unit Control Register */ |
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| 279 | #define ccr0 0x3b3 /* SPR: Core Configuration Register 0 */ |
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| 280 | #define icdbdr 0x3d3 /* SPR: Instruction Cache Debug Data Register */ |
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| 281 | #define dbdr 0x3f3 /* SPR: Debug Data Register */ |
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[ba46ffa6] | 282 | /* end of IBM400 series register definitions */ |
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| 283 | |
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[e69307b7] | 284 | #elif defined(mpc555) |
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| 285 | /* The following registers are for the MPC5xx */ |
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| 286 | #define eie 0x050 /* External Interrupt Enable Register */ |
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| 287 | #define eid 0x051 /* External Interrupt Disable Register */ |
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[5bb38e15] | 288 | #define nri 0x052 /* Non-Recoverable Interrupt Register */ |
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| 289 | |
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[8ef3818] | 290 | #elif defined(mpc860) || defined(mpc821) |
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[ba46ffa6] | 291 | /* The following registers are for the MPC8x0 */ |
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| 292 | #define der 0x095 /* Debug Enable Register */ |
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[8ef3818] | 293 | #define ictrl 0x09E /* Instruction Support Control Register */ |
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| 294 | #define immr 0x27E /* Internal Memory Map Register */ |
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[ba46ffa6] | 295 | /* end of MPC8x0 registers */ |
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[8ef3818] | 296 | #endif |
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[ba46ffa6] | 297 | |
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| 298 | /* |
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| 299 | * Following must be tailor for a particular flavor of the C compiler. |
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| 300 | * They may need to put underscores in front of the symbols. |
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| 301 | */ |
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| 302 | |
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| 303 | #define PUBLIC_VAR(sym) .globl SYM (sym) |
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| 304 | #define EXTERN_VAR(sym) .extern SYM (sym) |
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| 305 | #define PUBLIC_PROC(sym) .globl PROC (sym) |
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| 306 | #define EXTERN_PROC(sym) .extern PROC (sym) |
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| 307 | |
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| 308 | /* Other potentially assembler specific operations */ |
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| 309 | #if PPC_ASM == PPC_ASM_ELF |
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| 310 | #define ALIGN(n,p) .align p |
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| 311 | #define DESCRIPTOR(x) \ |
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| 312 | .section .descriptors,"aw"; \ |
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| 313 | PUBLIC_VAR (x); \ |
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| 314 | SYM (x):; \ |
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| 315 | .long PROC (x); \ |
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| 316 | .long s.got; \ |
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| 317 | .long 0 |
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| 318 | |
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| 319 | #define EXT_SYM_REF(x) .long x |
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| 320 | #define EXT_PROC_REF(x) .long x |
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| 321 | |
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| 322 | /* |
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| 323 | * Define macros to handle section beginning and ends. |
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| 324 | */ |
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| 325 | |
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| 326 | #define BEGIN_CODE_DCL .text |
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| 327 | #define END_CODE_DCL |
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| 328 | #define BEGIN_DATA_DCL .data |
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| 329 | #define END_DATA_DCL |
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| 330 | #define BEGIN_CODE .text |
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| 331 | #define END_CODE |
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| 332 | #define BEGIN_DATA .data |
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| 333 | #define END_DATA |
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| 334 | #define BEGIN_BSS .bss |
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| 335 | #define END_BSS |
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| 336 | #define END |
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| 337 | |
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| 338 | #else |
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| 339 | #error "PPC_ASM_TYPE is not properly defined" |
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| 340 | #endif |
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| 341 | #ifndef PPC_ASM |
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| 342 | #error "PPC_ASM_TYPE is not properly defined" |
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| 343 | #endif |
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| 344 | |
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| 345 | |
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| 346 | #endif |
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