source: rtems/cpukit/score/cpu/powerpc/ppc-isr-disable-mask.S @ 801b5d8

4.115
Last change on this file since 801b5d8 was 801b5d8, checked in by Sebastian Huber <sebastian.huber@…>, on 02/17/14 at 08:23:59

powerpc: Change interrupt disable implemetation

Instead of SPRG0 (= special purpose register 272) use the new global
symbol _PPC_INTERRUPT_DISABLE_MASK to store the interrupt disable mask.
The benefit is that it is now possible to disable interrupts without
further run-time initialization in boot_card().

At least on Freescale e500 cores this leads also to a faster execution
since the mfmsr and mfspr instruction require four cycles to complete.
The instructions to load the mask value can execute while the mfmsr is
in progress.
  • Property mode set to 100644
File size: 584 bytes
Line 
1/*
2 * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifdef HAVE_CONFIG_H
16  #include "config.h"
17#endif
18
19#include <rtems/asm.h>
20#include <rtems/score/cpu.h>
21
22.global _PPC_INTERRUPT_DISABLE_MASK
23.weak   _PPC_INTERRUPT_DISABLE_MASK
24.set    _PPC_INTERRUPT_DISABLE_MASK, PPC_INTERRUPT_DISABLE_MASK_DEFAULT
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