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ppc-context-validate.S @ 255fe43

Last change on this file since 255fe43 was 255fe43, checked in by Joel Sherrill <joel@…>, on 03/01/22 at 20:40:44

cpukit/: Scripted embedded brains header file clean up

Updates #4625.

Property mode set to 100644

File size: 13.1 KB

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1	/* SPDX-License-Identifier: BSD-2-Clause */
2
3	/*
4	* Copyright (c) 2013, 2017 embedded brains GmbH. All rights reserved.
5	*
6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions
8	* are met:
9	* 1. Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.
11	* 2. Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.
14	*
15	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18	* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19	* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20	* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21	* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22	* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23	* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24	* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25	* POSSIBILITY OF SUCH DAMAGE.
26	*/
27
28	#ifdef HAVE_CONFIG_H
29	#include "config.h"
30	#endif
31
32	#include <rtems/asm.h>
33	#include <rtems/score/cpu.h>
34
35	#define LR_OFFSET 8
36	#define CR_OFFSET 16
37	#define OFFSET(i) ((i) * PPC_GPR_SIZE + 32)
38	#define GPR14_OFFSET OFFSET(0)
39	#define GPR15_OFFSET OFFSET(1)
40	#define GPR16_OFFSET OFFSET(2)
41	#define GPR17_OFFSET OFFSET(3)
42	#define GPR18_OFFSET OFFSET(4)
43	#define GPR19_OFFSET OFFSET(5)
44	#define GPR20_OFFSET OFFSET(6)
45	#define GPR21_OFFSET OFFSET(7)
46	#define GPR22_OFFSET OFFSET(8)
47	#define GPR23_OFFSET OFFSET(9)
48	#define GPR24_OFFSET OFFSET(10)
49	#define GPR25_OFFSET OFFSET(11)
50	#define GPR26_OFFSET OFFSET(12)
51	#define GPR27_OFFSET OFFSET(13)
52	#define GPR28_OFFSET OFFSET(14)
53	#define GPR29_OFFSET OFFSET(15)
54	#define GPR30_OFFSET OFFSET(16)
55	#define GPR31_OFFSET OFFSET(17)
56
57	#ifdef PPC_MULTILIB_FPU
58	#define FOFFSET(i) ((i) * 8 + OFFSET(18))
59	#define F14_OFFSET FOFFSET(0)
60	#define F15_OFFSET FOFFSET(1)
61	#define F16_OFFSET FOFFSET(2)
62	#define F17_OFFSET FOFFSET(3)
63	#define F18_OFFSET FOFFSET(4)
64	#define F19_OFFSET FOFFSET(5)
65	#define F20_OFFSET FOFFSET(6)
66	#define F21_OFFSET FOFFSET(7)
67	#define F22_OFFSET FOFFSET(8)
68	#define F23_OFFSET FOFFSET(9)
69	#define F24_OFFSET FOFFSET(10)
70	#define F25_OFFSET FOFFSET(11)
71	#define F26_OFFSET FOFFSET(12)
72	#define F27_OFFSET FOFFSET(13)
73	#define F28_OFFSET FOFFSET(14)
74	#define F29_OFFSET FOFFSET(15)
75	#define F30_OFFSET FOFFSET(16)
76	#define F31_OFFSET FOFFSET(17)
77	#define FPSCR_OFFSET FOFFSET(18)
78	#define FTMP_OFFSET FOFFSET(19)
79	#define FTMP2_OFFSET FOFFSET(20)
80	#define FPUEND FOFFSET(21)
81	#else
82	#define FPUEND OFFSET(18)
83	#endif
84
85	#ifdef PPC_MULTILIB_ALTIVEC
86	#define VOFFSET(i) ((i) * 16 + ((FPUEND + 16 - 1) & ~(16 - 1)))
87	#define V20_OFFSET VOFFSET(0)
88	#define V21_OFFSET VOFFSET(1)
89	#define V22_OFFSET VOFFSET(2)
90	#define V23_OFFSET VOFFSET(3)
91	#define V24_OFFSET VOFFSET(4)
92	#define V25_OFFSET VOFFSET(5)
93	#define V26_OFFSET VOFFSET(6)
94	#define V27_OFFSET VOFFSET(7)
95	#define V28_OFFSET VOFFSET(8)
96	#define V29_OFFSET VOFFSET(9)
97	#define V30_OFFSET VOFFSET(10)
98	#define V31_OFFSET VOFFSET(11)
99	#define VTMP_OFFSET VOFFSET(12)
100	#define VTMP2_OFFSET VOFFSET(13)
101	#define VRSAVE_OFFSET VOFFSET(14)
102	#define VSCR_OFFSET (VOFFSET(14) + 12)
103	#define ALTIVECEND VOFFSET(15)
104	#else
105	#define ALTIVECEND FPUEND
106	#endif
107
108	#define FRAME_SIZE \
109	((ALTIVECEND + CPU_STACK_ALIGNMENT - 1) & ~(CPU_STACK_ALIGNMENT - 1))
110
111	.global _CPU_Context_validate
112
113	_CPU_Context_validate:
114
115	/* Save */
116	PPC_REG_STORE_UPDATE r1, -FRAME_SIZE(r1)
117	mflr r4
118	PPC_REG_STORE r4, LR_OFFSET(r1)
119	mfcr r4
120	stw r4, CR_OFFSET(r1)
121	PPC_REG_STORE r14, GPR14_OFFSET(r1)
122	PPC_REG_STORE r15, GPR15_OFFSET(r1)
123	PPC_REG_STORE r16, GPR16_OFFSET(r1)
124	PPC_REG_STORE r17, GPR17_OFFSET(r1)
125	PPC_REG_STORE r18, GPR18_OFFSET(r1)
126	PPC_REG_STORE r19, GPR19_OFFSET(r1)
127	PPC_REG_STORE r20, GPR20_OFFSET(r1)
128	PPC_REG_STORE r21, GPR21_OFFSET(r1)
129	PPC_REG_STORE r22, GPR22_OFFSET(r1)
130	PPC_REG_STORE r23, GPR23_OFFSET(r1)
131	PPC_REG_STORE r24, GPR24_OFFSET(r1)
132	PPC_REG_STORE r25, GPR25_OFFSET(r1)
133	PPC_REG_STORE r26, GPR26_OFFSET(r1)
134	PPC_REG_STORE r27, GPR27_OFFSET(r1)
135	PPC_REG_STORE r28, GPR28_OFFSET(r1)
136	PPC_REG_STORE r29, GPR29_OFFSET(r1)
137	PPC_REG_STORE r30, GPR30_OFFSET(r1)
138	PPC_REG_STORE r31, GPR31_OFFSET(r1)
139
140	#ifdef PPC_MULTILIB_FPU
141	stfd f14, F14_OFFSET(r1)
142	stfd f15, F15_OFFSET(r1)
143	stfd f16, F16_OFFSET(r1)
144	stfd f17, F17_OFFSET(r1)
145	stfd f18, F18_OFFSET(r1)
146	stfd f19, F19_OFFSET(r1)
147	stfd f20, F20_OFFSET(r1)
148	stfd f21, F21_OFFSET(r1)
149	stfd f22, F22_OFFSET(r1)
150	stfd f23, F23_OFFSET(r1)
151	stfd f24, F24_OFFSET(r1)
152	stfd f25, F25_OFFSET(r1)
153	stfd f26, F26_OFFSET(r1)
154	stfd f27, F27_OFFSET(r1)
155	stfd f28, F28_OFFSET(r1)
156	stfd f29, F29_OFFSET(r1)
157	stfd f30, F30_OFFSET(r1)
158	stfd f31, F31_OFFSET(r1)
159	mffs f0
160	stfd f0, FPSCR_OFFSET(r1)
161	#endif
162
163	#ifdef PPC_MULTILIB_ALTIVEC
164	li r0, V20_OFFSET
165	stvx v20, r1, r0
166	li r0, V21_OFFSET
167	stvx v21, r1, r0
168	li r0, V22_OFFSET
169	stvx v22, r1, r0
170	li r0, V23_OFFSET
171	stvx v23, r1, r0
172	li r0, V24_OFFSET
173	stvx v24, r1, r0
174	li r0, V25_OFFSET
175	stvx v25, r1, r0
176	li r0, V26_OFFSET
177	stvx v26, r1, r0
178	li r0, V27_OFFSET
179	stvx v27, r1, r0
180	li r0, V28_OFFSET
181	stvx v28, r1, r0
182	li r0, V29_OFFSET
183	stvx v29, r1, r0
184	li r0, V30_OFFSET
185	stvx v30, r1, r0
186	li r0, V31_OFFSET
187	stvx v31, r1, r0
188	mfvscr v0
189	li r0, VSCR_OFFSET
190	stvewx v0, r1, r0
191	mfvrsave r0
192	stw r0, VRSAVE_OFFSET(r1)
193	#endif
194
195	/* Fill */
196
197	/* CR and GPR29 are equal most of the time */
198	addi r4, r3, 24
199	mtcr r4
200
201	addi r4, r3, 25
202	mtlr r4
203	addi r4, r3, 26
204	mtctr r4
205	rlwinm r4, r3, 0, 25, 2
206	mtxer r4
207	addi r0, r3, 28
208
209	/* GPR4 is used for temporary values */
210
211	addi r5, r3, 1
212	addi r6, r3, 2
213	addi r7, r3, 3
214	addi r8, r3, 4
215	addi r9, r3, 5
216	addi r10, r3, 6
217	addi r11, r3, 7
218	addi r12, r3, 8
219	addi r14, r3, 9
220	addi r15, r3, 10
221	addi r16, r3, 11
222	addi r17, r3, 12
223	addi r18, r3, 13
224	addi r19, r3, 14
225	addi r20, r3, 15
226	addi r21, r3, 16
227	addi r22, r3, 17
228	addi r23, r3, 18
229	addi r24, r3, 19
230	addi r25, r3, 20
231	addi r26, r3, 21
232	addi r27, r3, 22
233
234	/* GPR28 contains the TP pattern */
235	#ifdef __powerpc64__
236	xor r28, r13, r3
237	#else
238	xor r28, r2, r3
239	#endif
240
241	/* GPR29 and CR are equal most of the time */
242	addi r29, r3, 24
243
244	/* GPR30 contains the MSR pattern */
245	mfmsr r30
246	xor r30, r30, r3
247
248	/* GPR31 contains the stack pointer */
249	mr r31, r1
250
251	#ifdef PPC_MULTILIB_FPU
252	.macro FILL_F i
253	addi r4, r3, 0x100 + \i
254	stw r4, FTMP_OFFSET(r1)
255	addi r4, r3, 0x200 + \i
256	stw r4, FTMP_OFFSET + 4(r1)
257	lfd \i, FTMP_OFFSET(r1)
258	.endm
259
260	FILL_F 0
261	FILL_F 1
262	FILL_F 2
263	FILL_F 3
264	FILL_F 4
265	FILL_F 5
266	FILL_F 6
267	FILL_F 7
268	FILL_F 8
269	FILL_F 9
270	FILL_F 10
271	FILL_F 11
272	FILL_F 12
273	FILL_F 13
274	FILL_F 14
275	FILL_F 15
276	FILL_F 16
277	FILL_F 17
278	FILL_F 18
279	FILL_F 19
280	FILL_F 20
281	FILL_F 21
282	FILL_F 22
283	FILL_F 23
284	FILL_F 24
285	FILL_F 25
286	FILL_F 26
287	FILL_F 27
288	FILL_F 28
289	FILL_F 29
290	FILL_F 30
291	FILL_F 31
292	#endif
293
294	#ifdef PPC_MULTILIB_ALTIVEC
295	.macro FILL_V i
296	addi r4, r3, 0x300 + \i
297	stw r4, VTMP_OFFSET(r1)
298	addi r4, r3, 0x400 + \i
299	stw r4, VTMP_OFFSET + 4(r1)
300	addi r4, r3, 0x500 + \i
301	stw r4, VTMP_OFFSET + 8(r1)
302	addi r4, r3, 0x600 + \i
303	stw r4, VTMP_OFFSET + 12(r1)
304	li r4, VTMP_OFFSET
305	lvx \i, r1, r4
306	.endm
307
308	FILL_V 0
309	FILL_V 1
310	FILL_V 2
311	FILL_V 3
312	FILL_V 4
313	FILL_V 5
314	FILL_V 6
315	FILL_V 7
316	FILL_V 8
317	FILL_V 9
318	FILL_V 10
319	FILL_V 11
320	FILL_V 12
321	FILL_V 13
322	FILL_V 14
323	FILL_V 15
324	FILL_V 16
325	FILL_V 17
326	FILL_V 18
327	FILL_V 19
328	FILL_V 20
329	FILL_V 21
330	FILL_V 22
331	FILL_V 23
332	FILL_V 24
333	FILL_V 25
334	FILL_V 26
335	FILL_V 27
336	FILL_V 28
337	FILL_V 29
338	FILL_V 30
339	FILL_V 31
340	addi r4, r3, 0x700
341	mtvrsave r4
342	#endif
343
344	/* Check */
345	check:
346	mfcr r4
347	cmpw r4, r29
348	bne restore
349	addi r4, r3, 1
350	PPC_REG_CMP r4, r5
351	bne restore
352	addi r4, r3, 2
353	PPC_REG_CMP r4, r6
354	bne restore
355	addi r4, r3, 3
356	PPC_REG_CMP r4, r7
357	bne restore
358	addi r4, r3, 4
359	PPC_REG_CMP r4, r8
360	bne restore
361	addi r4, r3, 5
362	PPC_REG_CMP r4, r9
363	bne restore
364	addi r4, r3, 6
365	PPC_REG_CMP r4, r10
366	bne restore
367	addi r4, r3, 7
368	PPC_REG_CMP r4, r11
369	bne restore
370	addi r4, r3, 8
371	PPC_REG_CMP r4, r12
372	bne restore
373	#ifdef __powerpc64__
374	lis r4, .TOC.@highest
375	ori r4, r4, .TOC.@higher
376	rldicr r4, r4, 32, 31
377	oris r4, r4, .TOC.@h
378	ori r4, r4, .TOC.@l
379	PPC_REG_CMP r4, r2
380	#else
381	lis r4, _SDA_BASE_@h
382	ori r4, r4, _SDA_BASE_@l
383	PPC_REG_CMP r4, r13
384	#endif
385	bne restore
386	addi r4, r3, 9
387	PPC_REG_CMP r4, r14
388	bne restore
389	addi r4, r3, 10
390	PPC_REG_CMP r4, r15
391	bne restore
392	addi r4, r3, 11
393	PPC_REG_CMP r4, r16
394	bne restore
395	addi r4, r3, 12
396	PPC_REG_CMP r4, r17
397	bne restore
398	addi r4, r3, 13
399	PPC_REG_CMP r4, r18
400	bne restore
401	addi r4, r3, 14
402	PPC_REG_CMP r4, r19
403	bne restore
404	addi r4, r3, 15
405	PPC_REG_CMP r4, r20
406	bne restore
407	addi r4, r3, 16
408	PPC_REG_CMP r4, r21
409	bne restore
410	addi r4, r3, 17
411	PPC_REG_CMP r4, r22
412	bne restore
413	addi r4, r3, 18
414	PPC_REG_CMP r4, r23
415	bne restore
416	addi r4, r3, 19
417	PPC_REG_CMP r4, r24
418	bne restore
419	addi r4, r3, 20
420	PPC_REG_CMP r4, r25
421	bne restore
422	addi r4, r3, 21
423	PPC_REG_CMP r4, r26
424	bne restore
425	addi r4, r3, 22
426	PPC_REG_CMP r4, r27
427	bne restore
428	#ifdef __powerpc64__
429	xor r4, r13, r3
430	#else
431	xor r4, r2, r3
432	#endif
433	PPC_REG_CMP r4, r28
434	bne restore
435	addi r4, r3, 24
436	PPC_REG_CMP r4, r29
437	bne restore
438	mfmsr r4
439	xor r4, r4, r3
440	PPC_REG_CMP r4, r30
441	bne restore
442	addi r4, r3, 25
443	mflr r5
444	PPC_REG_CMP r4, r5
445	bne restore
446	addi r4, r3, 26
447	mfctr r5
448	PPC_REG_CMP r4, r5
449	bne restore
450	rlwinm r4, r3, 0, 25, 2
451	mfxer r5
452	cmpw r4, r5
453	bne restore
454	addi r4, r3, 28
455	PPC_REG_CMP r4, r0
456	bne restore
457	PPC_REG_CMP r31, r1
458	bne restore
459
460	#ifdef PPC_MULTILIB_FPU
461	.macro CHECK_F i
462	stfd \i, FTMP_OFFSET(r1)
463	lwz r5, FTMP_OFFSET(r1)
464	addi r4, r3, 0x100 + \i
465	cmpw r5, r4
466	bne restore
467	lwz r5, FTMP_OFFSET + 4(r1)
468	addi r4, r3, 0x200 + \i
469	cmpw r5, r4
470	bne restore
471	.endm
472
473	/* Check FPSCR */
474	stfd f0, FTMP_OFFSET(r1)
475	mffs f0
476	stfd f0, FTMP2_OFFSET(r1)
477	lwz r4, FTMP2_OFFSET + 4(r1)
478	lwz r5, FPSCR_OFFSET + 4(r1)
479	cmpw r5, r4
480	bne restore
481	lfd f0, FTMP_OFFSET(r1)
482
483	CHECK_F 0
484	CHECK_F 1
485	CHECK_F 2
486	CHECK_F 3
487	CHECK_F 4
488	CHECK_F 5
489	CHECK_F 6
490	CHECK_F 7
491	CHECK_F 8
492	CHECK_F 9
493	CHECK_F 10
494	CHECK_F 11
495	CHECK_F 12
496	CHECK_F 13
497	CHECK_F 14
498	CHECK_F 15
499	CHECK_F 16
500	CHECK_F 17
501	CHECK_F 18
502	CHECK_F 19
503	CHECK_F 20
504	CHECK_F 21
505	CHECK_F 22
506	CHECK_F 23
507	CHECK_F 24
508	CHECK_F 25
509	CHECK_F 26
510	CHECK_F 27
511	CHECK_F 28
512	CHECK_F 29
513	CHECK_F 30
514	CHECK_F 31
515	#endif
516
517	#ifdef PPC_MULTILIB_ALTIVEC
518	.macro CHECK_V i
519	li r4, VTMP_OFFSET
520	stvx \i, r1, r4
521	lwz r5, VTMP_OFFSET(r1)
522	addi r4, r3, 0x300 + \i
523	cmpw r5, r4
524	bne restore
525	lwz r5, VTMP_OFFSET + 4(r1)
526	addi r4, r3, 0x400 + \i
527	cmpw r5, r4
528	bne restore
529	lwz r5, VTMP_OFFSET + 8(r1)
530	addi r4, r3, 0x500 + \i
531	cmpw r5, r4
532	bne restore
533	lwz r5, VTMP_OFFSET + 12(r1)
534	addi r4, r3, 0x600 + \i
535	cmpw r5, r4
536	bne restore
537	.endm
538
539	/* Check VSCR */
540	li r4, VTMP_OFFSET
541	stvx v0, r1, r4
542	mfvscr v0
543	li r4, VTMP2_OFFSET + 12
544	stvewx v0, r1, r4
545	lwz r4, VTMP2_OFFSET + 12(r1)
546	lwz r5, VSCR_OFFSET(r1)
547	cmpw r5, r4
548	bne restore
549	li r4, VTMP_OFFSET
550	lvx v0, r1, r4
551
552	CHECK_V 0
553	CHECK_V 1
554	CHECK_V 2
555	CHECK_V 3
556	CHECK_V 4
557	CHECK_V 5
558	CHECK_V 6
559	CHECK_V 7
560	CHECK_V 8
561	CHECK_V 9
562	CHECK_V 10
563	CHECK_V 11
564	CHECK_V 12
565	CHECK_V 13
566	CHECK_V 14
567	CHECK_V 15
568	CHECK_V 16
569	CHECK_V 17
570	CHECK_V 18
571	CHECK_V 19
572	CHECK_V 20
573	CHECK_V 21
574	CHECK_V 22
575	CHECK_V 23
576	CHECK_V 24
577	CHECK_V 25
578	CHECK_V 26
579	CHECK_V 27
580	CHECK_V 28
581	CHECK_V 29
582	CHECK_V 30
583	CHECK_V 31
584	mfvrsave r5
585	addi r4, r3, 0x700
586	cmpw r5, r4
587	bne restore
588	#endif
589
590	mtcr r29
591	addi r5, r3, 1
592	b check
593
594	/* Restore */
595	restore:
596
597	#ifdef PPC_MULTILIB_ALTIVEC
598	lwz r0, VRSAVE_OFFSET(r1)
599	mtvrsave r0
600	li r0, V31_OFFSET
601	lvx v31, r1, r0
602	li r0, V30_OFFSET
603	lvx v30, r1, r0
604	li r0, V29_OFFSET
605	lvx v29, r1, r0
606	li r0, V28_OFFSET
607	lvx v28, r1, r0
608	li r0, V27_OFFSET
609	lvx v27, r1, r0
610	li r0, V26_OFFSET
611	lvx v26, r1, r0
612	li r0, V25_OFFSET
613	lvx v25, r1, r0
614	li r0, V24_OFFSET
615	lvx v24, r1, r0
616	li r0, V23_OFFSET
617	lvx v23, r1, r0
618	li r0, V22_OFFSET
619	lvx v22, r1, r0
620	li r0, V21_OFFSET
621	lvx v21, r1, r0
622	li r0, V20_OFFSET
623	lvx v20, r1, r0
624	#endif
625
626	#ifdef PPC_MULTILIB_FPU
627	lfd f31, F31_OFFSET(r1)
628	lfd f30, F30_OFFSET(r1)
629	lfd f29, F29_OFFSET(r1)
630	lfd f28, F28_OFFSET(r1)
631	lfd f27, F27_OFFSET(r1)
632	lfd f26, F26_OFFSET(r1)
633	lfd f25, F25_OFFSET(r1)
634	lfd f24, F24_OFFSET(r1)
635	lfd f23, F23_OFFSET(r1)
636	lfd f22, F22_OFFSET(r1)
637	lfd f21, F21_OFFSET(r1)
638	lfd f20, F20_OFFSET(r1)
639	lfd f19, F19_OFFSET(r1)
640	lfd f18, F18_OFFSET(r1)
641	lfd f17, F17_OFFSET(r1)
642	lfd f16, F16_OFFSET(r1)
643	lfd f15, F15_OFFSET(r1)
644	lfd f14, F14_OFFSET(r1)
645	#endif
646
647	PPC_REG_LOAD r31, GPR31_OFFSET(r1)
648	PPC_REG_LOAD r30, GPR30_OFFSET(r1)
649	PPC_REG_LOAD r29, GPR29_OFFSET(r1)
650	PPC_REG_LOAD r28, GPR28_OFFSET(r1)
651	PPC_REG_LOAD r27, GPR27_OFFSET(r1)
652	PPC_REG_LOAD r26, GPR26_OFFSET(r1)
653	PPC_REG_LOAD r25, GPR25_OFFSET(r1)
654	PPC_REG_LOAD r24, GPR24_OFFSET(r1)
655	PPC_REG_LOAD r23, GPR23_OFFSET(r1)
656	PPC_REG_LOAD r22, GPR22_OFFSET(r1)
657	PPC_REG_LOAD r21, GPR21_OFFSET(r1)
658	PPC_REG_LOAD r20, GPR20_OFFSET(r1)
659	PPC_REG_LOAD r19, GPR19_OFFSET(r1)
660	PPC_REG_LOAD r18, GPR18_OFFSET(r1)
661	PPC_REG_LOAD r17, GPR17_OFFSET(r1)
662	PPC_REG_LOAD r16, GPR16_OFFSET(r1)
663	PPC_REG_LOAD r15, GPR15_OFFSET(r1)
664	PPC_REG_LOAD r14, GPR14_OFFSET(r1)
665	lwz r4, CR_OFFSET(r1)
666	mtcr r4
667	PPC_REG_LOAD r4, LR_OFFSET(r1)
668	mtlr r4
669	addi r1, r1, FRAME_SIZE
670	blr

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