source: rtems/cpukit/score/cpu/powerpc/include/rtems/score/cpuimpl.h @ bc16c65

5
Last change on this file since bc16c65 was 2afb22b, checked in by Chris Johns <chrisj@…>, on Dec 23, 2017 at 7:18:56 AM

Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

  • The make preinstall step itself needs time and disk space.
  • Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error.
  • There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult.
  • The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit.
  • An introduction of a new build system is difficult.
  • Include paths specified by the -B option are system headers. This may suppress warnings.
  • The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

  • cpukit/include
  • cpukit/score/cpu/@RTEMS_CPU@/include
  • cpukit/libnetworking

The new BSP include directories are:

  • bsps/include
  • bsps/@RTEMS_CPU@/include
  • bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

  • Property mode set to 100644
File size: 7.3 KB
Line 
1/**
2 * @file
3 *
4 * @brief CPU Port Implementation API
5 */
6
7/*
8 * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr)
9 *                    Canon Centre Recherche France.
10 *
11 * Copyright (C) 2007 Till Straumann <strauman@slac.stanford.edu>
12 *
13 * Copyright (c) 2009, 2017 embedded brains GmbH
14 *
15 * The license and distribution terms for this file may be
16 * found in the file LICENSE in this distribution or at
17 * http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPUIMPL_H
21#define _RTEMS_SCORE_CPUIMPL_H
22
23#include <rtems/score/cpu.h>
24
25/* Exception stack frame -> BSP_Exception_frame */
26#ifdef __powerpc64__
27  #define FRAME_LINK_SPACE 32
28#else
29  #define FRAME_LINK_SPACE 8
30#endif
31
32#define SRR0_FRAME_OFFSET FRAME_LINK_SPACE
33#define SRR1_FRAME_OFFSET (SRR0_FRAME_OFFSET + PPC_REG_SIZE)
34#define EXCEPTION_NUMBER_OFFSET (SRR1_FRAME_OFFSET + PPC_REG_SIZE)
35#define PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET (EXCEPTION_NUMBER_OFFSET + 4)
36#define EXC_CR_OFFSET (EXCEPTION_NUMBER_OFFSET + 8)
37#define EXC_XER_OFFSET (EXC_CR_OFFSET + 4)
38#define EXC_CTR_OFFSET (EXC_XER_OFFSET + 4)
39#define EXC_LR_OFFSET (EXC_CTR_OFFSET + PPC_REG_SIZE)
40#define PPC_EXC_INTERRUPT_FRAME_OFFSET (EXC_LR_OFFSET + PPC_REG_SIZE)
41
42#ifndef __SPE__
43  #define PPC_EXC_GPR_OFFSET(gpr) \
44    ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE)
45  #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3)
46  #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU)
47    #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33)
48    #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28)
49    #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4)
50    #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_VR_OFFSET(32))
51    #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32)
52    #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34)
53    #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12)
54    #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4)
55    #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_MIN_VR_OFFSET(20))
56    #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14)
57    #define CPU_INTERRUPT_FRAME_SIZE \
58      (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE)
59  #elif defined(PPC_MULTILIB_ALTIVEC)
60    #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33)
61    #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28)
62    #define PPC_EXC_VR_OFFSET(v) ((v) * 16 + PPC_EXC_VSCR_OFFSET + 4)
63    #define PPC_EXC_FRAME_SIZE PPC_EXC_VR_OFFSET(32)
64    #define PPC_EXC_MIN_VSCR_OFFSET (PPC_EXC_GPR_OFFSET(13) + 12)
65    #define PPC_EXC_MIN_VR_OFFSET(v) ((v) * 16 + PPC_EXC_MIN_VSCR_OFFSET + 4)
66    #define CPU_INTERRUPT_FRAME_SIZE \
67      (PPC_EXC_MIN_VR_OFFSET(20) + PPC_STACK_RED_ZONE_SIZE)
68  #elif defined(PPC_MULTILIB_FPU)
69    #define PPC_EXC_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(33))
70    #define PPC_EXC_FPSCR_OFFSET PPC_EXC_FR_OFFSET(32)
71    #define PPC_EXC_FRAME_SIZE PPC_EXC_FR_OFFSET(34)
72    #define PPC_EXC_MIN_FR_OFFSET(f) ((f) * 8 + PPC_EXC_GPR_OFFSET(13))
73    #define PPC_EXC_MIN_FPSCR_OFFSET PPC_EXC_MIN_FR_OFFSET(14)
74    #define CPU_INTERRUPT_FRAME_SIZE \
75      (PPC_EXC_MIN_FR_OFFSET(16) + PPC_STACK_RED_ZONE_SIZE)
76  #else
77    #define PPC_EXC_FRAME_SIZE PPC_EXC_GPR_OFFSET(33)
78    #define CPU_INTERRUPT_FRAME_SIZE \
79      (PPC_EXC_GPR_OFFSET(13) + PPC_STACK_RED_ZONE_SIZE)
80  #endif
81#else
82  #define PPC_EXC_SPEFSCR_OFFSET 44
83  #define PPC_EXC_ACC_OFFSET 48
84  #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56)
85  #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4)
86  #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE)
87  #define PPC_EXC_FRAME_SIZE 320
88#endif
89
90#define GPR0_OFFSET PPC_EXC_GPR_OFFSET(0)
91#define GPR1_OFFSET PPC_EXC_GPR_OFFSET(1)
92#define GPR2_OFFSET PPC_EXC_GPR_OFFSET(2)
93#define GPR3_OFFSET PPC_EXC_GPR_OFFSET(3)
94#define GPR4_OFFSET PPC_EXC_GPR_OFFSET(4)
95#define GPR5_OFFSET PPC_EXC_GPR_OFFSET(5)
96#define GPR6_OFFSET PPC_EXC_GPR_OFFSET(6)
97#define GPR7_OFFSET PPC_EXC_GPR_OFFSET(7)
98#define GPR8_OFFSET PPC_EXC_GPR_OFFSET(8)
99#define GPR9_OFFSET PPC_EXC_GPR_OFFSET(9)
100#define GPR10_OFFSET PPC_EXC_GPR_OFFSET(10)
101#define GPR11_OFFSET PPC_EXC_GPR_OFFSET(11)
102#define GPR12_OFFSET PPC_EXC_GPR_OFFSET(12)
103#define GPR13_OFFSET PPC_EXC_GPR_OFFSET(13)
104#define GPR14_OFFSET PPC_EXC_GPR_OFFSET(14)
105#define GPR15_OFFSET PPC_EXC_GPR_OFFSET(15)
106#define GPR16_OFFSET PPC_EXC_GPR_OFFSET(16)
107#define GPR17_OFFSET PPC_EXC_GPR_OFFSET(17)
108#define GPR18_OFFSET PPC_EXC_GPR_OFFSET(18)
109#define GPR19_OFFSET PPC_EXC_GPR_OFFSET(19)
110#define GPR20_OFFSET PPC_EXC_GPR_OFFSET(20)
111#define GPR21_OFFSET PPC_EXC_GPR_OFFSET(21)
112#define GPR22_OFFSET PPC_EXC_GPR_OFFSET(22)
113#define GPR23_OFFSET PPC_EXC_GPR_OFFSET(23)
114#define GPR24_OFFSET PPC_EXC_GPR_OFFSET(24)
115#define GPR25_OFFSET PPC_EXC_GPR_OFFSET(25)
116#define GPR26_OFFSET PPC_EXC_GPR_OFFSET(26)
117#define GPR27_OFFSET PPC_EXC_GPR_OFFSET(27)
118#define GPR28_OFFSET PPC_EXC_GPR_OFFSET(28)
119#define GPR29_OFFSET PPC_EXC_GPR_OFFSET(29)
120#define GPR30_OFFSET PPC_EXC_GPR_OFFSET(30)
121#define GPR31_OFFSET PPC_EXC_GPR_OFFSET(31)
122
123#define CPU_PER_CPU_CONTROL_SIZE 0
124
125#ifdef RTEMS_SMP
126
127/* Use SPRG0 for the per-CPU control of the current processor */
128#define PPC_PER_CPU_CONTROL_REGISTER 272
129
130#endif /* RTEMS_SMP */
131
132#ifndef ASM
133
134#ifdef __cplusplus
135extern "C" {
136#endif
137
138typedef struct {
139  uintptr_t FRAME_SP;
140  #ifdef __powerpc64__
141    uint32_t FRAME_CR;
142    uint32_t FRAME_RESERVED;
143  #endif
144  uintptr_t FRAME_LR;
145  #ifdef __powerpc64__
146    uintptr_t FRAME_TOC;
147  #endif
148  uintptr_t EXC_SRR0;
149  uintptr_t EXC_SRR1;
150  uint32_t RESERVED_FOR_ALIGNMENT_0;
151  uint32_t EXC_INTERRUPT_ENTRY_INSTANT;
152  uint32_t EXC_CR;
153  uint32_t EXC_XER;
154  uintptr_t EXC_CTR;
155  uintptr_t EXC_LR;
156  uintptr_t EXC_INTERRUPT_FRAME;
157  #ifdef __SPE__
158    uint32_t EXC_SPEFSCR;
159    uint64_t EXC_ACC;
160  #endif
161  PPC_GPR_TYPE GPR0;
162  PPC_GPR_TYPE GPR1;
163  PPC_GPR_TYPE GPR2;
164  PPC_GPR_TYPE GPR3;
165  PPC_GPR_TYPE GPR4;
166  PPC_GPR_TYPE GPR5;
167  PPC_GPR_TYPE GPR6;
168  PPC_GPR_TYPE GPR7;
169  PPC_GPR_TYPE GPR8;
170  PPC_GPR_TYPE GPR9;
171  PPC_GPR_TYPE GPR10;
172  PPC_GPR_TYPE GPR11;
173  PPC_GPR_TYPE GPR12;
174  #ifdef PPC_MULTILIB_ALTIVEC
175    /* This field must take stvewx/lvewx requirements into account */
176    uint32_t RESERVED_FOR_ALIGNMENT_3[3];
177    uint32_t VSCR;
178
179    uint8_t V0[16];
180    uint8_t V1[16];
181    uint8_t V2[16];
182    uint8_t V3[16];
183    uint8_t V4[16];
184    uint8_t V5[16];
185    uint8_t V6[16];
186    uint8_t V7[16];
187    uint8_t V8[16];
188    uint8_t V9[16];
189    uint8_t V10[16];
190    uint8_t V11[16];
191    uint8_t V12[16];
192    uint8_t V13[16];
193    uint8_t V14[16];
194    uint8_t V15[16];
195    uint8_t V16[16];
196    uint8_t V17[16];
197    uint8_t V18[16];
198    uint8_t V19[16];
199  #endif
200  #ifdef PPC_MULTILIB_FPU
201    double F0;
202    double F1;
203    double F2;
204    double F3;
205    double F4;
206    double F5;
207    double F6;
208    double F7;
209    double F8;
210    double F9;
211    double F10;
212    double F11;
213    double F12;
214    double F13;
215    uint64_t FPSCR;
216    uint64_t RESERVED_FOR_ALIGNMENT_4;
217  #endif
218  #if PPC_STACK_RED_ZONE_SIZE > 0
219    uint8_t RED_ZONE[ PPC_STACK_RED_ZONE_SIZE ];
220  #endif
221} CPU_Interrupt_frame;
222
223#ifdef RTEMS_SMP
224
225static inline struct Per_CPU_Control *_PPC_Get_current_per_CPU_control( void )
226{
227  struct Per_CPU_Control *cpu_self;
228
229  __asm__ volatile (
230    "mfspr %0, " RTEMS_XSTRING( PPC_PER_CPU_CONTROL_REGISTER )
231    : "=r" ( cpu_self )
232  );
233
234  return cpu_self;
235}
236
237#define _CPU_Get_current_per_CPU_control() _PPC_Get_current_per_CPU_control()
238
239#endif /* RTEMS_SMP */
240
241#ifdef __cplusplus
242}
243#endif
244
245#endif /* ASM */
246
247#endif /* _RTEMS_SCORE_CPUIMPL_H */
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