source: rtems/cpukit/score/cpu/powerpc/include/rtems/score/cpu.h @ 718a84af

5
Last change on this file since 718a84af was 718a84af, checked in by Sebastian Huber <sebastian.huber@…>, on 06/27/18 at 06:17:26

Remove unused CPU_MODES_INTERRUPT_LEVEL

  • Property mode set to 100644
File size: 36.9 KB
Line 
1/**
2 * @file
3 *
4 * @brief PowerPC CPU Department Source
5 */
6
7/*
8 *  COPYRIGHT (c) 1989-2012.
9 *  On-Line Applications Research Corporation (OAR).
10 *
11 *  COPYRIGHT (c) 1995 i-cubed ltd.
12 *
13 *  To anyone who acknowledges that this file is provided "AS IS"
14 *  without any express or implied warranty:
15 *      permission to use, copy, modify, and distribute this file
16 *      for any purpose is hereby granted without fee, provided that
17 *      the above copyright notice and this notice appears in all
18 *      copies, and that the name of i-cubed limited not be used in
19 *      advertising or publicity pertaining to distribution of the
20 *      software without specific, written prior permission.
21 *      i-cubed limited makes no representations about the suitability
22 *      of this software for any purpose.
23 *
24 *  Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>.
25 *
26 *  Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL).
27 *
28 *  Copyright (c) 2010, 2017 embedded brains GmbH.
29 *
30 *  The license and distribution terms for this file may be
31 *  found in the file LICENSE in this distribution or at
32 *  http://www.rtems.org/license/LICENSE.
33 */
34
35#ifndef _RTEMS_SCORE_CPU_H
36#define _RTEMS_SCORE_CPU_H
37
38#include <rtems/score/basedefs.h>
39#if defined(RTEMS_PARAVIRT)
40#include <rtems/score/paravirt.h>
41#endif
42#include <rtems/score/powerpc.h>
43#include <rtems/powerpc/registers.h>
44
45#ifndef ASM
46  #include <string.h> /* for memset() */
47#endif
48
49#ifdef __cplusplus
50extern "C" {
51#endif
52
53/* conditional compilation parameters */
54
55/*
56 *  Does this port provide a CPU dependent IDLE task implementation?
57 *
58 *  If TRUE, then the routine _CPU_Thread_Idle_body
59 *  must be provided and is the default IDLE thread body instead of
60 *  _CPU_Thread_Idle_body.
61 *
62 *  If FALSE, then use the generic IDLE thread body if the BSP does
63 *  not provide one.
64 *
65 *  This is intended to allow for supporting processors which have
66 *  a low power or idle mode.  When the IDLE thread is executed, then
67 *  the CPU can be powered down.
68 *
69 *  The order of precedence for selecting the IDLE thread body is:
70 *
71 *    1.  BSP provided
72 *    2.  CPU dependent (if provided)
73 *    3.  generic (if no BSP and no CPU dependent)
74 */
75
76#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
77
78/*
79 *  Does the stack grow up (toward higher addresses) or down
80 *  (toward lower addresses)?
81 *
82 *  If TRUE, then the grows upward.
83 *  If FALSE, then the grows toward smaller addresses.
84 */
85
86#define CPU_STACK_GROWS_UP               FALSE
87
88#define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT
89
90#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
91
92/*
93 *  Does the CPU have hardware floating point?
94 *
95 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
96 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
97 *
98 *  If there is a FP coprocessor such as the i387 or mc68881, then
99 *  the answer is TRUE.
100 *
101 *  The macro name "PPC_HAS_FPU" should be made CPU specific.
102 *  It indicates whether or not this CPU model has FP support.  For
103 *  example, it would be possible to have an i386_nofp CPU model
104 *  which set this to false to indicate that you have an i386 without
105 *  an i387 and wish to leave floating point support out of RTEMS.
106 */
107
108#if ( PPC_HAS_FPU == 1 )
109#define CPU_HARDWARE_FP     TRUE
110#define CPU_SOFTWARE_FP     FALSE
111#else
112#define CPU_HARDWARE_FP     FALSE
113#define CPU_SOFTWARE_FP     FALSE
114#endif
115
116/*
117 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
118 *
119 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
120 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
121 *
122 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
123 *
124 *  PowerPC Note: It appears the GCC can implicitly generate FPU
125 *  and Altivec instructions when you least expect them.  So make
126 *  all tasks floating point.
127 */
128
129#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
130
131/*
132 *  Should the IDLE task have a floating point context?
133 *
134 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
135 *  and it has a floating point context which is switched in and out.
136 *  If FALSE, then the IDLE task does not have a floating point context.
137 *
138 *  Setting this to TRUE negatively impacts the time required to preempt
139 *  the IDLE task from an interrupt because the floating point context
140 *  must be saved as part of the preemption.
141 */
142
143#define CPU_IDLE_TASK_IS_FP      FALSE
144
145#define CPU_MAXIMUM_PROCESSORS 32
146
147/*
148 *  Processor defined structures required for cpukit/score.
149 */
150
151/*
152 * Contexts
153 *
154 *  Generally there are 2 types of context to save.
155 *     1. Interrupt registers to save
156 *     2. Task level registers to save
157 *
158 *  This means we have the following 3 context items:
159 *     1. task level context stuff::  Context_Control
160 *     2. floating point task stuff:: Context_Control_fp
161 *     3. special interrupt level context :: Context_Control_interrupt
162 *
163 *  On some processors, it is cost-effective to save only the callee
164 *  preserved registers during a task context switch.  This means
165 *  that the ISR code needs to save those registers which do not
166 *  persist across function calls.  It is not mandatory to make this
167 *  distinctions between the caller/callee saves registers for the
168 *  purpose of minimizing context saved during task switch and on interrupts.
169 *  If the cost of saving extra registers is minimal, simplicity is the
170 *  choice.  Save the same context on interrupt entry as for tasks in
171 *  this case.
172 *
173 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
174 *  care should be used in designing the context area.
175 *
176 *  On some CPUs with hardware floating point support, the Context_Control_fp
177 *  structure will not be used or it simply consist of an array of a
178 *  fixed number of bytes.   This is done when the floating point context
179 *  is dumped by a "FP save context" type instruction and the format
180 *  is not really defined by the CPU.  In this case, there is no need
181 *  to figure out the exact format -- only the size.  Of course, although
182 *  this is enough information for RTEMS, it is probably not enough for
183 *  a debugger such as gdb.  But that is another problem.
184 */
185
186#ifndef __SPE__
187  #define PPC_GPR_TYPE uintptr_t
188  #if defined(__powerpc64__)
189    #define PPC_GPR_SIZE 8
190    #define PPC_GPR_LOAD ld
191    #define PPC_GPR_STORE std
192  #else
193    #define PPC_GPR_SIZE 4
194    #define PPC_GPR_LOAD lwz
195    #define PPC_GPR_STORE stw
196  #endif
197#else
198  #define PPC_GPR_TYPE uint64_t
199  #define PPC_GPR_SIZE 8
200  #define PPC_GPR_LOAD evldd
201  #define PPC_GPR_STORE evstdd
202#endif
203
204#if defined(__powerpc64__)
205  #define PPC_REG_SIZE 8
206  #define PPC_REG_LOAD ld
207  #define PPC_REG_STORE std
208  #define PPC_REG_STORE_UPDATE stdu
209  #define PPC_REG_CMP cmpd
210#else
211  #define PPC_REG_SIZE 4
212  #define PPC_REG_LOAD lwz
213  #define PPC_REG_STORE stw
214  #define PPC_REG_STORE_UPDATE stwu
215  #define PPC_REG_CMP cmpw
216#endif
217
218#ifndef ASM
219
220/*
221 * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according
222 * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 -
223 * Linux and Embedded")
224 */
225typedef struct {
226  uint32_t msr;
227  uint32_t cr;
228  uintptr_t gpr1;
229  uintptr_t lr;
230  PPC_GPR_TYPE gpr14;
231  PPC_GPR_TYPE gpr15;
232  PPC_GPR_TYPE gpr16;
233  PPC_GPR_TYPE gpr17;
234  PPC_GPR_TYPE gpr18;
235  PPC_GPR_TYPE gpr19;
236  PPC_GPR_TYPE gpr20;
237  PPC_GPR_TYPE gpr21;
238  PPC_GPR_TYPE gpr22;
239  PPC_GPR_TYPE gpr23;
240  PPC_GPR_TYPE gpr24;
241  PPC_GPR_TYPE gpr25;
242  PPC_GPR_TYPE gpr26;
243  PPC_GPR_TYPE gpr27;
244  PPC_GPR_TYPE gpr28;
245  PPC_GPR_TYPE gpr29;
246  PPC_GPR_TYPE gpr30;
247  PPC_GPR_TYPE gpr31;
248  uint32_t isr_dispatch_disable;
249  uint32_t reserved_for_alignment;
250  #if defined(PPC_MULTILIB_ALTIVEC)
251    uint8_t v20[16];
252    uint8_t v21[16];
253    uint8_t v22[16];
254    uint8_t v23[16];
255    uint8_t v24[16];
256    uint8_t v25[16];
257    uint8_t v26[16];
258    uint8_t v27[16];
259    uint8_t v28[16];
260    uint8_t v29[16];
261    uint8_t v30[16];
262    uint8_t v31[16];
263    uint32_t vrsave;
264  #elif defined(__ALTIVEC__)
265    /*
266     * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave
267     * and padding to ensure cache-alignment.  Unfortunately, we can't verify
268     * the cache line size here in the cpukit but altivec support code will
269     * produce an error if this is ever different from 32 bytes.
270     *
271     * Note: it is the BSP/CPU-support's responsibility to save/restore
272     *       volatile vregs across interrupts and exceptions.
273     */
274    uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE];
275  #endif
276  #if defined(PPC_MULTILIB_FPU)
277    double f14;
278    double f15;
279    double f16;
280    double f17;
281    double f18;
282    double f19;
283    double f20;
284    double f21;
285    double f22;
286    double f23;
287    double f24;
288    double f25;
289    double f26;
290    double f27;
291    double f28;
292    double f29;
293    double f30;
294    double f31;
295  #endif
296  /*
297   * The following items are at the structure end, so that we can use dcbz for
298   * the previous items to optimize the context switch.  We must not set the
299   * following items to zero via the dcbz.
300   */
301  uintptr_t tp;
302  #if defined(RTEMS_SMP)
303    volatile uint32_t is_executing;
304  #endif
305} ppc_context;
306
307typedef struct {
308  uint8_t context [
309    PPC_DEFAULT_CACHE_LINE_SIZE
310      + sizeof(ppc_context)
311      + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0
312        ? 0
313          : PPC_DEFAULT_CACHE_LINE_SIZE
314            - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE)
315  ];
316} Context_Control;
317
318static inline ppc_context *ppc_get_context( const Context_Control *context )
319{
320  uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE;
321  uintptr_t mask = clsz - 1;
322  uintptr_t addr = (uintptr_t) context;
323
324  return (ppc_context *) ((addr & ~mask) + clsz);
325}
326
327#define _CPU_Context_Get_SP( _context ) \
328  ppc_get_context(_context)->gpr1
329
330#ifdef RTEMS_SMP
331  static inline bool _CPU_Context_Get_is_executing(
332    const Context_Control *context
333  )
334  {
335    return ppc_get_context(context)->is_executing;
336  }
337
338  static inline void _CPU_Context_Set_is_executing(
339    Context_Control *context,
340    bool is_executing
341  )
342  {
343    ppc_get_context(context)->is_executing = is_executing;
344  }
345#endif
346#endif /* ASM */
347
348#define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE)
349#define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4)
350#define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8)
351#define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8)
352
353#define PPC_CONTEXT_GPR_OFFSET( gpr ) \
354  (((gpr) - 14) * PPC_GPR_SIZE + \
355    PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE)
356
357#define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 )
358#define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 )
359#define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 )
360#define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 )
361#define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 )
362#define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 )
363#define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 )
364#define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 )
365#define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 )
366#define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 )
367#define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 )
368#define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 )
369#define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 )
370#define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 )
371#define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 )
372#define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 )
373#define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 )
374#define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 )
375#define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 )
376
377#ifdef PPC_MULTILIB_ALTIVEC
378  #define PPC_CONTEXT_OFFSET_V( v ) \
379    ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8)
380  #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 )
381  #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 )
382  #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 )
383  #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 )
384  #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 )
385  #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 )
386  #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 )
387  #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 )
388  #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 )
389  #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 )
390  #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 )
391  #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 )
392  #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 )
393  #define PPC_CONTEXT_OFFSET_F( f ) \
394    ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 )
395#else
396  #define PPC_CONTEXT_OFFSET_F( f ) \
397    ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 )
398#endif
399
400#ifdef PPC_MULTILIB_FPU
401  #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 )
402  #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 )
403  #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 )
404  #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 )
405  #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 )
406  #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 )
407  #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 )
408  #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 )
409  #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 )
410  #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 )
411  #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 )
412  #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 )
413  #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 )
414  #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 )
415  #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 )
416  #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 )
417  #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 )
418  #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 )
419#endif
420
421#if defined(PPC_MULTILIB_FPU)
422  #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 )
423#elif defined(PPC_MULTILIB_ALTIVEC)
424  #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4)
425#elif defined(__ALTIVEC__)
426  #define PPC_CONTEXT_VOLATILE_SIZE \
427    (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \
428      + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE)
429#else
430  #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8)
431#endif
432
433#define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE
434
435#ifdef RTEMS_SMP
436  #define PPC_CONTEXT_OFFSET_IS_EXECUTING \
437    (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE)
438#endif
439
440#ifndef ASM
441typedef struct {
442#if (PPC_HAS_FPU == 1)
443    /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over
444     * procedure calls.  However, this would mean that the interrupt
445     * frame had to hold f0-f13, and the fpscr.  And as the majority
446     * of tasks will not have an FP context, we will save the whole
447     * context here.
448     */
449#if (PPC_HAS_DOUBLE == 1)
450    double      f[32];
451    uint64_t    fpscr;
452#else
453    float       f[32];
454    uint32_t    fpscr;
455#endif
456#endif /* (PPC_HAS_FPU == 1) */
457} Context_Control_fp;
458
459#endif /* ASM */
460
461/*
462 *  Does the CPU follow the simple vectored interrupt model?
463 *
464 *  If TRUE, then RTEMS allocates the vector table it internally manages.
465 *  If FALSE, then the BSP is assumed to allocate and manage the vector
466 *  table
467 *
468 *  PowerPC Specific Information:
469 *
470 *  The PowerPC and x86 were the first to use the PIC interrupt model.
471 *  They do not use the simple vectored interrupt model.
472 */
473#define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
474
475/*
476 *  Does RTEMS manage a dedicated interrupt stack in software?
477 *
478 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
479 *  If FALSE, nothing is done.
480 *
481 *  If the CPU supports a dedicated interrupt stack in hardware,
482 *  then it is generally the responsibility of the BSP to allocate it
483 *  and set it up.
484 *
485 *  If the CPU does not support a dedicated interrupt stack, then
486 *  the porter has two options: (1) execute interrupts on the
487 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
488 *  interrupt stack.
489 *
490 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
491 *
492 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
493 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
494 *  possible that both are FALSE for a particular CPU.  Although it
495 *  is unclear what that would imply about the interrupt processing
496 *  procedure on that CPU.
497 */
498
499#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
500
501/*
502 *  Does this CPU have hardware support for a dedicated interrupt stack?
503 *
504 *  If TRUE, then it must be installed during initialization.
505 *  If FALSE, then no installation is performed.
506 *
507 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
508 *
509 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
510 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
511 *  possible that both are FALSE for a particular CPU.  Although it
512 *  is unclear what that would imply about the interrupt processing
513 *  procedure on that CPU.
514 */
515
516#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
517
518/*
519 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
520 *
521 *  If TRUE, then the memory is allocated during initialization.
522 *  If FALSE, then the memory is allocated during initialization.
523 *
524 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
525 */
526
527#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
528
529/*
530 *  Does the RTEMS invoke the user's ISR with the vector number and
531 *  a pointer to the saved interrupt frame (1) or just the vector
532 *  number (0)?
533 */
534
535#define CPU_ISR_PASSES_FRAME_POINTER FALSE
536
537/*
538 *  Should the saving of the floating point registers be deferred
539 *  until a context switch is made to another different floating point
540 *  task?
541 *
542 *  If TRUE, then the floating point context will not be stored until
543 *  necessary.  It will remain in the floating point registers and not
544 *  disturned until another floating point task is switched to.
545 *
546 *  If FALSE, then the floating point context is saved when a floating
547 *  point task is switched out and restored when the next floating point
548 *  task is restored.  The state of the floating point registers between
549 *  those two operations is not specified.
550 *
551 *  If the floating point context does NOT have to be saved as part of
552 *  interrupt dispatching, then it should be safe to set this to TRUE.
553 *
554 *  Setting this flag to TRUE results in using a different algorithm
555 *  for deciding when to save and restore the floating point context.
556 *  The deferred FP switch algorithm minimizes the number of times
557 *  the FP context is saved and restored.  The FP context is not saved
558 *  until a context switch is made to another, different FP task.
559 *  Thus in a system with only one FP task, the FP context will never
560 *  be saved or restored.
561 *
562 *  Note, however that compilers may use floating point registers/
563 *  instructions for optimization or they may save/restore FP registers
564 *  on the stack. You must not use deferred switching in these cases
565 *  and on the PowerPC attempting to do so will raise a "FP unavailable"
566 *  exception.
567 */
568/*
569 *  ACB Note:  This could make debugging tricky..
570 */
571
572/* conservative setting (FALSE); probably doesn't affect performance too much */
573#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
574
575#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
576
577/*
578 *  Processor defined structures required for cpukit/score.
579 */
580
581#ifndef ASM
582
583/*
584 *  This variable is optional.  It is used on CPUs on which it is difficult
585 *  to generate an "uninitialized" FP context.  It is filled in by
586 *  _CPU_Initialize and copied into the task's FP context area during
587 *  _CPU_Context_Initialize.
588 */
589
590/* EXTERN Context_Control_fp  _CPU_Null_fp_context; */
591
592#endif /* ndef ASM */
593
594/*
595 *  This defines the number of levels and the mask used to pick those
596 *  bits out of a thread mode.
597 */
598
599#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
600
601/*
602 *  The size of the floating point context area.  On some CPUs this
603 *  will not be a "sizeof" because the format of the floating point
604 *  area is not defined -- only the size is.  This is usually on
605 *  CPUs with a "floating point save context" instruction.
606 */
607
608#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
609
610/*
611 * (Optional) # of bytes for libmisc/stackchk to check
612 * If not specifed, then it defaults to something reasonable
613 * for most architectures.
614 */
615
616#define CPU_STACK_CHECK_PATTERN_INITIALIZER \
617  { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
618    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
619    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
620    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
621    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
622    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
623    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \
624    0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 }
625
626/*
627 *  Amount of extra stack (above minimum stack size) required by
628 *  MPCI receive server thread.  Remember that in a multiprocessor
629 *  system this thread must exist and be able to process all directives.
630 */
631
632#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
633
634/*
635 *  This is defined if the port has a special way to report the ISR nesting
636 *  level.  Most ports maintain the variable _ISR_Nest_level. Note that
637 *  this is not an option - RTEMS/score _relies_ on _ISR_Nest_level
638 *  being maintained (e.g. watchdog queues).
639 */
640
641#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
642
643/*
644 *  ISR handler macros
645 */
646
647/*
648 *  Disable all interrupts for an RTEMS critical section.  The previous
649 *  level is returned in _isr_cookie.
650 */
651
652#ifndef ASM
653
654RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
655{
656  return ( level & MSR_EE ) != 0;
657}
658
659#if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE)
660
661static inline uint32_t   _CPU_ISR_Get_level( void )
662{
663  uint32_t msr;
664  _CPU_MSR_GET(msr);
665  if (msr & MSR_EE) return 0;
666  else  return 1;
667}
668
669static inline void _CPU_ISR_Set_level( uint32_t   level )
670{
671  uint32_t msr;
672  _CPU_MSR_GET(msr);
673  if (!(level & CPU_MODES_INTERRUPT_MASK)) {
674    msr |= ppc_interrupt_get_disable_mask();
675  }
676  else {
677    msr &= ~ppc_interrupt_get_disable_mask();
678  }
679  _CPU_MSR_SET(msr);
680}
681#else
682/* disable, enable, etc. are in registers.h */
683uint32_t ppc_get_interrupt_level( void );
684void ppc_set_interrupt_level( uint32_t level );
685#define _CPU_ISR_Get_level( _new_level ) ppc_get_interrupt_level()
686#define _CPU_ISR_Set_level( _new_level ) ppc_set_interrupt_level(_new_level)
687#endif
688
689#endif /* ASM */
690
691#define _CPU_Fatal_halt( _source, _error ) \
692  do { \
693    ppc_interrupt_disable(); \
694    __asm__ volatile ( \
695      "mr 3, %0\n" \
696      "mr 4, %1\n" \
697      "1:\n" \
698      "b 1b\n" \
699      : \
700      : "r" (_source), "r" (_error) \
701      : "memory" \
702    ); \
703  } while ( 0 )
704
705/*
706 *  Should be large enough to run all RTEMS tests.  This ensures
707 *  that a "reasonable" small application should not have any problems.
708 */
709
710#define CPU_STACK_MINIMUM_SIZE          (1024*8)
711
712#if defined(__powerpc64__)
713#define CPU_SIZEOF_POINTER 8
714#else
715#define CPU_SIZEOF_POINTER 4
716#endif
717
718/*
719 *  CPU's worst alignment requirement for data types on a byte boundary.  This
720 *  alignment does not take into account the requirements for the stack.
721 */
722
723#define CPU_ALIGNMENT              (PPC_ALIGNMENT)
724
725/*
726 *  This number corresponds to the byte alignment requirement for the
727 *  heap handler.  This alignment requirement may be stricter than that
728 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
729 *  common for the heap to follow the same alignment requirement as
730 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
731 *  then this should be set to CPU_ALIGNMENT.
732 *
733 *  NOTE:  This does not have to be a power of 2.  It does have to
734 *         be greater or equal to than CPU_ALIGNMENT.
735 */
736
737#define CPU_HEAP_ALIGNMENT         (PPC_ALIGNMENT)
738
739/*
740 *  This number corresponds to the byte alignment requirement for memory
741 *  buffers allocated by the partition manager.  This alignment requirement
742 *  may be stricter than that for the data types alignment specified by
743 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
744 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
745 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
746 *
747 *  NOTE:  This does not have to be a power of 2.  It does have to
748 *         be greater or equal to than CPU_ALIGNMENT.
749 */
750
751#define CPU_PARTITION_ALIGNMENT    (PPC_ALIGNMENT)
752
753/*
754 *  This number corresponds to the byte alignment requirement for the
755 *  stack.  This alignment requirement may be stricter than that for the
756 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
757 *  is strict enough for the stack, then this should be set to 0.
758 *
759 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
760 */
761
762#define CPU_STACK_ALIGNMENT        (PPC_STACK_ALIGNMENT)
763
764#ifndef ASM
765/*  The following routine swaps the endian format of an unsigned int.
766 *  It must be static because it is referenced indirectly.
767 *
768 *  This version will work on any processor, but if there is a better
769 *  way for your CPU PLEASE use it.  The most common way to do this is to:
770 *
771 *     swap least significant two bytes with 16-bit rotate
772 *     swap upper and lower 16-bits
773 *     swap most significant two bytes with 16-bit rotate
774 *
775 *  Some CPUs have special instructions which swap a 32-bit quantity in
776 *  a single instruction (e.g. i486).  It is probably best to avoid
777 *  an "endian swapping control bit" in the CPU.  One good reason is
778 *  that interrupts would probably have to be disabled to ensure that
779 *  an interrupt does not try to access the same "chunk" with the wrong
780 *  endian.  Another good reason is that on some CPUs, the endian bit
781 *  endianness for ALL fetches -- both code and data -- so the code
782 *  will be fetched incorrectly.
783 */
784
785static inline uint32_t CPU_swap_u32(
786  uint32_t value
787)
788{
789  uint32_t   swapped;
790
791  __asm__ volatile("rlwimi %0,%1,8,24,31;"
792               "rlwimi %0,%1,24,16,23;"
793               "rlwimi %0,%1,8,8,15;"
794               "rlwimi %0,%1,24,0,7;" :
795               "=&r" ((swapped)) : "r" ((value)));
796
797  return( swapped );
798}
799
800#define CPU_swap_u16( value ) \
801  (((value&0xff) << 8) | ((value >> 8)&0xff))
802
803typedef uint32_t CPU_Counter_ticks;
804
805uint32_t _CPU_Counter_frequency( void );
806
807static inline CPU_Counter_ticks _CPU_Counter_read( void )
808{
809  CPU_Counter_ticks value;
810
811#if defined(__PPC_CPU_E6500__)
812  /* Use Alternate Time Base */
813  __asm__ volatile( "mfspr %0, 526" : "=r" (value) );
814#else
815  __asm__ volatile( "mfspr %0, 268" : "=r" (value) );
816#endif
817
818  return value;
819}
820
821static inline CPU_Counter_ticks _CPU_Counter_difference(
822  CPU_Counter_ticks second,
823  CPU_Counter_ticks first
824)
825{
826  return second - first;
827}
828
829#endif /* ASM */
830
831
832#ifndef ASM
833/* Context handler macros */
834
835/*
836 *  Initialize the context to a state suitable for starting a
837 *  task after a context restore operation.  Generally, this
838 *  involves:
839 *
840 *     - setting a starting address
841 *     - preparing the stack
842 *     - preparing the stack and frame pointers
843 *     - setting the proper interrupt level in the context
844 *     - initializing the floating point context
845 *
846 *  This routine generally does not set any unnecessary register
847 *  in the context.  The state of the "general data" registers is
848 *  undefined at task start time.
849 */
850
851void _CPU_Context_Initialize(
852  Context_Control  *the_context,
853  void             *stack_base,
854  size_t            size,
855  uint32_t          new_level,
856  void             *entry_point,
857  bool              is_fp,
858  void             *tls_area
859);
860
861/*
862 *  This routine is responsible for somehow restarting the currently
863 *  executing task.  If you are lucky, then all that is necessary
864 *  is restoring the context.  Otherwise, there will need to be
865 *  a special assembly routine which does something special in this
866 *  case.  Context_Restore should work most of the time.  It will
867 *  not work if restarting self conflicts with the stack frame
868 *  assumptions of restoring a context.
869 */
870
871#define _CPU_Context_Restart_self( _the_context ) \
872   _CPU_Context_restore( (_the_context) );
873
874/*
875 *  This routine initializes the FP context area passed to it to.
876 *  There are a few standard ways in which to initialize the
877 *  floating point context.  The code included for this macro assumes
878 *  that this is a CPU in which a "initial" FP context was saved into
879 *  _CPU_Null_fp_context and it simply copies it to the destination
880 *  context passed to it.
881 *
882 *  Other models include (1) not doing anything, and (2) putting
883 *  a "null FP status word" in the correct place in the FP context.
884 */
885
886#define _CPU_Context_Initialize_fp( _destination ) \
887  memset( *(_destination), 0, sizeof( **(_destination) ) )
888
889/* end of Context handler macros */
890#endif /* ASM */
891
892#ifndef ASM
893/* Bitfield handler macros */
894
895#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
896
897/*
898 *  This routine sets _output to the bit number of the first bit
899 *  set in _value.  _value is of CPU dependent type Priority_bit_map_Word.
900 *  This type may be either 16 or 32 bits wide although only the 16
901 *  least significant bits will be used.
902 *
903 *  There are a number of variables in using a "find first bit" type
904 *  instruction.
905 *
906 *    (1) What happens when run on a value of zero?
907 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
908 *    (3) The numbering may be zero or one based.
909 *    (4) The "find first bit" instruction may search from MSB or LSB.
910 *
911 *  RTEMS guarantees that (1) will never happen so it is not a concern.
912 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
913 *  _CPU_Priority_Bits_index().  These three form a set of routines
914 *  which must logically operate together.  Bits in the _value are
915 *  set and cleared based on masks built by _CPU_Priority_mask().
916 *  The basic major and minor values calculated by _Priority_Major()
917 *  and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index()
918 *  to properly range between the values returned by the "find first bit"
919 *  instruction.  This makes it possible for _Priority_Get_highest() to
920 *  calculate the major and directly index into the minor table.
921 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
922 *  is the first bit found.
923 *
924 *  This entire "find first bit" and mapping process depends heavily
925 *  on the manner in which a priority is broken into a major and minor
926 *  components with the major being the 4 MSB of a priority and minor
927 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
928 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
929 *  to the lowest priority.
930 *
931 *  If your CPU does not have a "find first bit" instruction, then
932 *  there are ways to make do without it.  Here are a handful of ways
933 *  to implement this in software:
934 *
935 *    - a series of 16 bit test instructions
936 *    - a "binary search using if's"
937 *    - _number = 0
938 *      if _value > 0x00ff
939 *        _value >>=8
940 *        _number = 8;
941 *
942 *      if _value > 0x0000f
943 *        _value >=8
944 *        _number += 4
945 *
946 *      _number += bit_set_table[ _value ]
947 *
948 *    where bit_set_table[ 16 ] has values which indicate the first
949 *      bit set
950 */
951
952#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
953  { \
954    __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \
955                  "1" ((_value))); \
956    (_output) = (_output) - 16; \
957  }
958
959/* end of Bitfield handler macros */
960
961/*
962 *  This routine builds the mask which corresponds to the bit fields
963 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
964 *  for that routine.
965 */
966
967#define _CPU_Priority_Mask( _bit_number ) \
968  ( 0x8000u >> (_bit_number) )
969
970/*
971 *  This routine translates the bit numbers returned by
972 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
973 *  a major or minor component of a priority.  See the discussion
974 *  for that routine.
975 */
976
977#define _CPU_Priority_bits_index( _priority ) \
978  (_priority)
979
980/* end of Priority handler macros */
981#endif /* ASM */
982
983/* functions */
984
985#ifndef ASM
986
987/*
988 *  _CPU_Initialize
989 *
990 *  This routine performs CPU dependent initialization.
991 */
992
993void _CPU_Initialize(void);
994
995/*
996 *  _CPU_ISR_install_vector
997 *
998 *  This routine installs an interrupt vector.
999 */
1000
1001void _CPU_ISR_install_vector(
1002  uint32_t    vector,
1003  proc_ptr    new_handler,
1004  proc_ptr   *old_handler
1005);
1006
1007/*
1008 *  _CPU_Context_switch
1009 *
1010 *  This routine switches from the run context to the heir context.
1011 */
1012
1013void _CPU_Context_switch(
1014  Context_Control  *run,
1015  Context_Control  *heir
1016);
1017
1018/*
1019 *  _CPU_Context_restore
1020 *
1021 *  This routine is generallu used only to restart self in an
1022 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1023 *
1024 *  NOTE: May be unnecessary to reload some registers.
1025 */
1026
1027void _CPU_Context_restore(
1028  Context_Control *new_context
1029) RTEMS_NO_RETURN;
1030
1031/*
1032 *  _CPU_Context_save_fp
1033 *
1034 *  This routine saves the floating point context passed to it.
1035 */
1036
1037void _CPU_Context_save_fp(
1038  Context_Control_fp **fp_context_ptr
1039);
1040
1041/*
1042 *  _CPU_Context_restore_fp
1043 *
1044 *  This routine restores the floating point context passed to it.
1045 */
1046
1047void _CPU_Context_restore_fp(
1048  Context_Control_fp **fp_context_ptr
1049);
1050
1051void _CPU_Context_volatile_clobber( uintptr_t pattern );
1052
1053void _CPU_Context_validate( uintptr_t pattern );
1054
1055#ifdef RTEMS_SMP
1056  uint32_t _CPU_SMP_Initialize( void );
1057
1058  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1059
1060  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1061
1062  void _CPU_SMP_Prepare_start_multitasking( void );
1063
1064  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1065  {
1066    uint32_t pir;
1067
1068    /* Use Book E Processor ID Register (PIR) */
1069    __asm__ volatile (
1070      "mfspr %[pir], 286"
1071      : [pir] "=&r" (pir)
1072    );
1073
1074    return pir;
1075  }
1076
1077  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1078
1079  static inline void _CPU_SMP_Processor_event_broadcast( void )
1080  {
1081    __asm__ volatile ( "" : : : "memory" );
1082  }
1083
1084  static inline void _CPU_SMP_Processor_event_receive( void )
1085  {
1086    __asm__ volatile ( "" : : : "memory" );
1087  }
1088#endif
1089
1090typedef struct {
1091  uintptr_t EXC_SRR0;
1092  uintptr_t EXC_SRR1;
1093  uint32_t _EXC_number;
1094  uint32_t RESERVED_FOR_ALIGNMENT_0;
1095  uint32_t EXC_CR;
1096  uint32_t EXC_XER;
1097  uintptr_t EXC_CTR;
1098  uintptr_t EXC_LR;
1099  uintptr_t RESERVED_FOR_ALIGNMENT_1;
1100  #ifdef __SPE__
1101    uint32_t EXC_SPEFSCR;
1102    uint64_t EXC_ACC;
1103  #endif
1104  PPC_GPR_TYPE GPR0;
1105  PPC_GPR_TYPE GPR1;
1106  PPC_GPR_TYPE GPR2;
1107  PPC_GPR_TYPE GPR3;
1108  PPC_GPR_TYPE GPR4;
1109  PPC_GPR_TYPE GPR5;
1110  PPC_GPR_TYPE GPR6;
1111  PPC_GPR_TYPE GPR7;
1112  PPC_GPR_TYPE GPR8;
1113  PPC_GPR_TYPE GPR9;
1114  PPC_GPR_TYPE GPR10;
1115  PPC_GPR_TYPE GPR11;
1116  PPC_GPR_TYPE GPR12;
1117  PPC_GPR_TYPE GPR13;
1118  PPC_GPR_TYPE GPR14;
1119  PPC_GPR_TYPE GPR15;
1120  PPC_GPR_TYPE GPR16;
1121  PPC_GPR_TYPE GPR17;
1122  PPC_GPR_TYPE GPR18;
1123  PPC_GPR_TYPE GPR19;
1124  PPC_GPR_TYPE GPR20;
1125  PPC_GPR_TYPE GPR21;
1126  PPC_GPR_TYPE GPR22;
1127  PPC_GPR_TYPE GPR23;
1128  PPC_GPR_TYPE GPR24;
1129  PPC_GPR_TYPE GPR25;
1130  PPC_GPR_TYPE GPR26;
1131  PPC_GPR_TYPE GPR27;
1132  PPC_GPR_TYPE GPR28;
1133  PPC_GPR_TYPE GPR29;
1134  PPC_GPR_TYPE GPR30;
1135  PPC_GPR_TYPE GPR31;
1136  uintptr_t RESERVED_FOR_ALIGNMENT_2;
1137  #ifdef PPC_MULTILIB_ALTIVEC
1138    uint32_t VRSAVE;
1139    uint32_t RESERVED_FOR_ALIGNMENT_3[3];
1140
1141    /* This field must take stvewx/lvewx requirements into account */
1142    uint32_t RESERVED_FOR_ALIGNMENT_4[3];
1143    uint32_t VSCR;
1144
1145    uint8_t V0[16];
1146    uint8_t V1[16];
1147    uint8_t V2[16];
1148    uint8_t V3[16];
1149    uint8_t V4[16];
1150    uint8_t V5[16];
1151    uint8_t V6[16];
1152    uint8_t V7[16];
1153    uint8_t V8[16];
1154    uint8_t V9[16];
1155    uint8_t V10[16];
1156    uint8_t V11[16];
1157    uint8_t V12[16];
1158    uint8_t V13[16];
1159    uint8_t V14[16];
1160    uint8_t V15[16];
1161    uint8_t V16[16];
1162    uint8_t V17[16];
1163    uint8_t V18[16];
1164    uint8_t V19[16];
1165    uint8_t V20[16];
1166    uint8_t V21[16];
1167    uint8_t V22[16];
1168    uint8_t V23[16];
1169    uint8_t V24[16];
1170    uint8_t V25[16];
1171    uint8_t V26[16];
1172    uint8_t V27[16];
1173    uint8_t V28[16];
1174    uint8_t V29[16];
1175    uint8_t V30[16];
1176    uint8_t V31[16];
1177  #endif
1178  #ifdef PPC_MULTILIB_FPU
1179    double F0;
1180    double F1;
1181    double F2;
1182    double F3;
1183    double F4;
1184    double F5;
1185    double F6;
1186    double F7;
1187    double F8;
1188    double F9;
1189    double F10;
1190    double F11;
1191    double F12;
1192    double F13;
1193    double F14;
1194    double F15;
1195    double F16;
1196    double F17;
1197    double F18;
1198    double F19;
1199    double F20;
1200    double F21;
1201    double F22;
1202    double F23;
1203    double F24;
1204    double F25;
1205    double F26;
1206    double F27;
1207    double F28;
1208    double F29;
1209    double F30;
1210    double F31;
1211    uint64_t FPSCR;
1212    uint64_t RESERVED_FOR_ALIGNMENT_5;
1213  #endif
1214} CPU_Exception_frame;
1215
1216void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1217
1218/*
1219 * _CPU_Initialize_altivec()
1220 *
1221 * Global altivec-related initialization.
1222 */
1223void
1224_CPU_Initialize_altivec(void);
1225
1226/*
1227 * _CPU_Context_switch_altivec
1228 *
1229 * This routine switches the altivec contexts passed to it.
1230 */
1231
1232void
1233_CPU_Context_switch_altivec(
1234  ppc_context *from,
1235  ppc_context *to
1236);
1237
1238/*
1239 * _CPU_Context_restore_altivec
1240 *
1241 * This routine restores the altivec context passed to it.
1242 */
1243
1244void
1245_CPU_Context_restore_altivec(
1246  ppc_context *ctxt
1247);
1248
1249/*
1250 * _CPU_Context_initialize_altivec
1251 *
1252 * This routine initializes the altivec context passed to it.
1253 */
1254
1255void
1256_CPU_Context_initialize_altivec(
1257  ppc_context *ctxt
1258);
1259
1260void _CPU_Fatal_error(
1261  uint32_t   _error
1262);
1263
1264/** Type that can store a 32-bit integer or a pointer. */
1265typedef uintptr_t CPU_Uint32ptr;
1266
1267#endif /* ASM */
1268
1269#ifdef __cplusplus
1270}
1271#endif
1272
1273#endif /* _RTEMS_SCORE_CPU_H */
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