[d5607c5a] | 1 | /** |
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[d9e0006] | 2 | * @file |
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| 3 | * |
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| 4 | * @brief PowerPC CPU Department Source |
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[d5607c5a] | 5 | */ |
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| 6 | |
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[4a0d87e] | 7 | /* |
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[826fa6b1] | 8 | * COPYRIGHT (c) 1989-2012. |
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[43b4c7a] | 9 | * On-Line Applications Research Corporation (OAR). |
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| 10 | * |
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[af16a7d2] | 11 | * COPYRIGHT (c) 1995 i-cubed ltd. |
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| 12 | * |
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| 13 | * To anyone who acknowledges that this file is provided "AS IS" |
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| 14 | * without any express or implied warranty: |
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| 15 | * permission to use, copy, modify, and distribute this file |
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| 16 | * for any purpose is hereby granted without fee, provided that |
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| 17 | * the above copyright notice and this notice appears in all |
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| 18 | * copies, and that the name of i-cubed limited not be used in |
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| 19 | * advertising or publicity pertaining to distribution of the |
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| 20 | * software without specific, written prior permission. |
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| 21 | * i-cubed limited makes no representations about the suitability |
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| 22 | * of this software for any purpose. |
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| 23 | * |
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| 24 | * Copyright (c) 2001 Andy Dachs <a.dachs@sstl.co.uk>. |
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| 25 | * |
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| 26 | * Copyright (c) 2001 Surrey Satellite Technology Limited (SSTL). |
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| 27 | * |
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[a6f84b27] | 28 | * Copyright (c) 2010, 2017 embedded brains GmbH. |
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[af16a7d2] | 29 | * |
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[43b4c7a] | 30 | * The license and distribution terms for this file may be |
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| 31 | * found in the file LICENSE in this distribution or at |
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[c499856] | 32 | * http://www.rtems.org/license/LICENSE. |
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[4a0d87e] | 33 | */ |
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[5bb38e15] | 34 | |
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[7f70d1b7] | 35 | #ifndef _RTEMS_SCORE_CPU_H |
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| 36 | #define _RTEMS_SCORE_CPU_H |
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[4a0d87e] | 37 | |
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[d978d1b] | 38 | #include <rtems/score/basedefs.h> |
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[0a7a30d] | 39 | #if defined(RTEMS_PARAVIRT) |
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| 40 | #include <rtems/score/paravirt.h> |
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| 41 | #endif |
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[af16a7d2] | 42 | #include <rtems/score/powerpc.h> |
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| 43 | #include <rtems/powerpc/registers.h> |
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[2067679] | 44 | |
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[4a0d87e] | 45 | #ifndef ASM |
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[2067679] | 46 | #include <string.h> /* for memset() */ |
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[af16a7d2] | 47 | #endif |
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| 48 | |
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| 49 | #ifdef __cplusplus |
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| 50 | extern "C" { |
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[4a0d87e] | 51 | #endif |
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| 52 | |
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[8ecc042a] | 53 | /* conditional compilation parameters */ |
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| 54 | |
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[10c66191] | 55 | /* |
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| 56 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 57 | * |
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| 58 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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| 59 | * must be provided and is the default IDLE thread body instead of |
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| 60 | * _CPU_Thread_Idle_body. |
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| 61 | * |
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| 62 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 63 | * not provide one. |
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| 64 | * |
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| 65 | * This is intended to allow for supporting processors which have |
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| 66 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 67 | * the CPU can be powered down. |
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| 68 | * |
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| 69 | * The order of precedence for selecting the IDLE thread body is: |
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| 70 | * |
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| 71 | * 1. BSP provided |
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| 72 | * 2. CPU dependent (if provided) |
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| 73 | * 3. generic (if no BSP and no CPU dependent) |
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| 74 | */ |
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| 75 | |
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| 76 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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| 77 | |
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| 78 | /* |
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| 79 | * Does the stack grow up (toward higher addresses) or down |
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| 80 | * (toward lower addresses)? |
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| 81 | * |
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| 82 | * If TRUE, then the grows upward. |
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| 83 | * If FALSE, then the grows toward smaller addresses. |
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| 84 | */ |
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| 85 | |
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| 86 | #define CPU_STACK_GROWS_UP FALSE |
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| 87 | |
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[a8865f8] | 88 | #define CPU_CACHE_LINE_BYTES PPC_STRUCTURE_ALIGNMENT |
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[10c66191] | 89 | |
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[a8865f8] | 90 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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[10c66191] | 91 | |
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[56c5e091] | 92 | /* |
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| 93 | * Does the CPU have hardware floating point? |
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| 94 | * |
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| 95 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 96 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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| 97 | * |
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| 98 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 99 | * the answer is TRUE. |
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| 100 | * |
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| 101 | * The macro name "PPC_HAS_FPU" should be made CPU specific. |
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| 102 | * It indicates whether or not this CPU model has FP support. For |
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| 103 | * example, it would be possible to have an i386_nofp CPU model |
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| 104 | * which set this to false to indicate that you have an i386 without |
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| 105 | * an i387 and wish to leave floating point support out of RTEMS. |
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| 106 | */ |
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| 107 | |
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| 108 | #if ( PPC_HAS_FPU == 1 ) |
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| 109 | #define CPU_HARDWARE_FP TRUE |
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| 110 | #define CPU_SOFTWARE_FP FALSE |
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| 111 | #else |
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| 112 | #define CPU_HARDWARE_FP FALSE |
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| 113 | #define CPU_SOFTWARE_FP FALSE |
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| 114 | #endif |
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| 115 | |
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| 116 | /* |
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| 117 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 118 | * |
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| 119 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 120 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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| 121 | * |
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| 122 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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[a19034d] | 123 | * |
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| 124 | * PowerPC Note: It appears the GCC can implicitly generate FPU |
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| 125 | * and Altivec instructions when you least expect them. So make |
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| 126 | * all tasks floating point. |
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[56c5e091] | 127 | */ |
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| 128 | |
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[a19034d] | 129 | #define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP |
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[56c5e091] | 130 | |
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| 131 | /* |
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| 132 | * Should the IDLE task have a floating point context? |
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| 133 | * |
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| 134 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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| 135 | * and it has a floating point context which is switched in and out. |
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| 136 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 137 | * |
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| 138 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 139 | * the IDLE task from an interrupt because the floating point context |
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| 140 | * must be saved as part of the preemption. |
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| 141 | */ |
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| 142 | |
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| 143 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 144 | |
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[decff899] | 145 | #define CPU_MAXIMUM_PROCESSORS 32 |
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| 146 | |
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[b7c7b75b] | 147 | /* |
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| 148 | * Processor defined structures required for cpukit/score. |
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| 149 | */ |
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| 150 | |
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| 151 | /* |
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| 152 | * Contexts |
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| 153 | * |
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| 154 | * Generally there are 2 types of context to save. |
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| 155 | * 1. Interrupt registers to save |
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| 156 | * 2. Task level registers to save |
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| 157 | * |
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| 158 | * This means we have the following 3 context items: |
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| 159 | * 1. task level context stuff:: Context_Control |
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| 160 | * 2. floating point task stuff:: Context_Control_fp |
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| 161 | * 3. special interrupt level context :: Context_Control_interrupt |
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| 162 | * |
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| 163 | * On some processors, it is cost-effective to save only the callee |
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| 164 | * preserved registers during a task context switch. This means |
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| 165 | * that the ISR code needs to save those registers which do not |
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| 166 | * persist across function calls. It is not mandatory to make this |
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| 167 | * distinctions between the caller/callee saves registers for the |
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| 168 | * purpose of minimizing context saved during task switch and on interrupts. |
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| 169 | * If the cost of saving extra registers is minimal, simplicity is the |
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| 170 | * choice. Save the same context on interrupt entry as for tasks in |
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| 171 | * this case. |
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| 172 | * |
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| 173 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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| 174 | * care should be used in designing the context area. |
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| 175 | * |
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| 176 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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| 177 | * structure will not be used or it simply consist of an array of a |
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| 178 | * fixed number of bytes. This is done when the floating point context |
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| 179 | * is dumped by a "FP save context" type instruction and the format |
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| 180 | * is not really defined by the CPU. In this case, there is no need |
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| 181 | * to figure out the exact format -- only the size. Of course, although |
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| 182 | * this is enough information for RTEMS, it is probably not enough for |
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| 183 | * a debugger such as gdb. But that is another problem. |
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| 184 | */ |
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| 185 | |
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[c3ba11ac] | 186 | #ifndef __SPE__ |
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[a6f84b27] | 187 | #define PPC_GPR_TYPE uintptr_t |
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| 188 | #if defined(__powerpc64__) |
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| 189 | #define PPC_GPR_SIZE 8 |
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| 190 | #define PPC_GPR_LOAD ld |
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| 191 | #define PPC_GPR_STORE std |
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| 192 | #else |
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| 193 | #define PPC_GPR_SIZE 4 |
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| 194 | #define PPC_GPR_LOAD lwz |
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| 195 | #define PPC_GPR_STORE stw |
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| 196 | #endif |
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[1869bb7] | 197 | #else |
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| 198 | #define PPC_GPR_TYPE uint64_t |
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| 199 | #define PPC_GPR_SIZE 8 |
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| 200 | #define PPC_GPR_LOAD evldd |
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| 201 | #define PPC_GPR_STORE evstdd |
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| 202 | #endif |
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[c3ba11ac] | 203 | |
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[a6f84b27] | 204 | #if defined(__powerpc64__) |
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| 205 | #define PPC_REG_SIZE 8 |
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| 206 | #define PPC_REG_LOAD ld |
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| 207 | #define PPC_REG_STORE std |
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| 208 | #define PPC_REG_STORE_UPDATE stdu |
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| 209 | #define PPC_REG_CMP cmpd |
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| 210 | #else |
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| 211 | #define PPC_REG_SIZE 4 |
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| 212 | #define PPC_REG_LOAD lwz |
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| 213 | #define PPC_REG_STORE stw |
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| 214 | #define PPC_REG_STORE_UPDATE stwu |
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| 215 | #define PPC_REG_CMP cmpw |
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| 216 | #endif |
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| 217 | |
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[1869bb7] | 218 | #ifndef ASM |
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[5be93c2] | 219 | |
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[39a4574] | 220 | /* |
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| 221 | * Non-volatile context according to E500ABIUG, EABI and 32-bit TLS (according |
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| 222 | * to "Power Architecture 32-bit Application Binary Interface Supplement 1.0 - |
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| 223 | * Linux and Embedded") |
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| 224 | */ |
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[1869bb7] | 225 | typedef struct { |
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| 226 | uint32_t msr; |
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| 227 | uint32_t cr; |
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[a6f84b27] | 228 | uintptr_t gpr1; |
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| 229 | uintptr_t lr; |
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[1869bb7] | 230 | PPC_GPR_TYPE gpr14; |
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| 231 | PPC_GPR_TYPE gpr15; |
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| 232 | PPC_GPR_TYPE gpr16; |
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| 233 | PPC_GPR_TYPE gpr17; |
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| 234 | PPC_GPR_TYPE gpr18; |
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| 235 | PPC_GPR_TYPE gpr19; |
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| 236 | PPC_GPR_TYPE gpr20; |
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| 237 | PPC_GPR_TYPE gpr21; |
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| 238 | PPC_GPR_TYPE gpr22; |
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| 239 | PPC_GPR_TYPE gpr23; |
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| 240 | PPC_GPR_TYPE gpr24; |
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| 241 | PPC_GPR_TYPE gpr25; |
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| 242 | PPC_GPR_TYPE gpr26; |
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| 243 | PPC_GPR_TYPE gpr27; |
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| 244 | PPC_GPR_TYPE gpr28; |
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| 245 | PPC_GPR_TYPE gpr29; |
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| 246 | PPC_GPR_TYPE gpr30; |
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| 247 | PPC_GPR_TYPE gpr31; |
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[7ce60b3] | 248 | uint32_t isr_dispatch_disable; |
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[ae3e6af8] | 249 | uint32_t reserved_for_alignment; |
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[3e2647a7] | 250 | #if defined(PPC_MULTILIB_ALTIVEC) |
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| 251 | uint8_t v20[16]; |
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| 252 | uint8_t v21[16]; |
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| 253 | uint8_t v22[16]; |
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| 254 | uint8_t v23[16]; |
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| 255 | uint8_t v24[16]; |
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| 256 | uint8_t v25[16]; |
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| 257 | uint8_t v26[16]; |
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| 258 | uint8_t v27[16]; |
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| 259 | uint8_t v28[16]; |
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| 260 | uint8_t v29[16]; |
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| 261 | uint8_t v30[16]; |
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| 262 | uint8_t v31[16]; |
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| 263 | uint32_t vrsave; |
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| 264 | #elif defined(__ALTIVEC__) |
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[1869bb7] | 265 | /* |
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| 266 | * 12 non-volatile vector registers, cache-aligned area for vscr/vrsave |
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| 267 | * and padding to ensure cache-alignment. Unfortunately, we can't verify |
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| 268 | * the cache line size here in the cpukit but altivec support code will |
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| 269 | * produce an error if this is ever different from 32 bytes. |
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| 270 | * |
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| 271 | * Note: it is the BSP/CPU-support's responsibility to save/restore |
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| 272 | * volatile vregs across interrupts and exceptions. |
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| 273 | */ |
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| 274 | uint8_t altivec[16*12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE]; |
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| 275 | #endif |
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[3e2647a7] | 276 | #if defined(PPC_MULTILIB_FPU) |
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| 277 | double f14; |
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| 278 | double f15; |
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| 279 | double f16; |
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| 280 | double f17; |
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| 281 | double f18; |
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| 282 | double f19; |
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| 283 | double f20; |
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| 284 | double f21; |
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| 285 | double f22; |
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| 286 | double f23; |
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| 287 | double f24; |
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| 288 | double f25; |
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| 289 | double f26; |
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| 290 | double f27; |
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| 291 | double f28; |
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| 292 | double f29; |
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| 293 | double f30; |
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| 294 | double f31; |
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| 295 | #endif |
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[ae3e6af8] | 296 | /* |
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| 297 | * The following items are at the structure end, so that we can use dcbz for |
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| 298 | * the previous items to optimize the context switch. We must not set the |
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| 299 | * following items to zero via the dcbz. |
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| 300 | */ |
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[a6f84b27] | 301 | uintptr_t tp; |
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[3e2647a7] | 302 | #if defined(RTEMS_SMP) |
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| 303 | volatile uint32_t is_executing; |
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| 304 | #endif |
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[1869bb7] | 305 | } ppc_context; |
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[c3ba11ac] | 306 | |
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[1869bb7] | 307 | typedef struct { |
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| 308 | uint8_t context [ |
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| 309 | PPC_DEFAULT_CACHE_LINE_SIZE |
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| 310 | + sizeof(ppc_context) |
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| 311 | + (sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE == 0 |
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| 312 | ? 0 |
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| 313 | : PPC_DEFAULT_CACHE_LINE_SIZE |
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| 314 | - sizeof(ppc_context) % PPC_DEFAULT_CACHE_LINE_SIZE) |
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| 315 | ]; |
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| 316 | } Context_Control; |
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[5be93c2] | 317 | |
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[38b59a6] | 318 | static inline ppc_context *ppc_get_context( const Context_Control *context ) |
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[1869bb7] | 319 | { |
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| 320 | uintptr_t clsz = PPC_DEFAULT_CACHE_LINE_SIZE; |
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| 321 | uintptr_t mask = clsz - 1; |
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| 322 | uintptr_t addr = (uintptr_t) context; |
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[5be93c2] | 323 | |
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[1869bb7] | 324 | return (ppc_context *) ((addr & ~mask) + clsz); |
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| 325 | } |
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[5be93c2] | 326 | |
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[1869bb7] | 327 | #define _CPU_Context_Get_SP( _context ) \ |
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| 328 | ppc_get_context(_context)->gpr1 |
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[38b59a6] | 329 | |
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| 330 | #ifdef RTEMS_SMP |
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[11b05f1] | 331 | static inline bool _CPU_Context_Get_is_executing( |
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| 332 | const Context_Control *context |
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| 333 | ) |
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| 334 | { |
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| 335 | return ppc_get_context(context)->is_executing; |
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| 336 | } |
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| 337 | |
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| 338 | static inline void _CPU_Context_Set_is_executing( |
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| 339 | Context_Control *context, |
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| 340 | bool is_executing |
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| 341 | ) |
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| 342 | { |
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| 343 | ppc_get_context(context)->is_executing = is_executing; |
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| 344 | } |
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[38b59a6] | 345 | #endif |
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[1869bb7] | 346 | #endif /* ASM */ |
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[c3ba11ac] | 347 | |
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[a6f84b27] | 348 | #define PPC_CONTEXT_OFFSET_MSR (PPC_DEFAULT_CACHE_LINE_SIZE) |
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| 349 | #define PPC_CONTEXT_OFFSET_CR (PPC_DEFAULT_CACHE_LINE_SIZE + 4) |
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| 350 | #define PPC_CONTEXT_OFFSET_GPR1 (PPC_DEFAULT_CACHE_LINE_SIZE + 8) |
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| 351 | #define PPC_CONTEXT_OFFSET_LR (PPC_DEFAULT_CACHE_LINE_SIZE + PPC_REG_SIZE + 8) |
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[1869bb7] | 352 | |
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| 353 | #define PPC_CONTEXT_GPR_OFFSET( gpr ) \ |
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[a6f84b27] | 354 | (((gpr) - 14) * PPC_GPR_SIZE + \ |
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| 355 | PPC_DEFAULT_CACHE_LINE_SIZE + 8 + 2 * PPC_REG_SIZE) |
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[1869bb7] | 356 | |
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| 357 | #define PPC_CONTEXT_OFFSET_GPR14 PPC_CONTEXT_GPR_OFFSET( 14 ) |
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| 358 | #define PPC_CONTEXT_OFFSET_GPR15 PPC_CONTEXT_GPR_OFFSET( 15 ) |
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| 359 | #define PPC_CONTEXT_OFFSET_GPR16 PPC_CONTEXT_GPR_OFFSET( 16 ) |
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| 360 | #define PPC_CONTEXT_OFFSET_GPR17 PPC_CONTEXT_GPR_OFFSET( 17 ) |
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| 361 | #define PPC_CONTEXT_OFFSET_GPR18 PPC_CONTEXT_GPR_OFFSET( 18 ) |
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| 362 | #define PPC_CONTEXT_OFFSET_GPR19 PPC_CONTEXT_GPR_OFFSET( 19 ) |
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| 363 | #define PPC_CONTEXT_OFFSET_GPR20 PPC_CONTEXT_GPR_OFFSET( 20 ) |
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| 364 | #define PPC_CONTEXT_OFFSET_GPR21 PPC_CONTEXT_GPR_OFFSET( 21 ) |
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| 365 | #define PPC_CONTEXT_OFFSET_GPR22 PPC_CONTEXT_GPR_OFFSET( 22 ) |
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| 366 | #define PPC_CONTEXT_OFFSET_GPR23 PPC_CONTEXT_GPR_OFFSET( 23 ) |
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| 367 | #define PPC_CONTEXT_OFFSET_GPR24 PPC_CONTEXT_GPR_OFFSET( 24 ) |
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| 368 | #define PPC_CONTEXT_OFFSET_GPR25 PPC_CONTEXT_GPR_OFFSET( 25 ) |
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| 369 | #define PPC_CONTEXT_OFFSET_GPR26 PPC_CONTEXT_GPR_OFFSET( 26 ) |
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| 370 | #define PPC_CONTEXT_OFFSET_GPR27 PPC_CONTEXT_GPR_OFFSET( 27 ) |
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| 371 | #define PPC_CONTEXT_OFFSET_GPR28 PPC_CONTEXT_GPR_OFFSET( 28 ) |
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| 372 | #define PPC_CONTEXT_OFFSET_GPR29 PPC_CONTEXT_GPR_OFFSET( 29 ) |
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| 373 | #define PPC_CONTEXT_OFFSET_GPR30 PPC_CONTEXT_GPR_OFFSET( 30 ) |
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| 374 | #define PPC_CONTEXT_OFFSET_GPR31 PPC_CONTEXT_GPR_OFFSET( 31 ) |
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[ae3e6af8] | 375 | #define PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE PPC_CONTEXT_GPR_OFFSET( 32 ) |
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[b7c7b75b] | 376 | |
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[3e2647a7] | 377 | #ifdef PPC_MULTILIB_ALTIVEC |
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| 378 | #define PPC_CONTEXT_OFFSET_V( v ) \ |
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[a6f84b27] | 379 | ( ( ( v ) - 20 ) * 16 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8) |
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[3e2647a7] | 380 | #define PPC_CONTEXT_OFFSET_V20 PPC_CONTEXT_OFFSET_V( 20 ) |
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| 381 | #define PPC_CONTEXT_OFFSET_V21 PPC_CONTEXT_OFFSET_V( 21 ) |
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| 382 | #define PPC_CONTEXT_OFFSET_V22 PPC_CONTEXT_OFFSET_V( 22 ) |
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| 383 | #define PPC_CONTEXT_OFFSET_V23 PPC_CONTEXT_OFFSET_V( 23 ) |
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| 384 | #define PPC_CONTEXT_OFFSET_V24 PPC_CONTEXT_OFFSET_V( 24 ) |
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| 385 | #define PPC_CONTEXT_OFFSET_V25 PPC_CONTEXT_OFFSET_V( 25 ) |
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| 386 | #define PPC_CONTEXT_OFFSET_V26 PPC_CONTEXT_OFFSET_V( 26 ) |
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| 387 | #define PPC_CONTEXT_OFFSET_V27 PPC_CONTEXT_OFFSET_V( 27 ) |
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| 388 | #define PPC_CONTEXT_OFFSET_V28 PPC_CONTEXT_OFFSET_V( 28 ) |
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| 389 | #define PPC_CONTEXT_OFFSET_V29 PPC_CONTEXT_OFFSET_V( 29 ) |
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| 390 | #define PPC_CONTEXT_OFFSET_V30 PPC_CONTEXT_OFFSET_V( 30 ) |
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| 391 | #define PPC_CONTEXT_OFFSET_V31 PPC_CONTEXT_OFFSET_V( 31 ) |
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| 392 | #define PPC_CONTEXT_OFFSET_VRSAVE PPC_CONTEXT_OFFSET_V( 32 ) |
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| 393 | #define PPC_CONTEXT_OFFSET_F( f ) \ |
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[a6f84b27] | 394 | ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_VRSAVE + 8 ) |
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[3e2647a7] | 395 | #else |
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| 396 | #define PPC_CONTEXT_OFFSET_F( f ) \ |
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[a6f84b27] | 397 | ( ( ( f ) - 14 ) * 8 + PPC_CONTEXT_OFFSET_ISR_DISPATCH_DISABLE + 8 ) |
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[3e2647a7] | 398 | #endif |
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| 399 | |
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| 400 | #ifdef PPC_MULTILIB_FPU |
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| 401 | #define PPC_CONTEXT_OFFSET_F14 PPC_CONTEXT_OFFSET_F( 14 ) |
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| 402 | #define PPC_CONTEXT_OFFSET_F15 PPC_CONTEXT_OFFSET_F( 15 ) |
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| 403 | #define PPC_CONTEXT_OFFSET_F16 PPC_CONTEXT_OFFSET_F( 16 ) |
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| 404 | #define PPC_CONTEXT_OFFSET_F17 PPC_CONTEXT_OFFSET_F( 17 ) |
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| 405 | #define PPC_CONTEXT_OFFSET_F18 PPC_CONTEXT_OFFSET_F( 18 ) |
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| 406 | #define PPC_CONTEXT_OFFSET_F19 PPC_CONTEXT_OFFSET_F( 19 ) |
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| 407 | #define PPC_CONTEXT_OFFSET_F20 PPC_CONTEXT_OFFSET_F( 20 ) |
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| 408 | #define PPC_CONTEXT_OFFSET_F21 PPC_CONTEXT_OFFSET_F( 21 ) |
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| 409 | #define PPC_CONTEXT_OFFSET_F22 PPC_CONTEXT_OFFSET_F( 22 ) |
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| 410 | #define PPC_CONTEXT_OFFSET_F23 PPC_CONTEXT_OFFSET_F( 23 ) |
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| 411 | #define PPC_CONTEXT_OFFSET_F24 PPC_CONTEXT_OFFSET_F( 24 ) |
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| 412 | #define PPC_CONTEXT_OFFSET_F25 PPC_CONTEXT_OFFSET_F( 25 ) |
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| 413 | #define PPC_CONTEXT_OFFSET_F26 PPC_CONTEXT_OFFSET_F( 26 ) |
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| 414 | #define PPC_CONTEXT_OFFSET_F27 PPC_CONTEXT_OFFSET_F( 27 ) |
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| 415 | #define PPC_CONTEXT_OFFSET_F28 PPC_CONTEXT_OFFSET_F( 28 ) |
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| 416 | #define PPC_CONTEXT_OFFSET_F29 PPC_CONTEXT_OFFSET_F( 29 ) |
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| 417 | #define PPC_CONTEXT_OFFSET_F30 PPC_CONTEXT_OFFSET_F( 30 ) |
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| 418 | #define PPC_CONTEXT_OFFSET_F31 PPC_CONTEXT_OFFSET_F( 31 ) |
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| 419 | #endif |
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| 420 | |
---|
| 421 | #if defined(PPC_MULTILIB_FPU) |
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| 422 | #define PPC_CONTEXT_VOLATILE_SIZE PPC_CONTEXT_OFFSET_F( 32 ) |
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| 423 | #elif defined(PPC_MULTILIB_ALTIVEC) |
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| 424 | #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_OFFSET_VRSAVE + 4) |
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[d30c2cc] | 425 | #elif defined(__ALTIVEC__) |
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| 426 | #define PPC_CONTEXT_VOLATILE_SIZE \ |
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| 427 | (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8 \ |
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| 428 | + 16 * 12 + 32 + PPC_DEFAULT_CACHE_LINE_SIZE) |
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[3e2647a7] | 429 | #else |
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[f61195b2] | 430 | #define PPC_CONTEXT_VOLATILE_SIZE (PPC_CONTEXT_GPR_OFFSET( 32 ) + 8) |
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[3e2647a7] | 431 | #endif |
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| 432 | |
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[a6f84b27] | 433 | #define PPC_CONTEXT_OFFSET_TP PPC_CONTEXT_VOLATILE_SIZE |
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[ae3e6af8] | 434 | |
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[38b59a6] | 435 | #ifdef RTEMS_SMP |
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[a6f84b27] | 436 | #define PPC_CONTEXT_OFFSET_IS_EXECUTING \ |
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| 437 | (PPC_CONTEXT_OFFSET_TP + PPC_REG_SIZE) |
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[38b59a6] | 438 | #endif |
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| 439 | |
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[c3ba11ac] | 440 | #ifndef ASM |
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[b7c7b75b] | 441 | typedef struct { |
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[2e19bfd] | 442 | #if (PPC_HAS_FPU == 1) |
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[b7c7b75b] | 443 | /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over |
---|
| 444 | * procedure calls. However, this would mean that the interrupt |
---|
| 445 | * frame had to hold f0-f13, and the fpscr. And as the majority |
---|
| 446 | * of tasks will not have an FP context, we will save the whole |
---|
| 447 | * context here. |
---|
| 448 | */ |
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| 449 | #if (PPC_HAS_DOUBLE == 1) |
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| 450 | double f[32]; |
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[2067679] | 451 | uint64_t fpscr; |
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[b7c7b75b] | 452 | #else |
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| 453 | float f[32]; |
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[2067679] | 454 | uint32_t fpscr; |
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[b7c7b75b] | 455 | #endif |
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[2e19bfd] | 456 | #endif /* (PPC_HAS_FPU == 1) */ |
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[b7c7b75b] | 457 | } Context_Control_fp; |
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| 458 | |
---|
| 459 | #endif /* ASM */ |
---|
| 460 | |
---|
[9da42fb] | 461 | /* |
---|
| 462 | * Does the CPU follow the simple vectored interrupt model? |
---|
| 463 | * |
---|
| 464 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
---|
| 465 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
---|
| 466 | * table |
---|
| 467 | * |
---|
| 468 | * PowerPC Specific Information: |
---|
| 469 | * |
---|
| 470 | * The PowerPC and x86 were the first to use the PIC interrupt model. |
---|
| 471 | * They do not use the simple vectored interrupt model. |
---|
| 472 | */ |
---|
| 473 | #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE |
---|
| 474 | |
---|
[af16a7d2] | 475 | /* |
---|
| 476 | * Does RTEMS manage a dedicated interrupt stack in software? |
---|
| 477 | * |
---|
| 478 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
---|
| 479 | * If FALSE, nothing is done. |
---|
| 480 | * |
---|
| 481 | * If the CPU supports a dedicated interrupt stack in hardware, |
---|
| 482 | * then it is generally the responsibility of the BSP to allocate it |
---|
| 483 | * and set it up. |
---|
| 484 | * |
---|
| 485 | * If the CPU does not support a dedicated interrupt stack, then |
---|
| 486 | * the porter has two options: (1) execute interrupts on the |
---|
| 487 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
---|
| 488 | * interrupt stack. |
---|
| 489 | * |
---|
| 490 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
| 491 | * |
---|
| 492 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 493 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
| 494 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 495 | * is unclear what that would imply about the interrupt processing |
---|
| 496 | * procedure on that CPU. |
---|
| 497 | */ |
---|
| 498 | |
---|
| 499 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
---|
| 500 | |
---|
| 501 | /* |
---|
| 502 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
| 503 | * |
---|
| 504 | * If TRUE, then it must be installed during initialization. |
---|
| 505 | * If FALSE, then no installation is performed. |
---|
| 506 | * |
---|
| 507 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
| 508 | * |
---|
| 509 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 510 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
| 511 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 512 | * is unclear what that would imply about the interrupt processing |
---|
| 513 | * procedure on that CPU. |
---|
| 514 | */ |
---|
| 515 | |
---|
| 516 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
---|
| 517 | |
---|
| 518 | /* |
---|
| 519 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
| 520 | * |
---|
| 521 | * If TRUE, then the memory is allocated during initialization. |
---|
| 522 | * If FALSE, then the memory is allocated during initialization. |
---|
| 523 | * |
---|
| 524 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
---|
| 525 | */ |
---|
| 526 | |
---|
[ffbeb6f] | 527 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
---|
[af16a7d2] | 528 | |
---|
| 529 | /* |
---|
| 530 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
| 531 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
| 532 | * number (0)? |
---|
| 533 | */ |
---|
| 534 | |
---|
[141e16d] | 535 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
---|
[af16a7d2] | 536 | |
---|
| 537 | /* |
---|
| 538 | * Should the saving of the floating point registers be deferred |
---|
| 539 | * until a context switch is made to another different floating point |
---|
| 540 | * task? |
---|
| 541 | * |
---|
| 542 | * If TRUE, then the floating point context will not be stored until |
---|
| 543 | * necessary. It will remain in the floating point registers and not |
---|
| 544 | * disturned until another floating point task is switched to. |
---|
| 545 | * |
---|
| 546 | * If FALSE, then the floating point context is saved when a floating |
---|
| 547 | * point task is switched out and restored when the next floating point |
---|
| 548 | * task is restored. The state of the floating point registers between |
---|
| 549 | * those two operations is not specified. |
---|
| 550 | * |
---|
| 551 | * If the floating point context does NOT have to be saved as part of |
---|
| 552 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
| 553 | * |
---|
| 554 | * Setting this flag to TRUE results in using a different algorithm |
---|
| 555 | * for deciding when to save and restore the floating point context. |
---|
| 556 | * The deferred FP switch algorithm minimizes the number of times |
---|
| 557 | * the FP context is saved and restored. The FP context is not saved |
---|
| 558 | * until a context switch is made to another, different FP task. |
---|
| 559 | * Thus in a system with only one FP task, the FP context will never |
---|
| 560 | * be saved or restored. |
---|
| 561 | * |
---|
| 562 | * Note, however that compilers may use floating point registers/ |
---|
| 563 | * instructions for optimization or they may save/restore FP registers |
---|
| 564 | * on the stack. You must not use deferred switching in these cases |
---|
| 565 | * and on the PowerPC attempting to do so will raise a "FP unavailable" |
---|
| 566 | * exception. |
---|
| 567 | */ |
---|
| 568 | /* |
---|
| 569 | * ACB Note: This could make debugging tricky.. |
---|
| 570 | */ |
---|
| 571 | |
---|
| 572 | /* conservative setting (FALSE); probably doesn't affect performance too much */ |
---|
| 573 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
---|
| 574 | |
---|
[84e6f15] | 575 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
---|
| 576 | |
---|
[af16a7d2] | 577 | /* |
---|
| 578 | * Processor defined structures required for cpukit/score. |
---|
| 579 | */ |
---|
| 580 | |
---|
| 581 | #ifndef ASM |
---|
| 582 | |
---|
| 583 | /* |
---|
| 584 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 585 | * to generate an "uninitialized" FP context. It is filled in by |
---|
| 586 | * _CPU_Initialize and copied into the task's FP context area during |
---|
| 587 | * _CPU_Context_Initialize. |
---|
| 588 | */ |
---|
| 589 | |
---|
| 590 | /* EXTERN Context_Control_fp _CPU_Null_fp_context; */ |
---|
| 591 | |
---|
| 592 | #endif /* ndef ASM */ |
---|
| 593 | |
---|
| 594 | /* |
---|
| 595 | * This defines the number of levels and the mask used to pick those |
---|
| 596 | * bits out of a thread mode. |
---|
| 597 | */ |
---|
| 598 | |
---|
| 599 | #define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */ |
---|
| 600 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */ |
---|
| 601 | |
---|
| 602 | /* |
---|
| 603 | * The size of the floating point context area. On some CPUs this |
---|
| 604 | * will not be a "sizeof" because the format of the floating point |
---|
| 605 | * area is not defined -- only the size is. This is usually on |
---|
| 606 | * CPUs with a "floating point save context" instruction. |
---|
| 607 | */ |
---|
| 608 | |
---|
| 609 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 610 | |
---|
| 611 | /* |
---|
| 612 | * (Optional) # of bytes for libmisc/stackchk to check |
---|
| 613 | * If not specifed, then it defaults to something reasonable |
---|
| 614 | * for most architectures. |
---|
| 615 | */ |
---|
| 616 | |
---|
[8bb9d41] | 617 | #define CPU_STACK_CHECK_PATTERN_INITIALIZER \ |
---|
| 618 | { 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 619 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 620 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 621 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 622 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 623 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 624 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06, \ |
---|
| 625 | 0xFEEDF00D, 0x0BAD0D06, 0xDEADF00D, 0x600D0D06 } |
---|
[af16a7d2] | 626 | |
---|
| 627 | /* |
---|
| 628 | * Amount of extra stack (above minimum stack size) required by |
---|
| 629 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 630 | * system this thread must exist and be able to process all directives. |
---|
| 631 | */ |
---|
| 632 | |
---|
| 633 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 634 | |
---|
| 635 | /* |
---|
| 636 | * This is defined if the port has a special way to report the ISR nesting |
---|
| 637 | * level. Most ports maintain the variable _ISR_Nest_level. Note that |
---|
| 638 | * this is not an option - RTEMS/score _relies_ on _ISR_Nest_level |
---|
| 639 | * being maintained (e.g. watchdog queues). |
---|
| 640 | */ |
---|
| 641 | |
---|
| 642 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 643 | |
---|
| 644 | /* |
---|
| 645 | * ISR handler macros |
---|
| 646 | */ |
---|
| 647 | |
---|
| 648 | /* |
---|
| 649 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
| 650 | * level is returned in _isr_cookie. |
---|
| 651 | */ |
---|
| 652 | |
---|
| 653 | #ifndef ASM |
---|
| 654 | |
---|
[408609f6] | 655 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
| 656 | { |
---|
| 657 | return ( level & MSR_EE ) != 0; |
---|
| 658 | } |
---|
| 659 | |
---|
[0a7a30d] | 660 | #if !defined(PPC_DISABLE_INLINE_ISR_DISABLE_ENABLE) |
---|
| 661 | |
---|
[af16a7d2] | 662 | static inline uint32_t _CPU_ISR_Get_level( void ) |
---|
| 663 | { |
---|
| 664 | register unsigned int msr; |
---|
| 665 | _CPU_MSR_GET(msr); |
---|
| 666 | if (msr & MSR_EE) return 0; |
---|
| 667 | else return 1; |
---|
| 668 | } |
---|
| 669 | |
---|
| 670 | static inline void _CPU_ISR_Set_level( uint32_t level ) |
---|
| 671 | { |
---|
| 672 | register unsigned int msr; |
---|
| 673 | _CPU_MSR_GET(msr); |
---|
| 674 | if (!(level & CPU_MODES_INTERRUPT_MASK)) { |
---|
| 675 | msr |= ppc_interrupt_get_disable_mask(); |
---|
| 676 | } |
---|
| 677 | else { |
---|
| 678 | msr &= ~ppc_interrupt_get_disable_mask(); |
---|
| 679 | } |
---|
| 680 | _CPU_MSR_SET(msr); |
---|
| 681 | } |
---|
[0a7a30d] | 682 | #else |
---|
| 683 | /* disable, enable, etc. are in registers.h */ |
---|
| 684 | uint32_t ppc_get_interrupt_level( void ); |
---|
| 685 | void ppc_set_interrupt_level( uint32_t level ); |
---|
| 686 | #define _CPU_ISR_Get_level( _new_level ) ppc_get_interrupt_level() |
---|
| 687 | #define _CPU_ISR_Set_level( _new_level ) ppc_set_interrupt_level(_new_level) |
---|
| 688 | #endif |
---|
[af16a7d2] | 689 | |
---|
| 690 | #endif /* ASM */ |
---|
| 691 | |
---|
[f82752a4] | 692 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
[07d96453] | 693 | do { \ |
---|
| 694 | ppc_interrupt_disable(); \ |
---|
| 695 | __asm__ volatile ( \ |
---|
| 696 | "mr 3, %0\n" \ |
---|
| 697 | "mr 4, %1\n" \ |
---|
| 698 | "1:\n" \ |
---|
| 699 | "b 1b\n" \ |
---|
| 700 | : \ |
---|
| 701 | : "r" (_source), "r" (_error) \ |
---|
| 702 | : "memory" \ |
---|
| 703 | ); \ |
---|
| 704 | } while ( 0 ) |
---|
[af16a7d2] | 705 | |
---|
[b4f43549] | 706 | /* |
---|
[5961b4c7] | 707 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[b4f43549] | 708 | * that a "reasonable" small application should not have any problems. |
---|
| 709 | */ |
---|
| 710 | |
---|
| 711 | #define CPU_STACK_MINIMUM_SIZE (1024*8) |
---|
| 712 | |
---|
[5a9372f] | 713 | #if defined(__powerpc64__) |
---|
| 714 | #define CPU_SIZEOF_POINTER 8 |
---|
| 715 | #else |
---|
[f1738ed] | 716 | #define CPU_SIZEOF_POINTER 4 |
---|
[5a9372f] | 717 | #endif |
---|
[f1738ed] | 718 | |
---|
[b4f43549] | 719 | /* |
---|
| 720 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 721 | * alignment does not take into account the requirements for the stack. |
---|
| 722 | */ |
---|
| 723 | |
---|
| 724 | #define CPU_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 725 | |
---|
| 726 | /* |
---|
| 727 | * This number corresponds to the byte alignment requirement for the |
---|
| 728 | * heap handler. This alignment requirement may be stricter than that |
---|
| 729 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
---|
| 730 | * common for the heap to follow the same alignment requirement as |
---|
| 731 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
---|
| 732 | * then this should be set to CPU_ALIGNMENT. |
---|
| 733 | * |
---|
| 734 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 735 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 736 | */ |
---|
| 737 | |
---|
| 738 | #define CPU_HEAP_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 739 | |
---|
| 740 | /* |
---|
| 741 | * This number corresponds to the byte alignment requirement for memory |
---|
| 742 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 743 | * may be stricter than that for the data types alignment specified by |
---|
| 744 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 745 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
---|
| 746 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
---|
| 747 | * |
---|
| 748 | * NOTE: This does not have to be a power of 2. It does have to |
---|
| 749 | * be greater or equal to than CPU_ALIGNMENT. |
---|
| 750 | */ |
---|
| 751 | |
---|
| 752 | #define CPU_PARTITION_ALIGNMENT (PPC_ALIGNMENT) |
---|
| 753 | |
---|
| 754 | /* |
---|
| 755 | * This number corresponds to the byte alignment requirement for the |
---|
| 756 | * stack. This alignment requirement may be stricter than that for the |
---|
| 757 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
---|
| 758 | * is strict enough for the stack, then this should be set to 0. |
---|
| 759 | * |
---|
| 760 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
---|
| 761 | */ |
---|
| 762 | |
---|
| 763 | #define CPU_STACK_ALIGNMENT (PPC_STACK_ALIGNMENT) |
---|
| 764 | |
---|
[d4214b0] | 765 | #ifndef ASM |
---|
| 766 | /* The following routine swaps the endian format of an unsigned int. |
---|
| 767 | * It must be static because it is referenced indirectly. |
---|
| 768 | * |
---|
| 769 | * This version will work on any processor, but if there is a better |
---|
| 770 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 771 | * |
---|
| 772 | * swap least significant two bytes with 16-bit rotate |
---|
| 773 | * swap upper and lower 16-bits |
---|
| 774 | * swap most significant two bytes with 16-bit rotate |
---|
| 775 | * |
---|
| 776 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 777 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 778 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[5961b4c7] | 779 | * that interrupts would probably have to be disabled to ensure that |
---|
[d4214b0] | 780 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 781 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 782 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 783 | * will be fetched incorrectly. |
---|
| 784 | */ |
---|
[5bb38e15] | 785 | |
---|
[d4214b0] | 786 | static inline uint32_t CPU_swap_u32( |
---|
| 787 | uint32_t value |
---|
| 788 | ) |
---|
| 789 | { |
---|
| 790 | uint32_t swapped; |
---|
[5bb38e15] | 791 | |
---|
[3631c234] | 792 | __asm__ volatile("rlwimi %0,%1,8,24,31;" |
---|
[d4214b0] | 793 | "rlwimi %0,%1,24,16,23;" |
---|
| 794 | "rlwimi %0,%1,8,8,15;" |
---|
| 795 | "rlwimi %0,%1,24,0,7;" : |
---|
| 796 | "=&r" ((swapped)) : "r" ((value))); |
---|
| 797 | |
---|
| 798 | return( swapped ); |
---|
| 799 | } |
---|
| 800 | |
---|
| 801 | #define CPU_swap_u16( value ) \ |
---|
| 802 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 803 | |
---|
[24bf11e] | 804 | typedef uint32_t CPU_Counter_ticks; |
---|
| 805 | |
---|
| 806 | static inline CPU_Counter_ticks _CPU_Counter_read( void ) |
---|
| 807 | { |
---|
| 808 | CPU_Counter_ticks value; |
---|
| 809 | |
---|
[93f5adb] | 810 | #if defined(__PPC_CPU_E6500__) |
---|
[bb7bd148] | 811 | /* Use Alternate Time Base */ |
---|
| 812 | __asm__ volatile( "mfspr %0, 526" : "=r" (value) ); |
---|
[24bf11e] | 813 | #else |
---|
[e2fcb7d] | 814 | __asm__ volatile( "mfspr %0, 268" : "=r" (value) ); |
---|
[24bf11e] | 815 | #endif |
---|
| 816 | |
---|
| 817 | return value; |
---|
| 818 | } |
---|
| 819 | |
---|
| 820 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
---|
| 821 | CPU_Counter_ticks second, |
---|
| 822 | CPU_Counter_ticks first |
---|
| 823 | ) |
---|
| 824 | { |
---|
| 825 | return second - first; |
---|
| 826 | } |
---|
| 827 | |
---|
[d4214b0] | 828 | #endif /* ASM */ |
---|
| 829 | |
---|
[58847845] | 830 | |
---|
[6b25a47] | 831 | #ifndef ASM |
---|
| 832 | /* Context handler macros */ |
---|
| 833 | |
---|
| 834 | /* |
---|
| 835 | * Initialize the context to a state suitable for starting a |
---|
| 836 | * task after a context restore operation. Generally, this |
---|
| 837 | * involves: |
---|
| 838 | * |
---|
| 839 | * - setting a starting address |
---|
| 840 | * - preparing the stack |
---|
| 841 | * - preparing the stack and frame pointers |
---|
| 842 | * - setting the proper interrupt level in the context |
---|
| 843 | * - initializing the floating point context |
---|
| 844 | * |
---|
| 845 | * This routine generally does not set any unnecessary register |
---|
| 846 | * in the context. The state of the "general data" registers is |
---|
| 847 | * undefined at task start time. |
---|
| 848 | */ |
---|
[d4214b0] | 849 | |
---|
[6b25a47] | 850 | void _CPU_Context_Initialize( |
---|
| 851 | Context_Control *the_context, |
---|
[7837728b] | 852 | void *stack_base, |
---|
| 853 | size_t size, |
---|
[6b25a47] | 854 | uint32_t new_level, |
---|
| 855 | void *entry_point, |
---|
[022851a] | 856 | bool is_fp, |
---|
| 857 | void *tls_area |
---|
[6b25a47] | 858 | ); |
---|
| 859 | |
---|
| 860 | /* |
---|
| 861 | * This routine is responsible for somehow restarting the currently |
---|
| 862 | * executing task. If you are lucky, then all that is necessary |
---|
| 863 | * is restoring the context. Otherwise, there will need to be |
---|
| 864 | * a special assembly routine which does something special in this |
---|
| 865 | * case. Context_Restore should work most of the time. It will |
---|
| 866 | * not work if restarting self conflicts with the stack frame |
---|
| 867 | * assumptions of restoring a context. |
---|
| 868 | */ |
---|
| 869 | |
---|
| 870 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 871 | _CPU_Context_restore( (_the_context) ); |
---|
| 872 | |
---|
| 873 | /* |
---|
| 874 | * This routine initializes the FP context area passed to it to. |
---|
| 875 | * There are a few standard ways in which to initialize the |
---|
| 876 | * floating point context. The code included for this macro assumes |
---|
| 877 | * that this is a CPU in which a "initial" FP context was saved into |
---|
| 878 | * _CPU_Null_fp_context and it simply copies it to the destination |
---|
| 879 | * context passed to it. |
---|
| 880 | * |
---|
| 881 | * Other models include (1) not doing anything, and (2) putting |
---|
| 882 | * a "null FP status word" in the correct place in the FP context. |
---|
| 883 | */ |
---|
| 884 | |
---|
| 885 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
[2067679] | 886 | memset( *(_destination), 0, sizeof( **(_destination) ) ) |
---|
[6b25a47] | 887 | |
---|
| 888 | /* end of Context handler macros */ |
---|
| 889 | #endif /* ASM */ |
---|
| 890 | |
---|
[779939b2] | 891 | #ifndef ASM |
---|
| 892 | /* Bitfield handler macros */ |
---|
| 893 | |
---|
[987ea1a] | 894 | #define CPU_USE_GENERIC_BITFIELD_CODE FALSE |
---|
| 895 | |
---|
[779939b2] | 896 | /* |
---|
| 897 | * This routine sets _output to the bit number of the first bit |
---|
[f570b071] | 898 | * set in _value. _value is of CPU dependent type Priority_bit_map_Word. |
---|
[779939b2] | 899 | * This type may be either 16 or 32 bits wide although only the 16 |
---|
| 900 | * least significant bits will be used. |
---|
| 901 | * |
---|
| 902 | * There are a number of variables in using a "find first bit" type |
---|
| 903 | * instruction. |
---|
| 904 | * |
---|
| 905 | * (1) What happens when run on a value of zero? |
---|
| 906 | * (2) Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 907 | * (3) The numbering may be zero or one based. |
---|
| 908 | * (4) The "find first bit" instruction may search from MSB or LSB. |
---|
| 909 | * |
---|
| 910 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
| 911 | * (2),(3), (4) are handled by the macros _CPU_Priority_mask() and |
---|
| 912 | * _CPU_Priority_Bits_index(). These three form a set of routines |
---|
| 913 | * which must logically operate together. Bits in the _value are |
---|
| 914 | * set and cleared based on masks built by _CPU_Priority_mask(). |
---|
| 915 | * The basic major and minor values calculated by _Priority_Major() |
---|
| 916 | * and _Priority_Minor() are "massaged" by _CPU_Priority_Bits_index() |
---|
| 917 | * to properly range between the values returned by the "find first bit" |
---|
| 918 | * instruction. This makes it possible for _Priority_Get_highest() to |
---|
| 919 | * calculate the major and directly index into the minor table. |
---|
| 920 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 921 | * is the first bit found. |
---|
| 922 | * |
---|
| 923 | * This entire "find first bit" and mapping process depends heavily |
---|
| 924 | * on the manner in which a priority is broken into a major and minor |
---|
| 925 | * components with the major being the 4 MSB of a priority and minor |
---|
| 926 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 927 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 928 | * to the lowest priority. |
---|
| 929 | * |
---|
| 930 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 931 | * there are ways to make do without it. Here are a handful of ways |
---|
| 932 | * to implement this in software: |
---|
| 933 | * |
---|
| 934 | * - a series of 16 bit test instructions |
---|
| 935 | * - a "binary search using if's" |
---|
| 936 | * - _number = 0 |
---|
| 937 | * if _value > 0x00ff |
---|
| 938 | * _value >>=8 |
---|
| 939 | * _number = 8; |
---|
| 940 | * |
---|
| 941 | * if _value > 0x0000f |
---|
| 942 | * _value >=8 |
---|
| 943 | * _number += 4 |
---|
| 944 | * |
---|
| 945 | * _number += bit_set_table[ _value ] |
---|
| 946 | * |
---|
| 947 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 948 | * bit set |
---|
| 949 | */ |
---|
| 950 | |
---|
| 951 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 952 | { \ |
---|
[3631c234] | 953 | __asm__ volatile ("cntlzw %0, %1" : "=r" ((_output)), "=r" ((_value)) : \ |
---|
[779939b2] | 954 | "1" ((_value))); \ |
---|
[b04b76c6] | 955 | (_output) = (_output) - 16; \ |
---|
[779939b2] | 956 | } |
---|
| 957 | |
---|
| 958 | /* end of Bitfield handler macros */ |
---|
| 959 | |
---|
| 960 | /* |
---|
| 961 | * This routine builds the mask which corresponds to the bit fields |
---|
| 962 | * as searched by _CPU_Bitfield_Find_first_bit(). See the discussion |
---|
| 963 | * for that routine. |
---|
| 964 | */ |
---|
| 965 | |
---|
| 966 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
[b04b76c6] | 967 | ( 0x8000u >> (_bit_number) ) |
---|
[779939b2] | 968 | |
---|
| 969 | /* |
---|
| 970 | * This routine translates the bit numbers returned by |
---|
| 971 | * _CPU_Bitfield_Find_first_bit() into something suitable for use as |
---|
| 972 | * a major or minor component of a priority. See the discussion |
---|
| 973 | * for that routine. |
---|
| 974 | */ |
---|
| 975 | |
---|
| 976 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 977 | (_priority) |
---|
| 978 | |
---|
| 979 | /* end of Priority handler macros */ |
---|
| 980 | #endif /* ASM */ |
---|
| 981 | |
---|
[8773879] | 982 | /* functions */ |
---|
| 983 | |
---|
| 984 | #ifndef ASM |
---|
| 985 | |
---|
| 986 | /* |
---|
| 987 | * _CPU_Initialize |
---|
| 988 | * |
---|
| 989 | * This routine performs CPU dependent initialization. |
---|
| 990 | */ |
---|
| 991 | |
---|
[ef1be69] | 992 | void _CPU_Initialize(void); |
---|
[8773879] | 993 | |
---|
| 994 | /* |
---|
| 995 | * _CPU_ISR_install_vector |
---|
| 996 | * |
---|
| 997 | * This routine installs an interrupt vector. |
---|
| 998 | */ |
---|
| 999 | |
---|
| 1000 | void _CPU_ISR_install_vector( |
---|
| 1001 | uint32_t vector, |
---|
| 1002 | proc_ptr new_handler, |
---|
| 1003 | proc_ptr *old_handler |
---|
| 1004 | ); |
---|
| 1005 | |
---|
| 1006 | /* |
---|
| 1007 | * _CPU_Context_switch |
---|
| 1008 | * |
---|
| 1009 | * This routine switches from the run context to the heir context. |
---|
| 1010 | */ |
---|
| 1011 | |
---|
| 1012 | void _CPU_Context_switch( |
---|
| 1013 | Context_Control *run, |
---|
| 1014 | Context_Control *heir |
---|
| 1015 | ); |
---|
| 1016 | |
---|
| 1017 | /* |
---|
| 1018 | * _CPU_Context_restore |
---|
| 1019 | * |
---|
| 1020 | * This routine is generallu used only to restart self in an |
---|
| 1021 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
| 1022 | * |
---|
| 1023 | * NOTE: May be unnecessary to reload some registers. |
---|
| 1024 | */ |
---|
| 1025 | |
---|
| 1026 | void _CPU_Context_restore( |
---|
| 1027 | Context_Control *new_context |
---|
[143696a] | 1028 | ) RTEMS_NO_RETURN; |
---|
[8773879] | 1029 | |
---|
| 1030 | /* |
---|
| 1031 | * _CPU_Context_save_fp |
---|
| 1032 | * |
---|
| 1033 | * This routine saves the floating point context passed to it. |
---|
| 1034 | */ |
---|
| 1035 | |
---|
| 1036 | void _CPU_Context_save_fp( |
---|
[b60dc893] | 1037 | Context_Control_fp **fp_context_ptr |
---|
[8773879] | 1038 | ); |
---|
| 1039 | |
---|
| 1040 | /* |
---|
| 1041 | * _CPU_Context_restore_fp |
---|
| 1042 | * |
---|
| 1043 | * This routine restores the floating point context passed to it. |
---|
| 1044 | */ |
---|
| 1045 | |
---|
| 1046 | void _CPU_Context_restore_fp( |
---|
[b60dc893] | 1047 | Context_Control_fp **fp_context_ptr |
---|
[8773879] | 1048 | ); |
---|
| 1049 | |
---|
[39993d6] | 1050 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
---|
| 1051 | |
---|
| 1052 | void _CPU_Context_validate( uintptr_t pattern ); |
---|
| 1053 | |
---|
[ffbeb6f] | 1054 | #ifdef RTEMS_SMP |
---|
[53e008b] | 1055 | uint32_t _CPU_SMP_Initialize( void ); |
---|
| 1056 | |
---|
| 1057 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
---|
| 1058 | |
---|
| 1059 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
---|
[4627fcd] | 1060 | |
---|
[c34f94f7] | 1061 | void _CPU_SMP_Prepare_start_multitasking( void ); |
---|
| 1062 | |
---|
[47d60134] | 1063 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
[39e51758] | 1064 | { |
---|
| 1065 | uint32_t pir; |
---|
| 1066 | |
---|
| 1067 | /* Use Book E Processor ID Register (PIR) */ |
---|
[47d60134] | 1068 | __asm__ volatile ( |
---|
[39e51758] | 1069 | "mfspr %[pir], 286" |
---|
| 1070 | : [pir] "=&r" (pir) |
---|
| 1071 | ); |
---|
| 1072 | |
---|
| 1073 | return pir; |
---|
| 1074 | } |
---|
| 1075 | |
---|
[ca63ae2] | 1076 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
[39e51758] | 1077 | |
---|
[07f6e419] | 1078 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
[ffbeb6f] | 1079 | { |
---|
| 1080 | __asm__ volatile ( "" : : : "memory" ); |
---|
| 1081 | } |
---|
| 1082 | |
---|
[f7740e97] | 1083 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
[ffbeb6f] | 1084 | { |
---|
| 1085 | __asm__ volatile ( "" : : : "memory" ); |
---|
| 1086 | } |
---|
| 1087 | #endif |
---|
| 1088 | |
---|
[d2202ac] | 1089 | typedef struct { |
---|
[a6f84b27] | 1090 | uintptr_t EXC_SRR0; |
---|
| 1091 | uintptr_t EXC_SRR1; |
---|
[d2202ac] | 1092 | uint32_t _EXC_number; |
---|
[a6f84b27] | 1093 | uint32_t RESERVED_FOR_ALIGNMENT_0; |
---|
[d2202ac] | 1094 | uint32_t EXC_CR; |
---|
| 1095 | uint32_t EXC_XER; |
---|
[a6f84b27] | 1096 | uintptr_t EXC_CTR; |
---|
| 1097 | uintptr_t EXC_LR; |
---|
| 1098 | uintptr_t RESERVED_FOR_ALIGNMENT_1; |
---|
[d2202ac] | 1099 | #ifdef __SPE__ |
---|
| 1100 | uint32_t EXC_SPEFSCR; |
---|
| 1101 | uint64_t EXC_ACC; |
---|
| 1102 | #endif |
---|
| 1103 | PPC_GPR_TYPE GPR0; |
---|
| 1104 | PPC_GPR_TYPE GPR1; |
---|
| 1105 | PPC_GPR_TYPE GPR2; |
---|
| 1106 | PPC_GPR_TYPE GPR3; |
---|
| 1107 | PPC_GPR_TYPE GPR4; |
---|
| 1108 | PPC_GPR_TYPE GPR5; |
---|
| 1109 | PPC_GPR_TYPE GPR6; |
---|
| 1110 | PPC_GPR_TYPE GPR7; |
---|
| 1111 | PPC_GPR_TYPE GPR8; |
---|
| 1112 | PPC_GPR_TYPE GPR9; |
---|
| 1113 | PPC_GPR_TYPE GPR10; |
---|
| 1114 | PPC_GPR_TYPE GPR11; |
---|
| 1115 | PPC_GPR_TYPE GPR12; |
---|
| 1116 | PPC_GPR_TYPE GPR13; |
---|
| 1117 | PPC_GPR_TYPE GPR14; |
---|
| 1118 | PPC_GPR_TYPE GPR15; |
---|
| 1119 | PPC_GPR_TYPE GPR16; |
---|
| 1120 | PPC_GPR_TYPE GPR17; |
---|
| 1121 | PPC_GPR_TYPE GPR18; |
---|
| 1122 | PPC_GPR_TYPE GPR19; |
---|
| 1123 | PPC_GPR_TYPE GPR20; |
---|
| 1124 | PPC_GPR_TYPE GPR21; |
---|
| 1125 | PPC_GPR_TYPE GPR22; |
---|
| 1126 | PPC_GPR_TYPE GPR23; |
---|
| 1127 | PPC_GPR_TYPE GPR24; |
---|
| 1128 | PPC_GPR_TYPE GPR25; |
---|
| 1129 | PPC_GPR_TYPE GPR26; |
---|
| 1130 | PPC_GPR_TYPE GPR27; |
---|
| 1131 | PPC_GPR_TYPE GPR28; |
---|
| 1132 | PPC_GPR_TYPE GPR29; |
---|
| 1133 | PPC_GPR_TYPE GPR30; |
---|
| 1134 | PPC_GPR_TYPE GPR31; |
---|
[a6f84b27] | 1135 | uintptr_t RESERVED_FOR_ALIGNMENT_2; |
---|
[3e2647a7] | 1136 | #ifdef PPC_MULTILIB_ALTIVEC |
---|
| 1137 | uint32_t VRSAVE; |
---|
[a6f84b27] | 1138 | uint32_t RESERVED_FOR_ALIGNMENT_3[3]; |
---|
[60d39b66] | 1139 | |
---|
| 1140 | /* This field must take stvewx/lvewx requirements into account */ |
---|
[a6f84b27] | 1141 | uint32_t RESERVED_FOR_ALIGNMENT_4[3]; |
---|
[60d39b66] | 1142 | uint32_t VSCR; |
---|
| 1143 | |
---|
[3e2647a7] | 1144 | uint8_t V0[16]; |
---|
| 1145 | uint8_t V1[16]; |
---|
| 1146 | uint8_t V2[16]; |
---|
| 1147 | uint8_t V3[16]; |
---|
| 1148 | uint8_t V4[16]; |
---|
| 1149 | uint8_t V5[16]; |
---|
| 1150 | uint8_t V6[16]; |
---|
| 1151 | uint8_t V7[16]; |
---|
| 1152 | uint8_t V8[16]; |
---|
| 1153 | uint8_t V9[16]; |
---|
| 1154 | uint8_t V10[16]; |
---|
| 1155 | uint8_t V11[16]; |
---|
| 1156 | uint8_t V12[16]; |
---|
| 1157 | uint8_t V13[16]; |
---|
| 1158 | uint8_t V14[16]; |
---|
| 1159 | uint8_t V15[16]; |
---|
| 1160 | uint8_t V16[16]; |
---|
| 1161 | uint8_t V17[16]; |
---|
| 1162 | uint8_t V18[16]; |
---|
| 1163 | uint8_t V19[16]; |
---|
| 1164 | uint8_t V20[16]; |
---|
| 1165 | uint8_t V21[16]; |
---|
| 1166 | uint8_t V22[16]; |
---|
| 1167 | uint8_t V23[16]; |
---|
| 1168 | uint8_t V24[16]; |
---|
| 1169 | uint8_t V25[16]; |
---|
| 1170 | uint8_t V26[16]; |
---|
| 1171 | uint8_t V27[16]; |
---|
| 1172 | uint8_t V28[16]; |
---|
| 1173 | uint8_t V29[16]; |
---|
| 1174 | uint8_t V30[16]; |
---|
| 1175 | uint8_t V31[16]; |
---|
| 1176 | #endif |
---|
| 1177 | #ifdef PPC_MULTILIB_FPU |
---|
| 1178 | double F0; |
---|
| 1179 | double F1; |
---|
| 1180 | double F2; |
---|
| 1181 | double F3; |
---|
| 1182 | double F4; |
---|
| 1183 | double F5; |
---|
| 1184 | double F6; |
---|
| 1185 | double F7; |
---|
| 1186 | double F8; |
---|
| 1187 | double F9; |
---|
| 1188 | double F10; |
---|
| 1189 | double F11; |
---|
| 1190 | double F12; |
---|
| 1191 | double F13; |
---|
| 1192 | double F14; |
---|
| 1193 | double F15; |
---|
| 1194 | double F16; |
---|
| 1195 | double F17; |
---|
| 1196 | double F18; |
---|
| 1197 | double F19; |
---|
| 1198 | double F20; |
---|
| 1199 | double F21; |
---|
| 1200 | double F22; |
---|
| 1201 | double F23; |
---|
| 1202 | double F24; |
---|
| 1203 | double F25; |
---|
| 1204 | double F26; |
---|
| 1205 | double F27; |
---|
| 1206 | double F28; |
---|
| 1207 | double F29; |
---|
| 1208 | double F30; |
---|
| 1209 | double F31; |
---|
| 1210 | uint64_t FPSCR; |
---|
[a6f84b27] | 1211 | uint64_t RESERVED_FOR_ALIGNMENT_5; |
---|
[3e2647a7] | 1212 | #endif |
---|
[d2202ac] | 1213 | } CPU_Exception_frame; |
---|
| 1214 | |
---|
[c48cf0bd] | 1215 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
[815994f] | 1216 | |
---|
[6c28773e] | 1217 | /* |
---|
| 1218 | * _CPU_Initialize_altivec() |
---|
| 1219 | * |
---|
| 1220 | * Global altivec-related initialization. |
---|
| 1221 | */ |
---|
| 1222 | void |
---|
| 1223 | _CPU_Initialize_altivec(void); |
---|
| 1224 | |
---|
| 1225 | /* |
---|
| 1226 | * _CPU_Context_switch_altivec |
---|
| 1227 | * |
---|
| 1228 | * This routine switches the altivec contexts passed to it. |
---|
| 1229 | */ |
---|
| 1230 | |
---|
| 1231 | void |
---|
| 1232 | _CPU_Context_switch_altivec( |
---|
[56435e6] | 1233 | ppc_context *from, |
---|
| 1234 | ppc_context *to |
---|
[6c28773e] | 1235 | ); |
---|
| 1236 | |
---|
| 1237 | /* |
---|
| 1238 | * _CPU_Context_restore_altivec |
---|
| 1239 | * |
---|
| 1240 | * This routine restores the altivec context passed to it. |
---|
| 1241 | */ |
---|
| 1242 | |
---|
| 1243 | void |
---|
| 1244 | _CPU_Context_restore_altivec( |
---|
[56435e6] | 1245 | ppc_context *ctxt |
---|
[6c28773e] | 1246 | ); |
---|
| 1247 | |
---|
| 1248 | /* |
---|
| 1249 | * _CPU_Context_initialize_altivec |
---|
| 1250 | * |
---|
| 1251 | * This routine initializes the altivec context passed to it. |
---|
| 1252 | */ |
---|
| 1253 | |
---|
| 1254 | void |
---|
| 1255 | _CPU_Context_initialize_altivec( |
---|
[56435e6] | 1256 | ppc_context *ctxt |
---|
[6c28773e] | 1257 | ); |
---|
| 1258 | |
---|
[8773879] | 1259 | void _CPU_Fatal_error( |
---|
| 1260 | uint32_t _error |
---|
| 1261 | ); |
---|
| 1262 | |
---|
[d978d1b] | 1263 | /** Type that can store a 32-bit integer or a pointer. */ |
---|
| 1264 | typedef uintptr_t CPU_Uint32ptr; |
---|
| 1265 | |
---|
[8773879] | 1266 | #endif /* ASM */ |
---|
| 1267 | |
---|
[af16a7d2] | 1268 | #ifdef __cplusplus |
---|
| 1269 | } |
---|
| 1270 | #endif |
---|
| 1271 | |
---|
[6b25a47] | 1272 | #endif /* _RTEMS_SCORE_CPU_H */ |
---|