source: rtems/cpukit/score/cpu/powerpc/cpu.c @ 8b65b574

Last change on this file since 8b65b574 was 8b65b574, checked in by Sebastian Huber <sebastian.huber@…>, on 07/28/21 at 12:41:32

score: Canonicalize _CPU_Fatal_halt()

Move _CPU_Fatal_halt() declaration to <rtems/score/cpuimpl.h> and make sure it
is a proper declaration of a function which does not return. Fix the type of
the error code. If necessary, add the implementation to cpu.c. Implementing
_CPU_Fatal_halt() as a function makes it possible to wrap this function for
example to fully test _Terminate().
  • Property mode set to 100644
File size: 12.3 KB
Line 
1/**
2 *  @file
3 *
4 *  @brief PowerPC Dependent Source
5 */
6
7/*
8 * Copyright (C) 2009, 2017 embedded brains GmbH.
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15/*
16 * For now, this file is just a stub to work around
17 * structural deficiencies of the powerpc port.
18 */
19
20#ifdef HAVE_CONFIG_H
21#include "config.h"
22#endif
23
24#include <rtems/score/cpuimpl.h>
25
26#define PPC_ASSERT_OFFSET(field, off) \
27  RTEMS_STATIC_ASSERT( \
28    offsetof(ppc_context, field) + PPC_DEFAULT_CACHE_LINE_SIZE \
29      == PPC_CONTEXT_OFFSET_ ## off, \
30    ppc_context_offset_ ## field \
31  )
32
33PPC_ASSERT_OFFSET(gpr1, GPR1);
34PPC_ASSERT_OFFSET(msr, MSR);
35PPC_ASSERT_OFFSET(lr, LR);
36PPC_ASSERT_OFFSET(cr, CR);
37PPC_ASSERT_OFFSET(gpr14, GPR14);
38PPC_ASSERT_OFFSET(gpr15, GPR15);
39PPC_ASSERT_OFFSET(gpr16, GPR16);
40PPC_ASSERT_OFFSET(gpr17, GPR17);
41PPC_ASSERT_OFFSET(gpr18, GPR18);
42PPC_ASSERT_OFFSET(gpr19, GPR19);
43PPC_ASSERT_OFFSET(gpr20, GPR20);
44PPC_ASSERT_OFFSET(gpr21, GPR21);
45PPC_ASSERT_OFFSET(gpr22, GPR22);
46PPC_ASSERT_OFFSET(gpr23, GPR23);
47PPC_ASSERT_OFFSET(gpr24, GPR24);
48PPC_ASSERT_OFFSET(gpr25, GPR25);
49PPC_ASSERT_OFFSET(gpr26, GPR26);
50PPC_ASSERT_OFFSET(gpr27, GPR27);
51PPC_ASSERT_OFFSET(gpr28, GPR28);
52PPC_ASSERT_OFFSET(gpr29, GPR29);
53PPC_ASSERT_OFFSET(gpr30, GPR30);
54PPC_ASSERT_OFFSET(gpr31, GPR31);
55PPC_ASSERT_OFFSET(tp, TP);
56PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE);
57
58#ifdef RTEMS_SMP
59  PPC_ASSERT_OFFSET(is_executing, IS_EXECUTING);
60#endif
61
62#ifdef PPC_MULTILIB_ALTIVEC
63  RTEMS_STATIC_ASSERT(
64    PPC_CONTEXT_OFFSET_V20 % 16 == 0,
65    ppc_context_altivec
66  );
67  PPC_ASSERT_OFFSET(v20, V20);
68  PPC_ASSERT_OFFSET(v21, V21);
69  PPC_ASSERT_OFFSET(v22, V22);
70  PPC_ASSERT_OFFSET(v23, V23);
71  PPC_ASSERT_OFFSET(v24, V24);
72  PPC_ASSERT_OFFSET(v25, V25);
73  PPC_ASSERT_OFFSET(v26, V26);
74  PPC_ASSERT_OFFSET(v27, V27);
75  PPC_ASSERT_OFFSET(v28, V28);
76  PPC_ASSERT_OFFSET(v29, V29);
77  PPC_ASSERT_OFFSET(v30, V30);
78  PPC_ASSERT_OFFSET(v31, V31);
79  PPC_ASSERT_OFFSET(vrsave, VRSAVE);
80#endif
81
82#ifdef PPC_MULTILIB_FPU
83  PPC_ASSERT_OFFSET(f14, F14);
84  PPC_ASSERT_OFFSET(f15, F15);
85  PPC_ASSERT_OFFSET(f16, F16);
86  PPC_ASSERT_OFFSET(f17, F17);
87  PPC_ASSERT_OFFSET(f18, F18);
88  PPC_ASSERT_OFFSET(f19, F19);
89  PPC_ASSERT_OFFSET(f20, F20);
90  PPC_ASSERT_OFFSET(f21, F21);
91  PPC_ASSERT_OFFSET(f22, F22);
92  PPC_ASSERT_OFFSET(f23, F23);
93  PPC_ASSERT_OFFSET(f24, F24);
94  PPC_ASSERT_OFFSET(f25, F25);
95  PPC_ASSERT_OFFSET(f26, F26);
96  PPC_ASSERT_OFFSET(f27, F27);
97  PPC_ASSERT_OFFSET(f28, F28);
98  PPC_ASSERT_OFFSET(f29, F29);
99  PPC_ASSERT_OFFSET(f30, F30);
100  PPC_ASSERT_OFFSET(f31, F31);
101#endif
102
103RTEMS_STATIC_ASSERT(
104  sizeof(Context_Control) % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
105  ppc_context_size
106);
107
108#define PPC_EXC_ASSERT_OFFSET(field, off) \
109  RTEMS_STATIC_ASSERT( \
110    offsetof(CPU_Exception_frame, field) + FRAME_LINK_SPACE == off, \
111    CPU_Exception_frame_offset_ ## field \
112  )
113
114#define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \
115  PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET)
116
117#define PPC_EXC_MIN_ASSERT_OFFSET(field, off) \
118  RTEMS_STATIC_ASSERT( \
119    offsetof(CPU_Interrupt_frame, field) == off, \
120    CPU_Interrupt_frame_offset_ ## field \
121  )
122
123#define PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(field) \
124  PPC_EXC_MIN_ASSERT_OFFSET(field, field ## _OFFSET)
125
126PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
127PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
128PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET);
129PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR);
130PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR);
131PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER);
132PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR);
133#ifdef __SPE__
134  PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
135  PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
136#endif
137PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0);
138PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1);
139PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2);
140PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3);
141PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4);
142PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5);
143PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6);
144PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7);
145PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8);
146PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9);
147PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10);
148PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11);
149PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12);
150PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13);
151PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14);
152PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15);
153PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16);
154PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17);
155PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18);
156PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19);
157PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20);
158PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21);
159PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22);
160PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23);
161PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24);
162PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25);
163PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26);
164PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27);
165PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28);
166PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29);
167PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30);
168PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31);
169
170PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
171PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
172PPC_EXC_MIN_ASSERT_OFFSET(
173  EXC_INTERRUPT_ENTRY_INSTANT,
174  PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET
175);
176PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CR);
177PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CTR);
178PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_XER);
179PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_LR);
180PPC_EXC_MIN_ASSERT_OFFSET(EXC_INTERRUPT_FRAME, PPC_EXC_INTERRUPT_FRAME_OFFSET);
181#ifdef __SPE__
182  PPC_EXC_MIN_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
183  PPC_EXC_MIN_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
184#endif
185PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR0);
186PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR1);
187PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR2);
188PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR3);
189PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR4);
190PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR5);
191PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR6);
192PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR7);
193PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR8);
194PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR9);
195PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR10);
196PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR11);
197PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR12);
198
199#ifdef PPC_MULTILIB_ALTIVEC
200PPC_EXC_ASSERT_OFFSET(VSCR, PPC_EXC_VSCR_OFFSET);
201PPC_EXC_ASSERT_OFFSET(VRSAVE, PPC_EXC_VRSAVE_OFFSET);
202RTEMS_STATIC_ASSERT(PPC_EXC_VR_OFFSET(0) % 16 == 0, PPC_EXC_VR_OFFSET);
203PPC_EXC_ASSERT_OFFSET(V0, PPC_EXC_VR_OFFSET(0));
204PPC_EXC_ASSERT_OFFSET(V1, PPC_EXC_VR_OFFSET(1));
205PPC_EXC_ASSERT_OFFSET(V2, PPC_EXC_VR_OFFSET(2));
206PPC_EXC_ASSERT_OFFSET(V3, PPC_EXC_VR_OFFSET(3));
207PPC_EXC_ASSERT_OFFSET(V4, PPC_EXC_VR_OFFSET(4));
208PPC_EXC_ASSERT_OFFSET(V5, PPC_EXC_VR_OFFSET(5));
209PPC_EXC_ASSERT_OFFSET(V6, PPC_EXC_VR_OFFSET(6));
210PPC_EXC_ASSERT_OFFSET(V7, PPC_EXC_VR_OFFSET(7));
211PPC_EXC_ASSERT_OFFSET(V8, PPC_EXC_VR_OFFSET(8));
212PPC_EXC_ASSERT_OFFSET(V9, PPC_EXC_VR_OFFSET(9));
213PPC_EXC_ASSERT_OFFSET(V10, PPC_EXC_VR_OFFSET(10));
214PPC_EXC_ASSERT_OFFSET(V11, PPC_EXC_VR_OFFSET(11));
215PPC_EXC_ASSERT_OFFSET(V12, PPC_EXC_VR_OFFSET(12));
216PPC_EXC_ASSERT_OFFSET(V13, PPC_EXC_VR_OFFSET(13));
217PPC_EXC_ASSERT_OFFSET(V14, PPC_EXC_VR_OFFSET(14));
218PPC_EXC_ASSERT_OFFSET(V15, PPC_EXC_VR_OFFSET(15));
219PPC_EXC_ASSERT_OFFSET(V16, PPC_EXC_VR_OFFSET(16));
220PPC_EXC_ASSERT_OFFSET(V17, PPC_EXC_VR_OFFSET(17));
221PPC_EXC_ASSERT_OFFSET(V18, PPC_EXC_VR_OFFSET(18));
222PPC_EXC_ASSERT_OFFSET(V19, PPC_EXC_VR_OFFSET(19));
223PPC_EXC_ASSERT_OFFSET(V20, PPC_EXC_VR_OFFSET(20));
224PPC_EXC_ASSERT_OFFSET(V21, PPC_EXC_VR_OFFSET(21));
225PPC_EXC_ASSERT_OFFSET(V22, PPC_EXC_VR_OFFSET(22));
226PPC_EXC_ASSERT_OFFSET(V23, PPC_EXC_VR_OFFSET(23));
227PPC_EXC_ASSERT_OFFSET(V24, PPC_EXC_VR_OFFSET(24));
228PPC_EXC_ASSERT_OFFSET(V25, PPC_EXC_VR_OFFSET(25));
229PPC_EXC_ASSERT_OFFSET(V26, PPC_EXC_VR_OFFSET(26));
230PPC_EXC_ASSERT_OFFSET(V27, PPC_EXC_VR_OFFSET(27));
231PPC_EXC_ASSERT_OFFSET(V28, PPC_EXC_VR_OFFSET(28));
232PPC_EXC_ASSERT_OFFSET(V29, PPC_EXC_VR_OFFSET(29));
233PPC_EXC_ASSERT_OFFSET(V30, PPC_EXC_VR_OFFSET(30));
234PPC_EXC_ASSERT_OFFSET(V31, PPC_EXC_VR_OFFSET(31));
235
236PPC_EXC_MIN_ASSERT_OFFSET(VSCR, PPC_EXC_MIN_VSCR_OFFSET);
237RTEMS_STATIC_ASSERT(PPC_EXC_MIN_VR_OFFSET(0) % 16 == 0, PPC_EXC_MIN_VR_OFFSET);
238PPC_EXC_MIN_ASSERT_OFFSET(V0, PPC_EXC_MIN_VR_OFFSET(0));
239PPC_EXC_MIN_ASSERT_OFFSET(V1, PPC_EXC_MIN_VR_OFFSET(1));
240PPC_EXC_MIN_ASSERT_OFFSET(V2, PPC_EXC_MIN_VR_OFFSET(2));
241PPC_EXC_MIN_ASSERT_OFFSET(V3, PPC_EXC_MIN_VR_OFFSET(3));
242PPC_EXC_MIN_ASSERT_OFFSET(V4, PPC_EXC_MIN_VR_OFFSET(4));
243PPC_EXC_MIN_ASSERT_OFFSET(V5, PPC_EXC_MIN_VR_OFFSET(5));
244PPC_EXC_MIN_ASSERT_OFFSET(V6, PPC_EXC_MIN_VR_OFFSET(6));
245PPC_EXC_MIN_ASSERT_OFFSET(V7, PPC_EXC_MIN_VR_OFFSET(7));
246PPC_EXC_MIN_ASSERT_OFFSET(V8, PPC_EXC_MIN_VR_OFFSET(8));
247PPC_EXC_MIN_ASSERT_OFFSET(V9, PPC_EXC_MIN_VR_OFFSET(9));
248PPC_EXC_MIN_ASSERT_OFFSET(V10, PPC_EXC_MIN_VR_OFFSET(10));
249PPC_EXC_MIN_ASSERT_OFFSET(V11, PPC_EXC_MIN_VR_OFFSET(11));
250PPC_EXC_MIN_ASSERT_OFFSET(V12, PPC_EXC_MIN_VR_OFFSET(12));
251PPC_EXC_MIN_ASSERT_OFFSET(V13, PPC_EXC_MIN_VR_OFFSET(13));
252PPC_EXC_MIN_ASSERT_OFFSET(V14, PPC_EXC_MIN_VR_OFFSET(14));
253PPC_EXC_MIN_ASSERT_OFFSET(V15, PPC_EXC_MIN_VR_OFFSET(15));
254PPC_EXC_MIN_ASSERT_OFFSET(V16, PPC_EXC_MIN_VR_OFFSET(16));
255PPC_EXC_MIN_ASSERT_OFFSET(V17, PPC_EXC_MIN_VR_OFFSET(17));
256PPC_EXC_MIN_ASSERT_OFFSET(V18, PPC_EXC_MIN_VR_OFFSET(18));
257PPC_EXC_MIN_ASSERT_OFFSET(V19, PPC_EXC_MIN_VR_OFFSET(19));
258#endif
259
260#ifdef PPC_MULTILIB_FPU
261RTEMS_STATIC_ASSERT(PPC_EXC_FR_OFFSET(0) % 8 == 0, PPC_EXC_FR_OFFSET);
262PPC_EXC_ASSERT_OFFSET(F0, PPC_EXC_FR_OFFSET(0));
263PPC_EXC_ASSERT_OFFSET(F1, PPC_EXC_FR_OFFSET(1));
264PPC_EXC_ASSERT_OFFSET(F2, PPC_EXC_FR_OFFSET(2));
265PPC_EXC_ASSERT_OFFSET(F3, PPC_EXC_FR_OFFSET(3));
266PPC_EXC_ASSERT_OFFSET(F4, PPC_EXC_FR_OFFSET(4));
267PPC_EXC_ASSERT_OFFSET(F5, PPC_EXC_FR_OFFSET(5));
268PPC_EXC_ASSERT_OFFSET(F6, PPC_EXC_FR_OFFSET(6));
269PPC_EXC_ASSERT_OFFSET(F7, PPC_EXC_FR_OFFSET(7));
270PPC_EXC_ASSERT_OFFSET(F8, PPC_EXC_FR_OFFSET(8));
271PPC_EXC_ASSERT_OFFSET(F9, PPC_EXC_FR_OFFSET(9));
272PPC_EXC_ASSERT_OFFSET(F10, PPC_EXC_FR_OFFSET(10));
273PPC_EXC_ASSERT_OFFSET(F11, PPC_EXC_FR_OFFSET(11));
274PPC_EXC_ASSERT_OFFSET(F12, PPC_EXC_FR_OFFSET(12));
275PPC_EXC_ASSERT_OFFSET(F13, PPC_EXC_FR_OFFSET(13));
276PPC_EXC_ASSERT_OFFSET(F14, PPC_EXC_FR_OFFSET(14));
277PPC_EXC_ASSERT_OFFSET(F15, PPC_EXC_FR_OFFSET(15));
278PPC_EXC_ASSERT_OFFSET(F16, PPC_EXC_FR_OFFSET(16));
279PPC_EXC_ASSERT_OFFSET(F17, PPC_EXC_FR_OFFSET(17));
280PPC_EXC_ASSERT_OFFSET(F18, PPC_EXC_FR_OFFSET(18));
281PPC_EXC_ASSERT_OFFSET(F19, PPC_EXC_FR_OFFSET(19));
282PPC_EXC_ASSERT_OFFSET(F20, PPC_EXC_FR_OFFSET(20));
283PPC_EXC_ASSERT_OFFSET(F21, PPC_EXC_FR_OFFSET(21));
284PPC_EXC_ASSERT_OFFSET(F22, PPC_EXC_FR_OFFSET(22));
285PPC_EXC_ASSERT_OFFSET(F23, PPC_EXC_FR_OFFSET(23));
286PPC_EXC_ASSERT_OFFSET(F24, PPC_EXC_FR_OFFSET(24));
287PPC_EXC_ASSERT_OFFSET(F25, PPC_EXC_FR_OFFSET(25));
288PPC_EXC_ASSERT_OFFSET(F26, PPC_EXC_FR_OFFSET(26));
289PPC_EXC_ASSERT_OFFSET(F27, PPC_EXC_FR_OFFSET(27));
290PPC_EXC_ASSERT_OFFSET(F28, PPC_EXC_FR_OFFSET(28));
291PPC_EXC_ASSERT_OFFSET(F29, PPC_EXC_FR_OFFSET(29));
292PPC_EXC_ASSERT_OFFSET(F30, PPC_EXC_FR_OFFSET(30));
293PPC_EXC_ASSERT_OFFSET(F31, PPC_EXC_FR_OFFSET(31));
294PPC_EXC_ASSERT_OFFSET(FPSCR, PPC_EXC_FPSCR_OFFSET);
295
296RTEMS_STATIC_ASSERT(PPC_EXC_MIN_FR_OFFSET(0) % 8 == 0, PPC_EXC_MIN_FR_OFFSET);
297PPC_EXC_MIN_ASSERT_OFFSET(F0, PPC_EXC_MIN_FR_OFFSET(0));
298PPC_EXC_MIN_ASSERT_OFFSET(F1, PPC_EXC_MIN_FR_OFFSET(1));
299PPC_EXC_MIN_ASSERT_OFFSET(F2, PPC_EXC_MIN_FR_OFFSET(2));
300PPC_EXC_MIN_ASSERT_OFFSET(F3, PPC_EXC_MIN_FR_OFFSET(3));
301PPC_EXC_MIN_ASSERT_OFFSET(F4, PPC_EXC_MIN_FR_OFFSET(4));
302PPC_EXC_MIN_ASSERT_OFFSET(F5, PPC_EXC_MIN_FR_OFFSET(5));
303PPC_EXC_MIN_ASSERT_OFFSET(F6, PPC_EXC_MIN_FR_OFFSET(6));
304PPC_EXC_MIN_ASSERT_OFFSET(F7, PPC_EXC_MIN_FR_OFFSET(7));
305PPC_EXC_MIN_ASSERT_OFFSET(F8, PPC_EXC_MIN_FR_OFFSET(8));
306PPC_EXC_MIN_ASSERT_OFFSET(F9, PPC_EXC_MIN_FR_OFFSET(9));
307PPC_EXC_MIN_ASSERT_OFFSET(F10, PPC_EXC_MIN_FR_OFFSET(10));
308PPC_EXC_MIN_ASSERT_OFFSET(F11, PPC_EXC_MIN_FR_OFFSET(11));
309PPC_EXC_MIN_ASSERT_OFFSET(F12, PPC_EXC_MIN_FR_OFFSET(12));
310PPC_EXC_MIN_ASSERT_OFFSET(F13, PPC_EXC_MIN_FR_OFFSET(13));
311PPC_EXC_MIN_ASSERT_OFFSET(FPSCR, PPC_EXC_MIN_FPSCR_OFFSET);
312#endif
313
314RTEMS_STATIC_ASSERT(
315  CPU_INTERRUPT_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
316  CPU_INTERRUPT_FRAME_SIZE
317);
318
319RTEMS_STATIC_ASSERT(
320  PPC_EXC_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
321  PPC_EXC_FRAME_SIZE
322);
323
324RTEMS_STATIC_ASSERT(
325  sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE,
326  CPU_Exception_frame
327);
328
329void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
330{
331  ppc_interrupt_disable();
332  __asm__ volatile (
333    "mr 3, %0\n"
334    "mr 4, %1\n"
335    "1:\n"
336    "b 1b\n"
337    : \
338    : "r" (source), "r" (error)
339    : "memory"
340  );
341}
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