source: rtems/cpukit/score/cpu/powerpc/cpu.c @ 1869bb7

4.115
Last change on this file since 1869bb7 was 1869bb7, checked in by Sebastian Huber <sebastian.huber@…>, on 05/18/12 at 13:47:23

powerpc: Simplify context switch

PowerPC cores with the SPE (Signal Processing Extension) have 64-bit
general-purpose registers. The SPE context switch code has been merged
with the standard context switch code. The context switch may use cache
operations to increase the performance. It will be ensured that the
context is 32-byte aligned (PPC_DEFAULT_CACHE_LINE_SIZE). This
increases the overall memory size of the context area in the thread
control block slightly. The general-purpose registers GPR2 and GPR13
are no longer part of the context. The BSP must initialize these
registers during startup (usually initialized by the eabi() function).

The new BSP option BSP_USE_DATA_CACHE_BLOCK_TOUCH can be used to enable
the dcbt instruction in the context switch.

The new BSP option BSP_USE_SYNC_IN_CONTEXT_SWITCH can be used to enable
sync and isync instructions in the context switch. This should be not
necessary in most cases.

  • Property mode set to 100644
File size: 1.4 KB
Line 
1/*
2 *  The license and distribution terms for this file may be
3 *  found in the file LICENSE in this distribution or at
4 *  http://www.rtems.com/license/LICENSE.
5 */
6
7/*
8 * For now, this file is just a stub to work around
9 * structural deficiencies of the powerpc port.
10 */
11
12#ifdef HAVE_CONFIG_H
13  #include "config.h"
14#endif
15
16#include <rtems/system.h>
17#include <rtems/score/cpu.h>
18
19#define PPC_ASSERT_OFFSET(field, off) \
20  RTEMS_STATIC_ASSERT( \
21    offsetof(ppc_context, field) + PPC_DEFAULT_CACHE_LINE_SIZE \
22      == PPC_CONTEXT_OFFSET_ ## off, \
23    ppc_context_offset_ ## field \
24  )
25
26PPC_ASSERT_OFFSET(gpr1, GPR1);
27PPC_ASSERT_OFFSET(msr, MSR);
28PPC_ASSERT_OFFSET(lr, LR);
29PPC_ASSERT_OFFSET(cr, CR);
30PPC_ASSERT_OFFSET(gpr14, GPR14);
31PPC_ASSERT_OFFSET(gpr15, GPR15);
32PPC_ASSERT_OFFSET(gpr16, GPR16);
33PPC_ASSERT_OFFSET(gpr17, GPR17);
34PPC_ASSERT_OFFSET(gpr18, GPR18);
35PPC_ASSERT_OFFSET(gpr19, GPR19);
36PPC_ASSERT_OFFSET(gpr20, GPR20);
37PPC_ASSERT_OFFSET(gpr21, GPR21);
38PPC_ASSERT_OFFSET(gpr22, GPR22);
39PPC_ASSERT_OFFSET(gpr23, GPR23);
40PPC_ASSERT_OFFSET(gpr24, GPR24);
41PPC_ASSERT_OFFSET(gpr25, GPR25);
42PPC_ASSERT_OFFSET(gpr26, GPR26);
43PPC_ASSERT_OFFSET(gpr27, GPR27);
44PPC_ASSERT_OFFSET(gpr28, GPR28);
45PPC_ASSERT_OFFSET(gpr29, GPR29);
46PPC_ASSERT_OFFSET(gpr30, GPR30);
47PPC_ASSERT_OFFSET(gpr31, GPR31);
48
49RTEMS_STATIC_ASSERT(
50  sizeof(Context_Control) % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
51  ppc_context_size
52);
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