source: rtems/cpukit/score/cpu/powerpc/cpu.c

Last change on this file was bcef89f2, checked in by Sebastian Huber <sebastian.huber@…>, on 05/19/23 at 06:18:25

Update company name

The embedded brains GmbH & Co. KG is the legal successor of embedded
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1/* SPDX-License-Identifier: BSD-2-Clause */
2
3/**
4 *  @file
5 *
6 *  @brief PowerPC Dependent Source
7 */
8
9/*
10 * Copyright (C) 2009, 2017 embedded brains GmbH & Co. KG
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 *    notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 *    notice, this list of conditions and the following disclaimer in the
19 *    documentation and/or other materials provided with the distribution.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 */
33
34/*
35 * For now, this file is just a stub to work around
36 * structural deficiencies of the powerpc port.
37 */
38
39#ifdef HAVE_CONFIG_H
40#include "config.h"
41#endif
42
43#include <rtems/score/cpuimpl.h>
44
45#define PPC_ASSERT_OFFSET(field, off) \
46  RTEMS_STATIC_ASSERT( \
47    offsetof(ppc_context, field) + PPC_DEFAULT_CACHE_LINE_SIZE \
48      == PPC_CONTEXT_OFFSET_ ## off, \
49    ppc_context_offset_ ## field \
50  )
51
52PPC_ASSERT_OFFSET(gpr1, GPR1);
53PPC_ASSERT_OFFSET(msr, MSR);
54PPC_ASSERT_OFFSET(lr, LR);
55PPC_ASSERT_OFFSET(cr, CR);
56PPC_ASSERT_OFFSET(gpr14, GPR14);
57PPC_ASSERT_OFFSET(gpr15, GPR15);
58PPC_ASSERT_OFFSET(gpr16, GPR16);
59PPC_ASSERT_OFFSET(gpr17, GPR17);
60PPC_ASSERT_OFFSET(gpr18, GPR18);
61PPC_ASSERT_OFFSET(gpr19, GPR19);
62PPC_ASSERT_OFFSET(gpr20, GPR20);
63PPC_ASSERT_OFFSET(gpr21, GPR21);
64PPC_ASSERT_OFFSET(gpr22, GPR22);
65PPC_ASSERT_OFFSET(gpr23, GPR23);
66PPC_ASSERT_OFFSET(gpr24, GPR24);
67PPC_ASSERT_OFFSET(gpr25, GPR25);
68PPC_ASSERT_OFFSET(gpr26, GPR26);
69PPC_ASSERT_OFFSET(gpr27, GPR27);
70PPC_ASSERT_OFFSET(gpr28, GPR28);
71PPC_ASSERT_OFFSET(gpr29, GPR29);
72PPC_ASSERT_OFFSET(gpr30, GPR30);
73PPC_ASSERT_OFFSET(gpr31, GPR31);
74PPC_ASSERT_OFFSET(tp, TP);
75PPC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE);
76
77#ifdef RTEMS_SMP
78  PPC_ASSERT_OFFSET(is_executing, IS_EXECUTING);
79#endif
80
81#ifdef PPC_MULTILIB_ALTIVEC
82  PPC_ASSERT_OFFSET(vrsave, VRSAVE);
83  PPC_ASSERT_OFFSET(vscr, VSCR);
84  RTEMS_STATIC_ASSERT(
85    PPC_CONTEXT_OFFSET_V20 % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
86    ppc_context_altivec
87  );
88  PPC_ASSERT_OFFSET(v20, V20);
89  PPC_ASSERT_OFFSET(v21, V21);
90  PPC_ASSERT_OFFSET(v22, V22);
91  PPC_ASSERT_OFFSET(v23, V23);
92  PPC_ASSERT_OFFSET(v24, V24);
93  PPC_ASSERT_OFFSET(v25, V25);
94  PPC_ASSERT_OFFSET(v26, V26);
95  PPC_ASSERT_OFFSET(v27, V27);
96  PPC_ASSERT_OFFSET(v28, V28);
97  PPC_ASSERT_OFFSET(v29, V29);
98  PPC_ASSERT_OFFSET(v30, V30);
99  PPC_ASSERT_OFFSET(v31, V31);
100#endif
101
102#ifdef PPC_MULTILIB_FPU
103  PPC_ASSERT_OFFSET(f14, F14);
104  PPC_ASSERT_OFFSET(f15, F15);
105  PPC_ASSERT_OFFSET(f16, F16);
106  PPC_ASSERT_OFFSET(f17, F17);
107  PPC_ASSERT_OFFSET(f18, F18);
108  PPC_ASSERT_OFFSET(f19, F19);
109  PPC_ASSERT_OFFSET(f20, F20);
110  PPC_ASSERT_OFFSET(f21, F21);
111  PPC_ASSERT_OFFSET(f22, F22);
112  PPC_ASSERT_OFFSET(f23, F23);
113  PPC_ASSERT_OFFSET(f24, F24);
114  PPC_ASSERT_OFFSET(f25, F25);
115  PPC_ASSERT_OFFSET(f26, F26);
116  PPC_ASSERT_OFFSET(f27, F27);
117  PPC_ASSERT_OFFSET(f28, F28);
118  PPC_ASSERT_OFFSET(f29, F29);
119  PPC_ASSERT_OFFSET(f30, F30);
120  PPC_ASSERT_OFFSET(f31, F31);
121#endif
122
123RTEMS_STATIC_ASSERT(
124  sizeof(Context_Control) % PPC_DEFAULT_CACHE_LINE_SIZE == 0,
125  ppc_context_size
126);
127
128#define PPC_EXC_ASSERT_OFFSET(field, off) \
129  RTEMS_STATIC_ASSERT( \
130    offsetof(CPU_Exception_frame, field) + FRAME_LINK_SPACE == off, \
131    CPU_Exception_frame_offset_ ## field \
132  )
133
134#define PPC_EXC_ASSERT_CANONIC_OFFSET(field) \
135  PPC_EXC_ASSERT_OFFSET(field, field ## _OFFSET)
136
137#define PPC_EXC_MIN_ASSERT_OFFSET(field, off) \
138  RTEMS_STATIC_ASSERT( \
139    offsetof(CPU_Interrupt_frame, field) == off, \
140    CPU_Interrupt_frame_offset_ ## field \
141  )
142
143#define PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(field) \
144  PPC_EXC_MIN_ASSERT_OFFSET(field, field ## _OFFSET)
145
146PPC_EXC_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
147PPC_EXC_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
148PPC_EXC_ASSERT_OFFSET(_EXC_number, EXCEPTION_NUMBER_OFFSET);
149PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CR);
150PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_CTR);
151PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_XER);
152PPC_EXC_ASSERT_CANONIC_OFFSET(EXC_LR);
153#ifdef __SPE__
154  PPC_EXC_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
155  PPC_EXC_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
156#endif
157PPC_EXC_ASSERT_CANONIC_OFFSET(GPR0);
158PPC_EXC_ASSERT_CANONIC_OFFSET(GPR1);
159PPC_EXC_ASSERT_CANONIC_OFFSET(GPR2);
160PPC_EXC_ASSERT_CANONIC_OFFSET(GPR3);
161PPC_EXC_ASSERT_CANONIC_OFFSET(GPR4);
162PPC_EXC_ASSERT_CANONIC_OFFSET(GPR5);
163PPC_EXC_ASSERT_CANONIC_OFFSET(GPR6);
164PPC_EXC_ASSERT_CANONIC_OFFSET(GPR7);
165PPC_EXC_ASSERT_CANONIC_OFFSET(GPR8);
166PPC_EXC_ASSERT_CANONIC_OFFSET(GPR9);
167PPC_EXC_ASSERT_CANONIC_OFFSET(GPR10);
168PPC_EXC_ASSERT_CANONIC_OFFSET(GPR11);
169PPC_EXC_ASSERT_CANONIC_OFFSET(GPR12);
170PPC_EXC_ASSERT_CANONIC_OFFSET(GPR13);
171PPC_EXC_ASSERT_CANONIC_OFFSET(GPR14);
172PPC_EXC_ASSERT_CANONIC_OFFSET(GPR15);
173PPC_EXC_ASSERT_CANONIC_OFFSET(GPR16);
174PPC_EXC_ASSERT_CANONIC_OFFSET(GPR17);
175PPC_EXC_ASSERT_CANONIC_OFFSET(GPR18);
176PPC_EXC_ASSERT_CANONIC_OFFSET(GPR19);
177PPC_EXC_ASSERT_CANONIC_OFFSET(GPR20);
178PPC_EXC_ASSERT_CANONIC_OFFSET(GPR21);
179PPC_EXC_ASSERT_CANONIC_OFFSET(GPR22);
180PPC_EXC_ASSERT_CANONIC_OFFSET(GPR23);
181PPC_EXC_ASSERT_CANONIC_OFFSET(GPR24);
182PPC_EXC_ASSERT_CANONIC_OFFSET(GPR25);
183PPC_EXC_ASSERT_CANONIC_OFFSET(GPR26);
184PPC_EXC_ASSERT_CANONIC_OFFSET(GPR27);
185PPC_EXC_ASSERT_CANONIC_OFFSET(GPR28);
186PPC_EXC_ASSERT_CANONIC_OFFSET(GPR29);
187PPC_EXC_ASSERT_CANONIC_OFFSET(GPR30);
188PPC_EXC_ASSERT_CANONIC_OFFSET(GPR31);
189
190PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR0, SRR0_FRAME_OFFSET);
191PPC_EXC_MIN_ASSERT_OFFSET(EXC_SRR1, SRR1_FRAME_OFFSET);
192PPC_EXC_MIN_ASSERT_OFFSET(
193  EXC_INTERRUPT_ENTRY_INSTANT,
194  PPC_EXC_INTERRUPT_ENTRY_INSTANT_OFFSET
195);
196PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CR);
197PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_CTR);
198PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_XER);
199PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(EXC_LR);
200PPC_EXC_MIN_ASSERT_OFFSET(EXC_INTERRUPT_FRAME, PPC_EXC_INTERRUPT_FRAME_OFFSET);
201#ifdef __SPE__
202  PPC_EXC_MIN_ASSERT_OFFSET(EXC_SPEFSCR, PPC_EXC_SPEFSCR_OFFSET);
203  PPC_EXC_MIN_ASSERT_OFFSET(EXC_ACC, PPC_EXC_ACC_OFFSET);
204#endif
205PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR0);
206PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR1);
207PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR2);
208PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR3);
209PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR4);
210PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR5);
211PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR6);
212PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR7);
213PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR8);
214PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR9);
215PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR10);
216PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR11);
217PPC_EXC_MIN_ASSERT_CANONIC_OFFSET(GPR12);
218
219#ifdef PPC_MULTILIB_ALTIVEC
220PPC_EXC_ASSERT_OFFSET(VSCR, PPC_EXC_VSCR_OFFSET);
221PPC_EXC_ASSERT_OFFSET(VRSAVE, PPC_EXC_VRSAVE_OFFSET);
222RTEMS_STATIC_ASSERT(PPC_EXC_VR_OFFSET(0) % 16 == 0, PPC_EXC_VR_OFFSET);
223PPC_EXC_ASSERT_OFFSET(V0, PPC_EXC_VR_OFFSET(0));
224PPC_EXC_ASSERT_OFFSET(V1, PPC_EXC_VR_OFFSET(1));
225PPC_EXC_ASSERT_OFFSET(V2, PPC_EXC_VR_OFFSET(2));
226PPC_EXC_ASSERT_OFFSET(V3, PPC_EXC_VR_OFFSET(3));
227PPC_EXC_ASSERT_OFFSET(V4, PPC_EXC_VR_OFFSET(4));
228PPC_EXC_ASSERT_OFFSET(V5, PPC_EXC_VR_OFFSET(5));
229PPC_EXC_ASSERT_OFFSET(V6, PPC_EXC_VR_OFFSET(6));
230PPC_EXC_ASSERT_OFFSET(V7, PPC_EXC_VR_OFFSET(7));
231PPC_EXC_ASSERT_OFFSET(V8, PPC_EXC_VR_OFFSET(8));
232PPC_EXC_ASSERT_OFFSET(V9, PPC_EXC_VR_OFFSET(9));
233PPC_EXC_ASSERT_OFFSET(V10, PPC_EXC_VR_OFFSET(10));
234PPC_EXC_ASSERT_OFFSET(V11, PPC_EXC_VR_OFFSET(11));
235PPC_EXC_ASSERT_OFFSET(V12, PPC_EXC_VR_OFFSET(12));
236PPC_EXC_ASSERT_OFFSET(V13, PPC_EXC_VR_OFFSET(13));
237PPC_EXC_ASSERT_OFFSET(V14, PPC_EXC_VR_OFFSET(14));
238PPC_EXC_ASSERT_OFFSET(V15, PPC_EXC_VR_OFFSET(15));
239PPC_EXC_ASSERT_OFFSET(V16, PPC_EXC_VR_OFFSET(16));
240PPC_EXC_ASSERT_OFFSET(V17, PPC_EXC_VR_OFFSET(17));
241PPC_EXC_ASSERT_OFFSET(V18, PPC_EXC_VR_OFFSET(18));
242PPC_EXC_ASSERT_OFFSET(V19, PPC_EXC_VR_OFFSET(19));
243PPC_EXC_ASSERT_OFFSET(V20, PPC_EXC_VR_OFFSET(20));
244PPC_EXC_ASSERT_OFFSET(V21, PPC_EXC_VR_OFFSET(21));
245PPC_EXC_ASSERT_OFFSET(V22, PPC_EXC_VR_OFFSET(22));
246PPC_EXC_ASSERT_OFFSET(V23, PPC_EXC_VR_OFFSET(23));
247PPC_EXC_ASSERT_OFFSET(V24, PPC_EXC_VR_OFFSET(24));
248PPC_EXC_ASSERT_OFFSET(V25, PPC_EXC_VR_OFFSET(25));
249PPC_EXC_ASSERT_OFFSET(V26, PPC_EXC_VR_OFFSET(26));
250PPC_EXC_ASSERT_OFFSET(V27, PPC_EXC_VR_OFFSET(27));
251PPC_EXC_ASSERT_OFFSET(V28, PPC_EXC_VR_OFFSET(28));
252PPC_EXC_ASSERT_OFFSET(V29, PPC_EXC_VR_OFFSET(29));
253PPC_EXC_ASSERT_OFFSET(V30, PPC_EXC_VR_OFFSET(30));
254PPC_EXC_ASSERT_OFFSET(V31, PPC_EXC_VR_OFFSET(31));
255
256PPC_EXC_MIN_ASSERT_OFFSET(VSCR, PPC_EXC_MIN_VSCR_OFFSET);
257RTEMS_STATIC_ASSERT(PPC_EXC_MIN_VR_OFFSET(0) % 16 == 0, PPC_EXC_MIN_VR_OFFSET);
258PPC_EXC_MIN_ASSERT_OFFSET(V0, PPC_EXC_MIN_VR_OFFSET(0));
259PPC_EXC_MIN_ASSERT_OFFSET(V1, PPC_EXC_MIN_VR_OFFSET(1));
260PPC_EXC_MIN_ASSERT_OFFSET(V2, PPC_EXC_MIN_VR_OFFSET(2));
261PPC_EXC_MIN_ASSERT_OFFSET(V3, PPC_EXC_MIN_VR_OFFSET(3));
262PPC_EXC_MIN_ASSERT_OFFSET(V4, PPC_EXC_MIN_VR_OFFSET(4));
263PPC_EXC_MIN_ASSERT_OFFSET(V5, PPC_EXC_MIN_VR_OFFSET(5));
264PPC_EXC_MIN_ASSERT_OFFSET(V6, PPC_EXC_MIN_VR_OFFSET(6));
265PPC_EXC_MIN_ASSERT_OFFSET(V7, PPC_EXC_MIN_VR_OFFSET(7));
266PPC_EXC_MIN_ASSERT_OFFSET(V8, PPC_EXC_MIN_VR_OFFSET(8));
267PPC_EXC_MIN_ASSERT_OFFSET(V9, PPC_EXC_MIN_VR_OFFSET(9));
268PPC_EXC_MIN_ASSERT_OFFSET(V10, PPC_EXC_MIN_VR_OFFSET(10));
269PPC_EXC_MIN_ASSERT_OFFSET(V11, PPC_EXC_MIN_VR_OFFSET(11));
270PPC_EXC_MIN_ASSERT_OFFSET(V12, PPC_EXC_MIN_VR_OFFSET(12));
271PPC_EXC_MIN_ASSERT_OFFSET(V13, PPC_EXC_MIN_VR_OFFSET(13));
272PPC_EXC_MIN_ASSERT_OFFSET(V14, PPC_EXC_MIN_VR_OFFSET(14));
273PPC_EXC_MIN_ASSERT_OFFSET(V15, PPC_EXC_MIN_VR_OFFSET(15));
274PPC_EXC_MIN_ASSERT_OFFSET(V16, PPC_EXC_MIN_VR_OFFSET(16));
275PPC_EXC_MIN_ASSERT_OFFSET(V17, PPC_EXC_MIN_VR_OFFSET(17));
276PPC_EXC_MIN_ASSERT_OFFSET(V18, PPC_EXC_MIN_VR_OFFSET(18));
277PPC_EXC_MIN_ASSERT_OFFSET(V19, PPC_EXC_MIN_VR_OFFSET(19));
278#endif
279
280#ifdef PPC_MULTILIB_FPU
281RTEMS_STATIC_ASSERT(PPC_EXC_FR_OFFSET(0) % 8 == 0, PPC_EXC_FR_OFFSET);
282PPC_EXC_ASSERT_OFFSET(F0, PPC_EXC_FR_OFFSET(0));
283PPC_EXC_ASSERT_OFFSET(F1, PPC_EXC_FR_OFFSET(1));
284PPC_EXC_ASSERT_OFFSET(F2, PPC_EXC_FR_OFFSET(2));
285PPC_EXC_ASSERT_OFFSET(F3, PPC_EXC_FR_OFFSET(3));
286PPC_EXC_ASSERT_OFFSET(F4, PPC_EXC_FR_OFFSET(4));
287PPC_EXC_ASSERT_OFFSET(F5, PPC_EXC_FR_OFFSET(5));
288PPC_EXC_ASSERT_OFFSET(F6, PPC_EXC_FR_OFFSET(6));
289PPC_EXC_ASSERT_OFFSET(F7, PPC_EXC_FR_OFFSET(7));
290PPC_EXC_ASSERT_OFFSET(F8, PPC_EXC_FR_OFFSET(8));
291PPC_EXC_ASSERT_OFFSET(F9, PPC_EXC_FR_OFFSET(9));
292PPC_EXC_ASSERT_OFFSET(F10, PPC_EXC_FR_OFFSET(10));
293PPC_EXC_ASSERT_OFFSET(F11, PPC_EXC_FR_OFFSET(11));
294PPC_EXC_ASSERT_OFFSET(F12, PPC_EXC_FR_OFFSET(12));
295PPC_EXC_ASSERT_OFFSET(F13, PPC_EXC_FR_OFFSET(13));
296PPC_EXC_ASSERT_OFFSET(F14, PPC_EXC_FR_OFFSET(14));
297PPC_EXC_ASSERT_OFFSET(F15, PPC_EXC_FR_OFFSET(15));
298PPC_EXC_ASSERT_OFFSET(F16, PPC_EXC_FR_OFFSET(16));
299PPC_EXC_ASSERT_OFFSET(F17, PPC_EXC_FR_OFFSET(17));
300PPC_EXC_ASSERT_OFFSET(F18, PPC_EXC_FR_OFFSET(18));
301PPC_EXC_ASSERT_OFFSET(F19, PPC_EXC_FR_OFFSET(19));
302PPC_EXC_ASSERT_OFFSET(F20, PPC_EXC_FR_OFFSET(20));
303PPC_EXC_ASSERT_OFFSET(F21, PPC_EXC_FR_OFFSET(21));
304PPC_EXC_ASSERT_OFFSET(F22, PPC_EXC_FR_OFFSET(22));
305PPC_EXC_ASSERT_OFFSET(F23, PPC_EXC_FR_OFFSET(23));
306PPC_EXC_ASSERT_OFFSET(F24, PPC_EXC_FR_OFFSET(24));
307PPC_EXC_ASSERT_OFFSET(F25, PPC_EXC_FR_OFFSET(25));
308PPC_EXC_ASSERT_OFFSET(F26, PPC_EXC_FR_OFFSET(26));
309PPC_EXC_ASSERT_OFFSET(F27, PPC_EXC_FR_OFFSET(27));
310PPC_EXC_ASSERT_OFFSET(F28, PPC_EXC_FR_OFFSET(28));
311PPC_EXC_ASSERT_OFFSET(F29, PPC_EXC_FR_OFFSET(29));
312PPC_EXC_ASSERT_OFFSET(F30, PPC_EXC_FR_OFFSET(30));
313PPC_EXC_ASSERT_OFFSET(F31, PPC_EXC_FR_OFFSET(31));
314PPC_EXC_ASSERT_OFFSET(FPSCR, PPC_EXC_FPSCR_OFFSET);
315
316RTEMS_STATIC_ASSERT(PPC_EXC_MIN_FR_OFFSET(0) % 8 == 0, PPC_EXC_MIN_FR_OFFSET);
317PPC_EXC_MIN_ASSERT_OFFSET(F0, PPC_EXC_MIN_FR_OFFSET(0));
318PPC_EXC_MIN_ASSERT_OFFSET(F1, PPC_EXC_MIN_FR_OFFSET(1));
319PPC_EXC_MIN_ASSERT_OFFSET(F2, PPC_EXC_MIN_FR_OFFSET(2));
320PPC_EXC_MIN_ASSERT_OFFSET(F3, PPC_EXC_MIN_FR_OFFSET(3));
321PPC_EXC_MIN_ASSERT_OFFSET(F4, PPC_EXC_MIN_FR_OFFSET(4));
322PPC_EXC_MIN_ASSERT_OFFSET(F5, PPC_EXC_MIN_FR_OFFSET(5));
323PPC_EXC_MIN_ASSERT_OFFSET(F6, PPC_EXC_MIN_FR_OFFSET(6));
324PPC_EXC_MIN_ASSERT_OFFSET(F7, PPC_EXC_MIN_FR_OFFSET(7));
325PPC_EXC_MIN_ASSERT_OFFSET(F8, PPC_EXC_MIN_FR_OFFSET(8));
326PPC_EXC_MIN_ASSERT_OFFSET(F9, PPC_EXC_MIN_FR_OFFSET(9));
327PPC_EXC_MIN_ASSERT_OFFSET(F10, PPC_EXC_MIN_FR_OFFSET(10));
328PPC_EXC_MIN_ASSERT_OFFSET(F11, PPC_EXC_MIN_FR_OFFSET(11));
329PPC_EXC_MIN_ASSERT_OFFSET(F12, PPC_EXC_MIN_FR_OFFSET(12));
330PPC_EXC_MIN_ASSERT_OFFSET(F13, PPC_EXC_MIN_FR_OFFSET(13));
331PPC_EXC_MIN_ASSERT_OFFSET(FPSCR, PPC_EXC_MIN_FPSCR_OFFSET);
332#endif
333
334RTEMS_STATIC_ASSERT(
335  CPU_INTERRUPT_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
336  CPU_INTERRUPT_FRAME_SIZE
337);
338
339RTEMS_STATIC_ASSERT(
340  PPC_EXC_FRAME_SIZE % CPU_STACK_ALIGNMENT == 0,
341  PPC_EXC_FRAME_SIZE
342);
343
344RTEMS_STATIC_ASSERT(
345  sizeof(CPU_Exception_frame) + FRAME_LINK_SPACE <= PPC_EXC_FRAME_SIZE,
346  CPU_Exception_frame
347);
348
349void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
350{
351  ppc_interrupt_disable();
352  __asm__ volatile (
353    "mr 3, %0\n"
354    "mr 4, %1\n"
355    "1:\n"
356    "b 1b\n"
357    : \
358    : "r" (source), "r" (error)
359    : "memory"
360  );
361  RTEMS_UNREACHABLE();
362}
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