source: rtems/cpukit/score/cpu/or32/cpu.c @ 42540ecd

4.104.114.84.95
Last change on this file since 42540ecd was 42540ecd, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 30, 2004 at 11:46:13 AM

2004-03-30 Ralf Corsepius <ralf_corsepius@…>

  • cpu.c, cpu_asm.c, rtems/score/cpu.h: Convert to using c99 fixed size types.
  • Property mode set to 100644
File size: 4.8 KB
Line 
1/*
2 *  Opencore Or1k CPU Dependent Source
3 *
4 *
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 *  This file adapted from no_bsp board library of the RTEMS distribution.
13 *  The body has been modified for the Bender Or1k implementation by
14 *  Chris Ziomkowski. <chris@asics.ws>
15 */
16
17#include <rtems/system.h>
18#include <rtems/score/isr.h>
19#include <rtems/score/wkspace.h>
20
21/*  _CPU_Initialize
22 *
23 *  This routine performs processor dependent initialization.
24 *
25 *  INPUT PARAMETERS:
26 *    cpu_table       - CPU table to initialize
27 *    thread_dispatch - address of disptaching routine
28 *
29 */
30
31
32void _CPU_Initialize(
33  rtems_cpu_table  *cpu_table,
34  void      (*thread_dispatch) 
35)
36{
37  /*
38   *  The thread_dispatch argument is the address of the entry point
39   *  for the routine called at the end of an ISR once it has been
40   *  decided a context switch is necessary.  On some compilation
41   *  systems it is difficult to call a high-level language routine
42   *  from assembly.  This allows us to trick these systems.
43   *
44   *  If you encounter this problem save the entry point in a CPU
45   *  dependent variable.
46   */
47
48  _CPU_Thread_dispatch_pointer = thread_dispatch;
49
50  /*
51   *  If there is not an easy way to initialize the FP context
52   *  during Context_Initialize, then it is usually easier to
53   *  save an "uninitialized" FP context here and copy it to
54   *  the task's during Context_Initialize.
55   */
56
57  /* FP context initialization support goes here */
58
59  _CPU_Table = *cpu_table;
60}
61
62/*PAGE
63 *
64 *  _CPU_ISR_Get_level
65 *
66 *  or1k Specific Information:
67 *
68 *  There are only 2 interrupt levels for the or1k architecture.
69 *  Either interrupts are enabled or disabled. They are considered
70 *  enabled if both exceptions are enabled (SR_EXR) and interrupts
71 *  are enabled (SR_EIR). If either of these conditions are not
72 *  met, interrupts are disabled, and a level of 1 is returned.
73 */
74
75inline uint32_t   _CPU_ISR_Get_level( void )
76{
77  register uint32_t   sr;
78  asm("l.mfspr %0,r0,0x17" : "=r" (sr));
79  return !((sr & SR_EXR) && (sr & SR_EIR));
80}
81
82/*PAGE
83 *
84 *  _CPU_ISR_install_raw_handler
85 *
86 *  or1k Specific Information:
87 *
88 *  As a general rule the following is done for interrupts:
89 * 
90 *  For normal exceptions, exceptions are immediately reenabled
91 *  by setting the SR_EXR bit. For interrupt exceptions, the
92 *  SR_EIR bit is first cleared, and then exceptions are reenabled.
93 */
94 
95void _CPU_ISR_install_raw_handler(
96  uint32_t    vector,
97  proc_ptr    new_handler,
98  proc_ptr   *old_handler
99)
100{
101  register uint32_t   sr;
102  register uint32_t   tmp;
103  extern uint32_t   Or1k_Interrupt_Vectors[];
104
105  asm volatile ("l.mfspr %0,r0,0x11\n\t"
106               "l.addi  %1,r0,-5\n\t"
107               "l.and   %1,%1,%0\n\t": "=r" (sr) : "r" (tmp));
108  *old_handler = *((proc_ptr*)&Or1k_Interrupt_Vectors[vector]);
109  *((proc_ptr*)&Or1k_Interrupt_Vectors[vector]) = new_handler;
110  asm volatile ("l.mtspr r0,%0,0x11\n\t":: "r" (sr));
111}
112
113/*PAGE
114 *
115 *  _CPU_ISR_install_vector
116 *
117 *  This kernel routine installs the RTEMS handler for the
118 *  specified vector.
119 *
120 *  Input parameters:
121 *    vector      - interrupt vector number
122 *    old_handler - former ISR for this vector number
123 *    new_handler - replacement ISR for this vector number
124 *
125 *  Output parameters:  NONE
126 *
127 *
128 *  NO_CPU Specific Information:
129 *
130 *  XXX document implementation including references if appropriate
131 */
132
133void _CPU_ISR_install_vector(
134  uint32_t    vector,
135  proc_ptr    new_handler,
136  proc_ptr   *old_handler
137)
138{
139   *old_handler = _ISR_Vector_table[ vector ];
140
141   /*
142    *  If the interrupt vector table is a table of pointer to isr entry
143    *  points, then we need to install the appropriate RTEMS interrupt
144    *  handler for this vector number.
145    */
146
147   _CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
148
149   /*
150    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
151    *  be used by the _ISR_Handler so the user gets control.
152    */
153
154    _ISR_Vector_table[ vector ] = new_handler;
155}
156
157/*PAGE
158 *
159 *  _CPU_Install_interrupt_stack
160 * 
161 *  We don't use a separate interrupt stack.
162 *
163 */
164
165void _CPU_Install_interrupt_stack( void )
166{
167}
168
169/*PAGE
170 *
171 *  _CPU_Thread_Idle_body
172 *
173 *  NOTES:
174 *
175 *  1. This is the same as the regular CPU independent algorithm.
176 *
177 *  2. If you implement this using a "halt", "idle", or "shutdown"
178 *     instruction, then don't forget to put it in an infinite loop.
179 *
180 *  3. Be warned. Some processors with onboard DMA have been known
181 *     to stop the DMA if the CPU were put in IDLE mode.  This might
182 *     also be a problem with other on-chip peripherals.  So use this
183 *     hook with caution.
184 *
185 */
186
187void _CPU_Thread_Idle_body( void )
188{
189
190  for( ; ; )
191    /* insert your "halt" instruction here */ ;
192}
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