source: rtems/cpukit/score/cpu/or1k/rtems/score/or1k-utility.h @ 94d45f6

4.115
Last change on this file since 94d45f6 was 94d45f6, checked in by Hesham ALMatary <heshamelmatary@…>, on Aug 12, 2014 at 3:57:42 PM

Add support for OpenRISC - Fixed issues

This work is based on the old or32 port (that has been
removed back in 2005) authored by Chris Ziomkowski. The patch includes the
basic functions every port should implement like: context switch, exception
handling, OpenRISC ABI and machine definitions and configurations.

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File size: 14.2 KB
Line 
1/**
2 * @file
3 *
4 * @brief OR1K utility
5 */
6/*
7 * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
8 *
9 * The license and distribution terms for this file may be
10 * found in the file LICENSE in this distribution or at
11 * http://www.rtems.org/license/LICENSE.
12 */
13
14#ifndef _RTEMS_SCORE_OR1K_UTILITY_H
15#define _RTEMS_SCORE_OR1K_UTILITY_H
16
17/* SPR groups definitions */
18#define SPR_GRP_SHAMT 11
19#define SPR_GRP0_SYS_CTRL  (0  << SPR_GRP_SHAMT)
20#define SPR_GRP1_DMMU      (1  << SPR_GRP_SHAMT)
21#define SPR_GRP2_IMMU      (2  << SPR_GRP_SHAMT)
22#define SPR_GRP3_DC        (3  << SPR_GRP_SHAMT)
23#define SPR_GRP4_IC        (4  << SPR_GRP_SHAMT)
24#define SPR_GRP5_MAC       (5  << SPR_GRP_SHAMT)
25#define SPR_GRP6_DEBUG     (6  << SPR_GRP_SHAMT)
26#define SPR_GRP7_PERF_CTR  (7  << SPR_GRP_SHAMT)
27#define SPR_GRP8_PWR_MNG   (8  << SPR_GRP_SHAMT)
28#define SPR_GRP9_PIC       (9  << SPR_GRP_SHAMT)
29#define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT)
30#define SPR_GPR11_FPU      (11 << SPR_GRP_SHAMT)
31
32/* SPR registers definitions */
33
34/* Group 0: System control registers */
35#define CPU_OR1K_SPR_VR       (SPR_GRP0_SYS_CTRL + 0)
36#define CPU_OR1K_SPR_UPR      (SPR_GRP0_SYS_CTRL + 1)
37#define CPU_OR1K_SPR_CPUCFGR  (SPR_GRP0_SYS_CTRL + 2)
38#define CPU_OR1K_SPR_DMMUCFGR (SPR_GRP0_SYS_CTRL + 3)
39#define CPU_OR1K_SPR_IMMUCFGR (SPR_GRP0_SYS_CTRL + 4)
40#define CPU_OR1K_SPR_DCCFGR   (SPR_GRP0_SYS_CTRL + 5)
41#define CPU_OR1K_SPR_ICCFGR   (SPR_GRP0_SYS_CTRL + 6)
42#define CPU_OR1K_SPR_DCFGR    (SPR_GRP0_SYS_CTRL + 7)
43#define CPU_OR1K_SPR_PCCFGR   (SPR_GRP0_SYS_CTRL + 8)
44#define CPU_OR1K_SPR_VR2      (SPR_GRP0_SYS_CTRL + 9)
45#define CPU_OR1K_SPR_AVR      (SPR_GRP0_SYS_CTRL + 10)
46#define CPU_OR1K_SPR_EVBAR    (SPR_GRP0_SYS_CTRL + 11)
47#define CPU_OR1K_SPR_AECR     (SPR_GRP0_SYS_CTRL + 12)
48#define CPU_OR1K_SPR_AESR     (SPR_GRP0_SYS_CTRL + 13)
49#define CPU_OR1K_SPR_NPC      (SPR_GRP0_SYS_CTRL + 16)
50#define CPU_OR1K_SPR_SR       (SPR_GRP0_SYS_CTRL + 17)
51#define CPU_OR1K_SPR_PPC      (SPR_GRP0_SYS_CTRL + 18)
52#define CPU_OR1K_SPR_FPCSR    (SPR_GRP0_SYS_CTRL + 20)
53#define CPU_OR1K_SPR_EPCR0    (SPR_GRP0_SYS_CTRL + 32)
54#define CPU_OR1K_SPR_EPCR1    (SPR_GRP0_SYS_CTRL + 33)
55#define CPU_OR1K_SPR_EPCR2    (SPR_GRP0_SYS_CTRL + 34)
56#define CPU_OR1K_SPR_EPCR3    (SPR_GRP0_SYS_CTRL + 35)
57#define CPU_OR1K_SPR_EPCR4    (SPR_GRP0_SYS_CTRL + 36)
58#define CPU_OR1K_SPR_EPCR5    (SPR_GRP0_SYS_CTRL + 37)
59#define CPU_OR1K_SPR_EPCR6    (SPR_GRP0_SYS_CTRL + 38)
60#define CPU_OR1K_SPR_EPCR7    (SPR_GRP0_SYS_CTRL + 39)
61#define CPU_OR1K_SPR_EPCR8    (SPR_GRP0_SYS_CTRL + 40)
62#define CPU_OR1K_SPR_EPCR9    (SPR_GRP0_SYS_CTRL + 41)
63#define CPU_OR1K_SPR_EPCR10   (SPR_GRP0_SYS_CTRL + 42)
64#define CPU_OR1K_SPR_EPCR11   (SPR_GRP0_SYS_CTRL + 43)
65#define CPU_OR1K_SPR_EPCR12   (SPR_GRP0_SYS_CTRL + 44)
66#define CPU_OR1K_SPR_EPCR13   (SPR_GRP0_SYS_CTRL + 45)
67#define CPU_OR1K_SPR_EPCR14   (SPR_GRP0_SYS_CTRL + 46)
68#define CPU_OR1K_SPR_EPCR15   (SPR_GRP0_SYS_CTRL + 47)
69#define CPU_OR1K_SPR_EEAR0    (SPR_GRP0_SYS_CTRL + 48)
70#define CPU_OR1K_SPR_EEAR1    (SPR_GRP0_SYS_CTRL + 49)
71#define CPU_OR1K_SPR_EEAR2    (SPR_GRP0_SYS_CTRL + 50)
72#define CPU_OR1K_SPR_EEAR3    (SPR_GRP0_SYS_CTRL + 51)
73#define CPU_OR1K_SPR_EEAR4    (SPR_GRP0_SYS_CTRL + 52)
74#define CPU_OR1K_SPR_EEAR5    (SPR_GRP0_SYS_CTRL + 53)
75#define CPU_OR1K_SPR_EEAR6    (SPR_GRP0_SYS_CTRL + 54)
76#define CPU_OR1K_SPR_EEAR7    (SPR_GRP0_SYS_CTRL + 55)
77#define CPU_OR1K_SPR_EEAR8    (SPR_GRP0_SYS_CTRL + 56)
78#define CPU_OR1K_SPR_EEAR9    (SPR_GRP0_SYS_CTRL + 57)
79#define CPU_OR1K_SPR_EEAR10   (SPR_GRP0_SYS_CTRL + 58)
80#define CPU_OR1K_SPR_EEAR11   (SPR_GRP0_SYS_CTRL + 59)
81#define CPU_OR1K_SPR_EEAR12   (SPR_GRP0_SYS_CTRL + 60)
82#define CPU_OR1K_SPR_EEAR13   (SPR_GRP0_SYS_CTRL + 61)
83#define CPU_OR1K_SPR_EEAR14   (SPR_GRP0_SYS_CTRL + 62)
84#define CPU_OR1K_SPR_EEAR15   (SPR_GRP0_SYS_CTRL + 63)
85#define CPU_OR1K_SPR_ESR0     (SPR_GRP0_SYS_CTRL + 64)
86#define CPU_OR1K_SPR_ESR1     (SPR_GRP0_SYS_CTRL + 65)
87#define CPU_OR1K_SPR_ESR2     (SPR_GRP0_SYS_CTRL + 66)
88#define CPU_OR1K_SPR_ESR3     (SPR_GRP0_SYS_CTRL + 67)
89#define CPU_OR1K_SPR_ESR4     (SPR_GRP0_SYS_CTRL + 68)
90#define CPU_OR1K_SPR_ESR5     (SPR_GRP0_SYS_CTRL + 69)
91#define CPU_OR1K_SPR_ESR6     (SPR_GRP0_SYS_CTRL + 70)
92#define CPU_OR1K_SPR_ESR7     (SPR_GRP0_SYS_CTRL + 71)
93#define CPU_OR1K_SPR_ESR8     (SPR_GRP0_SYS_CTRL + 72)
94#define CPU_OR1K_SPR_ESR9     (SPR_GRP0_SYS_CTRL + 73)
95#define CPU_OR1K_SPR_ESR10    (SPR_GRP0_SYS_CTRL + 74)
96#define CPU_OR1K_SPR_ESR11    (SPR_GRP0_SYS_CTRL + 75)
97#define CPU_OR1K_SPR_ESR12    (SPR_GRP0_SYS_CTRL + 76)
98#define CPU_OR1K_SPR_ESR13    (SPR_GRP0_SYS_CTRL + 77)
99#define CPU_OR1K_SPR_ESR14    (SPR_GRP0_SYS_CTRL + 78)
100#define CPU_OR1K_SPR_ESR15    (SPR_GRP0_SYS_CTRL + 79)
101
102/* Shadow registers base */
103#define CPU_OR1K_SPR_GPR32    (SPR_GRP0_SYS_CTRL + 1024)
104
105/* Group1: Data MMU registers */
106#define CPU_OR1K_SPR_DMMUCR   (SPR_GRP1_DMMU + 0)
107#define CPU_OR1K_SPR_DMMUPR   (SPR_GRP1_DMMU + 1)
108#define CPU_OR1K_SPR_DTLBEIR  (SPR_GRP1_DMMU + 2)
109#define CPU_OR1K_SPR_DATBMR0  (SPR_GRP1_DMMU + 4)
110#define CPU_OR1K_SPR_DATBMR1  (SPR_GRP1_DMMU + 5)
111#define CPU_OR1K_SPR_DATBMR2  (SPR_GRP1_DMMU + 6)
112#define CPU_OR1K_SPR_DATBMR3  (SPR_GRP1_DMMU + 7)
113#define CPU_OR1K_SPR_DATBTR0  (SPR_GRP1_DMMU + 8)
114#define CPU_OR1K_SPR_DATBTR1  (SPR_GRP1_DMMU + 9)
115#define CPU_OR1K_SPR_DATBTR2  (SPR_GRP1_DMMU + 10)
116#define CPU_OR1K_SPR_DATBTR3  (SPR_GRP1_DMMU + 11)
117
118/* Group2: Instruction MMU registers */
119#define CPU_OR1K_SPR_IMMUCR   (SPR_GRP2_IMMU + 0)
120#define CPU_OR1K_SPR_IMMUPR   (SPR_GRP2_IMMU + 1)
121#define CPU_OR1K_SPR_ITLBEIR  (SPR_GRP2_IMMU + 2)
122#define CPU_OR1K_SPR_IATBMR0  (SPR_GRP2_IMMU + 4)
123#define CPU_OR1K_SPR_IATBMR1  (SPR_GRP2_IMMU + 5)
124#define CPU_OR1K_SPR_IATBMR2  (SPR_GRP2_IMMU + 6)
125#define CPU_OR1K_SPR_IATBMR3  (SPR_GRP2_IMMU + 7)
126#define CPU_OR1K_SPR_IATBTR0  (SPR_GRP2_IMMU + 8)
127#define CPU_OR1K_SPR_IATBTR1  (SPR_GRP2_IMMU + 9)
128#define CPU_OR1K_SPR_IATBTR2  (SPR_GRP2_IMMU + 10)
129#define CPU_OR1K_SPR_IATBTR3  (SPR_GRP2_IMMU + 11)
130
131/* Group3: Data Cache registers */
132#define CPU_OR1K_SPR_DCCR   (SPR_GRP3_DC + 0)
133#define CPU_OR1K_SPR_DCBPR  (SPR_GRP3_DC + 1)
134#define CPU_OR1K_SPR_DCBFR  (SPR_GRP3_DC + 2)
135#define CPU_OR1K_SPR_DCBIR  (SPR_GRP3_DC + 3)
136#define CPU_OR1K_SPR_DCBWR  (SPR_GRP3_DC + 4)
137#define CPU_OR1K_SPR_DCBLR  (SPR_GRP3_DC + 5)
138
139/* Group4: Instruction Cache registers */
140#define CPU_OR1K_SPR_ICCR   (SPR_GRP4_IC + 0)
141#define CPU_OR1K_SPR_ICBPR  (SPR_GRP4_IC + 1)
142#define CPU_OR1K_SPR_ICBIR  (SPR_GRP4_IC + 2)
143#define CPU_OR1K_SPR_ICBLR  (SPR_GRP4_IC + 3)
144
145/* Group5: MAC registers */
146#define CPU_OR1K_SPR_MACLO  (SPR_GRP5_MAC + 1)
147#define CPU_OR1K_SPR_MACHI  (SPR_GRP5_MAC + 2)
148
149/* Group6: Debug registers */
150#define CPU_OR1K_SPR_DVR0   (SPR_GRP6_DEBUG + 0)
151#define CPU_OR1K_SPR_DVR1   (SPR_GRP6_DEBUG + 1)
152#define CPU_OR1K_SPR_DVR2   (SPR_GRP6_DEBUG + 2)
153#define CPU_OR1K_SPR_DVR3   (SPR_GRP6_DEBUG + 3)
154#define CPU_OR1K_SPR_DVR4   (SPR_GRP6_DEBUG + 4)
155#define CPU_OR1K_SPR_DVR5   (SPR_GRP6_DEBUG + 5)
156#define CPU_OR1K_SPR_DVR6   (SPR_GRP6_DEBUG + 6)
157#define CPU_OR1K_SPR_DVR7   (SPR_GRP6_DEBUG + 7)
158#define CPU_OR1K_SPR_DCR0   (SPR_GRP6_DEBUG + 8)
159#define CPU_OR1K_SPR_DCR1   (SPR_GRP6_DEBUG + 9)
160#define CPU_OR1K_SPR_DCR2   (SPR_GRP6_DEBUG + 10)
161#define CPU_OR1K_SPR_DCR3   (SPR_GRP6_DEBUG + 11)
162#define CPU_OR1K_SPR_DCR4   (SPR_GRP6_DEBUG + 12)
163#define CPU_OR1K_SPR_DCR5   (SPR_GRP6_DEBUG + 13)
164#define CPU_OR1K_SPR_DCR6   (SPR_GRP6_DEBUG + 14)
165#define CPU_OR1K_SPR_DCR7   (SPR_GRP6_DEBUG + 15)
166#define CPU_OR1K_SPR_DMR1   (SPR_GRP6_DEBUG + 16)
167#define CPU_OR1K_SPR_DMR2   (SPR_GRP6_DEBUG + 17)
168#define CPU_OR1K_SPR_DCWR0  (SPR_GRP6_DEBUG + 18)
169#define CPU_OR1K_SPR_DCWR1  (SPR_GRP6_DEBUG + 19)
170#define CPU_OR1K_SPR_DSR    (SPR_GRP6_DEBUG + 20)
171#define CPU_OR1K_SPR_DRR    (SPR_GRP6_DEBUG + 21)
172
173/* Group7: Performance counters registers */
174#define CPU_OR1K_SPR_PCCR0  (SPR_GRP7_PERF_CTR + 0)
175#define CPU_OR1K_SPR_PCCR1  (SPR_GRP7_PERF_CTR + 1)
176#define CPU_OR1K_SPR_PCCR2  (SPR_GRP7_PERF_CTR + 2)
177#define CPU_OR1K_SPR_PCCR3  (SPR_GRP7_PERF_CTR + 3)
178#define CPU_OR1K_SPR_PCCR4  (SPR_GRP7_PERF_CTR + 4)
179#define CPU_OR1K_SPR_PCCR5  (SPR_GRP7_PERF_CTR + 5)
180#define CPU_OR1K_SPR_PCCR6  (SPR_GRP7_PERF_CTR + 6)
181#define CPU_OR1K_SPR_PCCR7  (SPR_GRP7_PERF_CTR + 7)
182#define CPU_OR1K_SPR_PCMR0  (SPR_GRP7_PERF_CTR + 8)
183#define CPU_OR1K_SPR_PCMR1  (SPR_GRP7_PERF_CTR + 9)
184#define CPU_OR1K_SPR_PCMR2  (SPR_GRP7_PERF_CTR + 10)
185#define CPU_OR1K_SPR_PCMR3  (SPR_GRP7_PERF_CTR + 11)
186#define CPU_OR1K_SPR_PCMR4  (SPR_GRP7_PERF_CTR + 12)
187#define CPU_OR1K_SPR_PCMR5  (SPR_GRP7_PERF_CTR + 13)
188#define CPU_OR1K_SPR_PCMR6  (SPR_GRP7_PERF_CTR + 14)
189#define CPU_OR1K_SPR_PCMR7  (SPR_GRP7_PERF_CTR + 15)
190
191/* Group8: Power management register */
192#define CPU_OR1K_SPR_PMR    (SPR_GRP8_PWR_MNG + 0)
193
194/* Group9: PIC registers */
195#define CPU_OR1K_SPR_PICMR  (SPR_GRP9_PIC + 0)
196#define CPU_OR1K_SPR_PICSR  (SPR_GRP9_PIC + 2)
197
198/* Group10: Tick Timer registers */
199#define CPU_OR1K_SPR_TTMR   (SPR_GPR10_TICK_TMR + 0)
200#define CPU_OR1K_SPR_TTCR   (SPR_GPR10_TICK_TMR + 1)
201
202 /* Shift amount macros for bits position in Supervision Register */
203#define CPU_OR1K_SPR_SR_SHAMT_SM     (0)
204#define CPU_OR1K_SPR_SR_SHAMT_TEE    (1)
205#define CPU_OR1K_SPR_SR_SHAMT_IEE    (2)
206#define CPU_OR1K_SPR_SR_SHAMT_DCE    (3)
207#define CPU_OR1K_SPR_SR_SHAMT_ICE    (4)
208#define CPU_OR1K_SPR_SR_SHAMT_DME    (5)
209#define CPU_OR1K_SPR_SR_SHAMT_IME    (6)
210#define CPU_OR1K_SPR_SR_SHAMT_LEE    (7)
211#define CPU_OR1K_SPR_SR_SHAMT_CE     (8)
212#define CPU_OR1K_SPR_SR_SHAMT_F      (9)
213#define CPU_OR1K_SPR_SR_SHAMT_CY     (10)
214#define CPU_OR1K_SPR_SR_SHAMT_OV     (11)
215#define CPU_OR1K_SPR_SR_SHAMT_OVE    (12)
216#define CPU_OR1K_SPR_SR_SHAMT_DSX    (13)
217#define CPU_OR1K_SPR_SR_SHAMT_EPH    (14)
218#define CPU_OR1K_SPR_SR_SHAMT_FO     (15)
219#define CPU_OR1K_SPR_SR_SHAMT_SUMRA  (16)
220#define CPU_OR1K_SPR_SR_SHAMT_CID    (28)
221
222/* Supervision Mode Register. @see OpenRISC architecture manual*/
223
224 /* Supervisor Mode */
225#define CPU_OR1K_SPR_SR_SM    (1 << CPU_OR1K_SPR_SR_SHAMT_SM)
226/* Tick Timer Exception Enabled */
227#define CPU_OR1K_SPR_SR_TEE   (1 << CPU_OR1K_SPR_SR_SHAMT_TEE)
228/* Interrupt Exception Enabled */
229#define CPU_OR1K_SPR_SR_IEE   (1 << CPU_OR1K_SPR_SR_SHAMT_IEE)
230/* Data Cache Enable */
231#define CPU_OR1K_SPR_SR_DCE   (1 << CPU_OR1K_SPR_SR_SHAMT_DCE)
232/* Instruction Cache Enable */
233#define CPU_OR1K_SPR_SR_ICE   (1 << CPU_OR1K_SPR_SR_SHAMT_ICE)
234/* Data MMU Enable */
235#define CPU_OR1K_SPR_SR_DME   (1 << CPU_OR1K_SPR_SR_SHAMT_DME)
236/* Instruction MMU Enable */
237#define CPU_OR1K_SPR_SR_IME   (1 << CPU_OR1K_SPR_SR_SHAMT_IME)
238/* Little Endian Enable */
239#define CPU_OR1K_SPR_SR_LEE   (1 << CPU_OR1K_SPR_SR_SHAMT_LEE)
240/* CID Enable */
241#define CPU_OR1K_SPR_SR_CE    (1 << CPU_OR1K_SPR_SR_SHAMT_CE)
242/* Conditional branch flag */
243#define CPU_OR1K_SPR_SR_F     (1 << CPU_OR1K_SPR_SR_SHAMT_F)
244/* Carry flag */
245#define CPU_OR1K_SPR_SR_CY    (1 << CPU_OR1K_SPR_SR_SHAMT_CY)
246/* Overflow flag */
247#define CPU_OR1K_SPR_SR_OV    (1 << CPU_OR1K_SPR_SR_SHAMT_OV)
248/* Overflow flag Exception */
249#define CPU_OR1K_SPR_SR_OVE   (1 << CPU_OR1K_SPR_SR_SHAMT_OVE)
250/* Delay Slot Exception */
251#define CPU_OR1K_SPR_SR_DSX   (1 << CPU_OR1K_SPR_SR_SHAMT_DSX)
252 /* Exception Prefix High */
253#define CPU_OR1K_SPR_SR_EPH   (1 << CPU_OR1K_SPR_SR_SHAMT_EPH)
254/* Fixed One */
255#define CPU_OR1K_SPR_SR_FO    (1 << CPU_OR1K_SPR_SR_SHAMT_FO)
256/* SPRs User Mode Read Access */
257#define CPU_OR1K_SPR_SR_SUMRA (1 << CPU_OR1K_SPR_SR_SHAMT_SUMRA)
258/*Context ID (Fast Context Switching) */
259#define CPU_OR1K_SPR_SR_CID   (F << CPU_OR1K_SPR_SR_SHAMT_CID)
260
261/* Power management register bits */
262#define CPU_OR1K_SPR_PMR_SHAMT_SDF  0
263#define CPU_OR1K_SPR_PMR_SHAMT_DME  4
264#define CPU_OR1K_SPR_PMR_SHAMT_SME  5
265#define CPU_OR1K_SPR_PMR_SHAMT_DCGE 6
266#define CPU_OR1K_SPR_PMR_SHAMT_SUME 7
267
268#define CPU_OR1K_SPR_PMR_SDF  (0xF << CPU_OR1K_SPR_PMR_SHAMT_SDF)
269#define CPU_OR1K_SPR_PMR_DME  (1 << CPU_OR1K_SPR_PMR_SHAMT_DME)
270#define CPU_OR1K_SPR_PMR_SME  (1 << CPU_OR1K_SPR_PMR_SHAMT_SME)
271#define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE)
272#define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME)
273
274/* Shift amount macros for bit positions in Power Management register */
275
276#ifndef ASM
277
278#include <stddef.h>
279#include <stdint.h>
280#include <stdbool.h>
281
282#ifdef __cplusplus
283extern "C" {
284#endif /* __cplusplus */
285
286/**
287 * @brief Supervision Mode registers definitions.
288 *
289 * @see OpenRISC architecture manual - revision 0.
290 */
291typedef enum {
292  OR1K_EXCEPTION_RESET = 1,
293  OR1K_EXCEPTION_BUS_ERR = 2,
294  OR1K_EXCEPTION_D_PF = 3, /* Data Page Fault */
295  OR1K_EXCEPTION_I_PF = 4, /* Instruction Page Fault */
296  OR1K_EXCEPTION_TICK_TIMER = 5,
297  OR1K_EXCEPTION_ALIGNMENT = 6,
298  OR1K_EXCEPTION_I_UNDEF= 7, /* Undefiend instruction */
299  OR1K_EXCEPTION_IRQ = 8, /* External interrupt */
300  OR1K_EXCPETION_D_TLB = 9, /* Data TLB miss */
301  OR1K_EXCPETION_I_TLB = 10, /* Instruction TLB miss */
302  OR1K_EXCPETION_RANGE = 11, /* Range exception */
303  OR1K_EXCPETION_SYS_CALL = 12,
304  OR1K_EXCPETION_FP = 13, /* Floating point exception */
305  OR1K_EXCPETION_TRAP = 14, /* Caused by l.trap instruction or by debug unit */
306  OR1K_EXCPETION_RESERVED1 = 15,
307  OR1K_EXCPETION_RESERVED2 = 16,
308  OR1K_EXCPETION_RESERVED3 = 17,
309  MAX_EXCEPTIONS = 17,
310  OR1K_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
311} OR1K_Symbolic_exception_name;
312
313static inline uint32_t _OR1K_mfspr(uint32_t reg)
314{
315   uint32_t spr_value;
316
317   asm volatile (
318     "l.mfspr  %0, %1, 0;\n\t"
319     : "=r" (spr_value) : "r" (reg));
320
321   return spr_value;
322}
323
324static inline void _OR1K_mtspr(uint32_t reg, uint32_t value)
325{
326   asm volatile (
327     "l.mtspr  %1, %0, 0;\n\t"
328     :: "r" (value), "r" (reg)
329   );
330}
331
332/**
333 * @brief The slow down feature takes advantage of the low-power
334 * dividers in external clock generation circuitry to enable full
335 * functionality, but at a lower frequency so that power consumption
336 * is reduced. @see OpenRISC architecture manual, power management section.
337 *
338 * @param[in] value is 4 bit value to be written in PMR[SDF].
339 * A lower value specifies higher expected performance from the processor core.
340 *
341 */
342#define _OR1K_CPU_SlowDown(value) \
343   _OR1K_mtspr(CPU_OR1K_SPR_PMR, (value & CPU_OR1K_SPR_PMR_SDF))
344
345
346#define _OR1K_CPU_Doze() \
347  _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_DME)
348
349
350#define _OR1K_CPU_Sleep() \
351   _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME)
352
353
354#define _OR1K_CPU_Suspend() \
355   _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME)
356
357static inline void _OR1K_Sync_mem( void )
358{
359  asm volatile("l.msync");
360}
361
362static inline void _OR1K_Sync_pipeline( void )
363{
364  asm volatile("l.psync");
365}
366
367#else /* ASM */
368
369#endif /* ASM */
370
371#endif /* _RTEMS_SCORE_OR1K_UTILITY_H */
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