1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief OR1K utility |
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5 | */ |
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6 | /* |
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7 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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8 | * |
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9 | * The license and distribution terms for this file may be |
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10 | * found in the file LICENSE in this distribution or at |
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11 | * http://www.rtems.org/license/LICENSE. |
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12 | */ |
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13 | |
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14 | #ifndef _RTEMS_SCORE_OR1K_UTILITY_H |
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15 | #define _RTEMS_SCORE_OR1K_UTILITY_H |
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16 | |
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17 | /* SPR groups definitions */ |
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18 | #define SPR_GRP_SHAMT 11 |
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19 | #define SPR_GRP0_SYS_CTRL (0 << SPR_GRP_SHAMT) |
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20 | #define SPR_GRP1_DMMU (1 << SPR_GRP_SHAMT) |
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21 | #define SPR_GRP2_IMMU (2 << SPR_GRP_SHAMT) |
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22 | #define SPR_GRP3_DC (3 << SPR_GRP_SHAMT) |
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23 | #define SPR_GRP4_IC (4 << SPR_GRP_SHAMT) |
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24 | #define SPR_GRP5_MAC (5 << SPR_GRP_SHAMT) |
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25 | #define SPR_GRP6_DEBUG (6 << SPR_GRP_SHAMT) |
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26 | #define SPR_GRP7_PERF_CTR (7 << SPR_GRP_SHAMT) |
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27 | #define SPR_GRP8_PWR_MNG (8 << SPR_GRP_SHAMT) |
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28 | #define SPR_GRP9_PIC (9 << SPR_GRP_SHAMT) |
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29 | #define SPR_GPR10_TICK_TMR (10 << SPR_GRP_SHAMT) |
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30 | #define SPR_GPR11_FPU (11 << SPR_GRP_SHAMT) |
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31 | |
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32 | /* SPR registers definitions */ |
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33 | |
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34 | /* Group 0: System control registers */ |
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35 | #define CPU_OR1K_SPR_VR (SPR_GRP0_SYS_CTRL + 0) |
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36 | #define CPU_OR1K_SPR_UPR (SPR_GRP0_SYS_CTRL + 1) |
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37 | #define CPU_OR1K_SPR_CPUCFGR (SPR_GRP0_SYS_CTRL + 2) |
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38 | #define CPU_OR1K_SPR_DMMUCFGR (SPR_GRP0_SYS_CTRL + 3) |
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39 | #define CPU_OR1K_SPR_IMMUCFGR (SPR_GRP0_SYS_CTRL + 4) |
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40 | #define CPU_OR1K_SPR_DCCFGR (SPR_GRP0_SYS_CTRL + 5) |
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41 | #define CPU_OR1K_SPR_ICCFGR (SPR_GRP0_SYS_CTRL + 6) |
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42 | #define CPU_OR1K_SPR_DCFGR (SPR_GRP0_SYS_CTRL + 7) |
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43 | #define CPU_OR1K_SPR_PCCFGR (SPR_GRP0_SYS_CTRL + 8) |
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44 | #define CPU_OR1K_SPR_VR2 (SPR_GRP0_SYS_CTRL + 9) |
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45 | #define CPU_OR1K_SPR_AVR (SPR_GRP0_SYS_CTRL + 10) |
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46 | #define CPU_OR1K_SPR_EVBAR (SPR_GRP0_SYS_CTRL + 11) |
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47 | #define CPU_OR1K_SPR_AECR (SPR_GRP0_SYS_CTRL + 12) |
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48 | #define CPU_OR1K_SPR_AESR (SPR_GRP0_SYS_CTRL + 13) |
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49 | #define CPU_OR1K_SPR_NPC (SPR_GRP0_SYS_CTRL + 16) |
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50 | #define CPU_OR1K_SPR_SR (SPR_GRP0_SYS_CTRL + 17) |
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51 | #define CPU_OR1K_SPR_PPC (SPR_GRP0_SYS_CTRL + 18) |
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52 | #define CPU_OR1K_SPR_FPCSR (SPR_GRP0_SYS_CTRL + 20) |
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53 | #define CPU_OR1K_SPR_EPCR0 (SPR_GRP0_SYS_CTRL + 32) |
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54 | #define CPU_OR1K_SPR_EPCR1 (SPR_GRP0_SYS_CTRL + 33) |
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55 | #define CPU_OR1K_SPR_EPCR2 (SPR_GRP0_SYS_CTRL + 34) |
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56 | #define CPU_OR1K_SPR_EPCR3 (SPR_GRP0_SYS_CTRL + 35) |
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57 | #define CPU_OR1K_SPR_EPCR4 (SPR_GRP0_SYS_CTRL + 36) |
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58 | #define CPU_OR1K_SPR_EPCR5 (SPR_GRP0_SYS_CTRL + 37) |
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59 | #define CPU_OR1K_SPR_EPCR6 (SPR_GRP0_SYS_CTRL + 38) |
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60 | #define CPU_OR1K_SPR_EPCR7 (SPR_GRP0_SYS_CTRL + 39) |
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61 | #define CPU_OR1K_SPR_EPCR8 (SPR_GRP0_SYS_CTRL + 40) |
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62 | #define CPU_OR1K_SPR_EPCR9 (SPR_GRP0_SYS_CTRL + 41) |
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63 | #define CPU_OR1K_SPR_EPCR10 (SPR_GRP0_SYS_CTRL + 42) |
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64 | #define CPU_OR1K_SPR_EPCR11 (SPR_GRP0_SYS_CTRL + 43) |
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65 | #define CPU_OR1K_SPR_EPCR12 (SPR_GRP0_SYS_CTRL + 44) |
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66 | #define CPU_OR1K_SPR_EPCR13 (SPR_GRP0_SYS_CTRL + 45) |
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67 | #define CPU_OR1K_SPR_EPCR14 (SPR_GRP0_SYS_CTRL + 46) |
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68 | #define CPU_OR1K_SPR_EPCR15 (SPR_GRP0_SYS_CTRL + 47) |
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69 | #define CPU_OR1K_SPR_EEAR0 (SPR_GRP0_SYS_CTRL + 48) |
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70 | #define CPU_OR1K_SPR_EEAR1 (SPR_GRP0_SYS_CTRL + 49) |
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71 | #define CPU_OR1K_SPR_EEAR2 (SPR_GRP0_SYS_CTRL + 50) |
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72 | #define CPU_OR1K_SPR_EEAR3 (SPR_GRP0_SYS_CTRL + 51) |
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73 | #define CPU_OR1K_SPR_EEAR4 (SPR_GRP0_SYS_CTRL + 52) |
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74 | #define CPU_OR1K_SPR_EEAR5 (SPR_GRP0_SYS_CTRL + 53) |
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75 | #define CPU_OR1K_SPR_EEAR6 (SPR_GRP0_SYS_CTRL + 54) |
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76 | #define CPU_OR1K_SPR_EEAR7 (SPR_GRP0_SYS_CTRL + 55) |
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77 | #define CPU_OR1K_SPR_EEAR8 (SPR_GRP0_SYS_CTRL + 56) |
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78 | #define CPU_OR1K_SPR_EEAR9 (SPR_GRP0_SYS_CTRL + 57) |
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79 | #define CPU_OR1K_SPR_EEAR10 (SPR_GRP0_SYS_CTRL + 58) |
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80 | #define CPU_OR1K_SPR_EEAR11 (SPR_GRP0_SYS_CTRL + 59) |
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81 | #define CPU_OR1K_SPR_EEAR12 (SPR_GRP0_SYS_CTRL + 60) |
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82 | #define CPU_OR1K_SPR_EEAR13 (SPR_GRP0_SYS_CTRL + 61) |
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83 | #define CPU_OR1K_SPR_EEAR14 (SPR_GRP0_SYS_CTRL + 62) |
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84 | #define CPU_OR1K_SPR_EEAR15 (SPR_GRP0_SYS_CTRL + 63) |
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85 | #define CPU_OR1K_SPR_ESR0 (SPR_GRP0_SYS_CTRL + 64) |
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86 | #define CPU_OR1K_SPR_ESR1 (SPR_GRP0_SYS_CTRL + 65) |
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87 | #define CPU_OR1K_SPR_ESR2 (SPR_GRP0_SYS_CTRL + 66) |
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88 | #define CPU_OR1K_SPR_ESR3 (SPR_GRP0_SYS_CTRL + 67) |
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89 | #define CPU_OR1K_SPR_ESR4 (SPR_GRP0_SYS_CTRL + 68) |
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90 | #define CPU_OR1K_SPR_ESR5 (SPR_GRP0_SYS_CTRL + 69) |
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91 | #define CPU_OR1K_SPR_ESR6 (SPR_GRP0_SYS_CTRL + 70) |
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92 | #define CPU_OR1K_SPR_ESR7 (SPR_GRP0_SYS_CTRL + 71) |
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93 | #define CPU_OR1K_SPR_ESR8 (SPR_GRP0_SYS_CTRL + 72) |
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94 | #define CPU_OR1K_SPR_ESR9 (SPR_GRP0_SYS_CTRL + 73) |
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95 | #define CPU_OR1K_SPR_ESR10 (SPR_GRP0_SYS_CTRL + 74) |
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96 | #define CPU_OR1K_SPR_ESR11 (SPR_GRP0_SYS_CTRL + 75) |
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97 | #define CPU_OR1K_SPR_ESR12 (SPR_GRP0_SYS_CTRL + 76) |
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98 | #define CPU_OR1K_SPR_ESR13 (SPR_GRP0_SYS_CTRL + 77) |
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99 | #define CPU_OR1K_SPR_ESR14 (SPR_GRP0_SYS_CTRL + 78) |
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100 | #define CPU_OR1K_SPR_ESR15 (SPR_GRP0_SYS_CTRL + 79) |
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101 | |
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102 | /* Shadow registers base */ |
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103 | #define CPU_OR1K_SPR_GPR32 (SPR_GRP0_SYS_CTRL + 1024) |
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104 | |
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105 | /* Group1: Data MMU registers */ |
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106 | #define CPU_OR1K_SPR_DMMUCR (SPR_GRP1_DMMU + 0) |
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107 | #define CPU_OR1K_SPR_DMMUPR (SPR_GRP1_DMMU + 1) |
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108 | #define CPU_OR1K_SPR_DTLBEIR (SPR_GRP1_DMMU + 2) |
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109 | #define CPU_OR1K_SPR_DATBMR0 (SPR_GRP1_DMMU + 4) |
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110 | #define CPU_OR1K_SPR_DATBMR1 (SPR_GRP1_DMMU + 5) |
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111 | #define CPU_OR1K_SPR_DATBMR2 (SPR_GRP1_DMMU + 6) |
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112 | #define CPU_OR1K_SPR_DATBMR3 (SPR_GRP1_DMMU + 7) |
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113 | #define CPU_OR1K_SPR_DATBTR0 (SPR_GRP1_DMMU + 8) |
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114 | #define CPU_OR1K_SPR_DATBTR1 (SPR_GRP1_DMMU + 9) |
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115 | #define CPU_OR1K_SPR_DATBTR2 (SPR_GRP1_DMMU + 10) |
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116 | #define CPU_OR1K_SPR_DATBTR3 (SPR_GRP1_DMMU + 11) |
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117 | |
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118 | /* Group2: Instruction MMU registers */ |
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119 | #define CPU_OR1K_SPR_IMMUCR (SPR_GRP2_IMMU + 0) |
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120 | #define CPU_OR1K_SPR_IMMUPR (SPR_GRP2_IMMU + 1) |
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121 | #define CPU_OR1K_SPR_ITLBEIR (SPR_GRP2_IMMU + 2) |
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122 | #define CPU_OR1K_SPR_IATBMR0 (SPR_GRP2_IMMU + 4) |
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123 | #define CPU_OR1K_SPR_IATBMR1 (SPR_GRP2_IMMU + 5) |
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124 | #define CPU_OR1K_SPR_IATBMR2 (SPR_GRP2_IMMU + 6) |
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125 | #define CPU_OR1K_SPR_IATBMR3 (SPR_GRP2_IMMU + 7) |
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126 | #define CPU_OR1K_SPR_IATBTR0 (SPR_GRP2_IMMU + 8) |
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127 | #define CPU_OR1K_SPR_IATBTR1 (SPR_GRP2_IMMU + 9) |
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128 | #define CPU_OR1K_SPR_IATBTR2 (SPR_GRP2_IMMU + 10) |
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129 | #define CPU_OR1K_SPR_IATBTR3 (SPR_GRP2_IMMU + 11) |
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130 | |
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131 | /* Group3: Data Cache registers */ |
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132 | #define CPU_OR1K_SPR_DCCR (SPR_GRP3_DC + 0) |
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133 | #define CPU_OR1K_SPR_DCBPR (SPR_GRP3_DC + 1) |
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134 | #define CPU_OR1K_SPR_DCBFR (SPR_GRP3_DC + 2) |
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135 | #define CPU_OR1K_SPR_DCBIR (SPR_GRP3_DC + 3) |
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136 | #define CPU_OR1K_SPR_DCBWR (SPR_GRP3_DC + 4) |
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137 | #define CPU_OR1K_SPR_DCBLR (SPR_GRP3_DC + 5) |
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138 | |
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139 | /* Group4: Instruction Cache registers */ |
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140 | #define CPU_OR1K_SPR_ICCR (SPR_GRP4_IC + 0) |
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141 | #define CPU_OR1K_SPR_ICBPR (SPR_GRP4_IC + 1) |
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142 | #define CPU_OR1K_SPR_ICBIR (SPR_GRP4_IC + 2) |
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143 | #define CPU_OR1K_SPR_ICBLR (SPR_GRP4_IC + 3) |
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144 | |
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145 | /* Group5: MAC registers */ |
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146 | #define CPU_OR1K_SPR_MACLO (SPR_GRP5_MAC + 1) |
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147 | #define CPU_OR1K_SPR_MACHI (SPR_GRP5_MAC + 2) |
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148 | |
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149 | /* Group6: Debug registers */ |
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150 | #define CPU_OR1K_SPR_DVR0 (SPR_GRP6_DEBUG + 0) |
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151 | #define CPU_OR1K_SPR_DVR1 (SPR_GRP6_DEBUG + 1) |
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152 | #define CPU_OR1K_SPR_DVR2 (SPR_GRP6_DEBUG + 2) |
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153 | #define CPU_OR1K_SPR_DVR3 (SPR_GRP6_DEBUG + 3) |
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154 | #define CPU_OR1K_SPR_DVR4 (SPR_GRP6_DEBUG + 4) |
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155 | #define CPU_OR1K_SPR_DVR5 (SPR_GRP6_DEBUG + 5) |
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156 | #define CPU_OR1K_SPR_DVR6 (SPR_GRP6_DEBUG + 6) |
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157 | #define CPU_OR1K_SPR_DVR7 (SPR_GRP6_DEBUG + 7) |
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158 | #define CPU_OR1K_SPR_DCR0 (SPR_GRP6_DEBUG + 8) |
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159 | #define CPU_OR1K_SPR_DCR1 (SPR_GRP6_DEBUG + 9) |
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160 | #define CPU_OR1K_SPR_DCR2 (SPR_GRP6_DEBUG + 10) |
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161 | #define CPU_OR1K_SPR_DCR3 (SPR_GRP6_DEBUG + 11) |
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162 | #define CPU_OR1K_SPR_DCR4 (SPR_GRP6_DEBUG + 12) |
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163 | #define CPU_OR1K_SPR_DCR5 (SPR_GRP6_DEBUG + 13) |
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164 | #define CPU_OR1K_SPR_DCR6 (SPR_GRP6_DEBUG + 14) |
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165 | #define CPU_OR1K_SPR_DCR7 (SPR_GRP6_DEBUG + 15) |
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166 | #define CPU_OR1K_SPR_DMR1 (SPR_GRP6_DEBUG + 16) |
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167 | #define CPU_OR1K_SPR_DMR2 (SPR_GRP6_DEBUG + 17) |
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168 | #define CPU_OR1K_SPR_DCWR0 (SPR_GRP6_DEBUG + 18) |
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169 | #define CPU_OR1K_SPR_DCWR1 (SPR_GRP6_DEBUG + 19) |
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170 | #define CPU_OR1K_SPR_DSR (SPR_GRP6_DEBUG + 20) |
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171 | #define CPU_OR1K_SPR_DRR (SPR_GRP6_DEBUG + 21) |
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172 | |
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173 | /* Group7: Performance counters registers */ |
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174 | #define CPU_OR1K_SPR_PCCR0 (SPR_GRP7_PERF_CTR + 0) |
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175 | #define CPU_OR1K_SPR_PCCR1 (SPR_GRP7_PERF_CTR + 1) |
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176 | #define CPU_OR1K_SPR_PCCR2 (SPR_GRP7_PERF_CTR + 2) |
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177 | #define CPU_OR1K_SPR_PCCR3 (SPR_GRP7_PERF_CTR + 3) |
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178 | #define CPU_OR1K_SPR_PCCR4 (SPR_GRP7_PERF_CTR + 4) |
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179 | #define CPU_OR1K_SPR_PCCR5 (SPR_GRP7_PERF_CTR + 5) |
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180 | #define CPU_OR1K_SPR_PCCR6 (SPR_GRP7_PERF_CTR + 6) |
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181 | #define CPU_OR1K_SPR_PCCR7 (SPR_GRP7_PERF_CTR + 7) |
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182 | #define CPU_OR1K_SPR_PCMR0 (SPR_GRP7_PERF_CTR + 8) |
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183 | #define CPU_OR1K_SPR_PCMR1 (SPR_GRP7_PERF_CTR + 9) |
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184 | #define CPU_OR1K_SPR_PCMR2 (SPR_GRP7_PERF_CTR + 10) |
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185 | #define CPU_OR1K_SPR_PCMR3 (SPR_GRP7_PERF_CTR + 11) |
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186 | #define CPU_OR1K_SPR_PCMR4 (SPR_GRP7_PERF_CTR + 12) |
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187 | #define CPU_OR1K_SPR_PCMR5 (SPR_GRP7_PERF_CTR + 13) |
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188 | #define CPU_OR1K_SPR_PCMR6 (SPR_GRP7_PERF_CTR + 14) |
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189 | #define CPU_OR1K_SPR_PCMR7 (SPR_GRP7_PERF_CTR + 15) |
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190 | |
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191 | /* Group8: Power management register */ |
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192 | #define CPU_OR1K_SPR_PMR (SPR_GRP8_PWR_MNG + 0) |
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193 | |
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194 | /* Group9: PIC registers */ |
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195 | #define CPU_OR1K_SPR_PICMR (SPR_GRP9_PIC + 0) |
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196 | #define CPU_OR1K_SPR_PICSR (SPR_GRP9_PIC + 2) |
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197 | |
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198 | /* Group10: Tick Timer registers */ |
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199 | #define CPU_OR1K_SPR_TTMR (SPR_GPR10_TICK_TMR + 0) |
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200 | #define CPU_OR1K_SPR_TTCR (SPR_GPR10_TICK_TMR + 1) |
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201 | |
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202 | /* Shift amount macros for bits position in Supervision Register */ |
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203 | #define CPU_OR1K_SPR_SR_SHAMT_SM (0) |
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204 | #define CPU_OR1K_SPR_SR_SHAMT_TEE (1) |
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205 | #define CPU_OR1K_SPR_SR_SHAMT_IEE (2) |
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206 | #define CPU_OR1K_SPR_SR_SHAMT_DCE (3) |
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207 | #define CPU_OR1K_SPR_SR_SHAMT_ICE (4) |
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208 | #define CPU_OR1K_SPR_SR_SHAMT_DME (5) |
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209 | #define CPU_OR1K_SPR_SR_SHAMT_IME (6) |
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210 | #define CPU_OR1K_SPR_SR_SHAMT_LEE (7) |
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211 | #define CPU_OR1K_SPR_SR_SHAMT_CE (8) |
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212 | #define CPU_OR1K_SPR_SR_SHAMT_F (9) |
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213 | #define CPU_OR1K_SPR_SR_SHAMT_CY (10) |
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214 | #define CPU_OR1K_SPR_SR_SHAMT_OV (11) |
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215 | #define CPU_OR1K_SPR_SR_SHAMT_OVE (12) |
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216 | #define CPU_OR1K_SPR_SR_SHAMT_DSX (13) |
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217 | #define CPU_OR1K_SPR_SR_SHAMT_EPH (14) |
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218 | #define CPU_OR1K_SPR_SR_SHAMT_FO (15) |
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219 | #define CPU_OR1K_SPR_SR_SHAMT_SUMRA (16) |
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220 | #define CPU_OR1K_SPR_SR_SHAMT_CID (28) |
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221 | |
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222 | /* Supervision Mode Register. @see OpenRISC architecture manual*/ |
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223 | |
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224 | /* Supervisor Mode */ |
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225 | #define CPU_OR1K_SPR_SR_SM (1 << CPU_OR1K_SPR_SR_SHAMT_SM) |
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226 | /* Tick Timer Exception Enabled */ |
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227 | #define CPU_OR1K_SPR_SR_TEE (1 << CPU_OR1K_SPR_SR_SHAMT_TEE) |
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228 | /* Interrupt Exception Enabled */ |
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229 | #define CPU_OR1K_SPR_SR_IEE (1 << CPU_OR1K_SPR_SR_SHAMT_IEE) |
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230 | /* Data Cache Enable */ |
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231 | #define CPU_OR1K_SPR_SR_DCE (1 << CPU_OR1K_SPR_SR_SHAMT_DCE) |
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232 | /* Instruction Cache Enable */ |
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233 | #define CPU_OR1K_SPR_SR_ICE (1 << CPU_OR1K_SPR_SR_SHAMT_ICE) |
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234 | /* Data MMU Enable */ |
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235 | #define CPU_OR1K_SPR_SR_DME (1 << CPU_OR1K_SPR_SR_SHAMT_DME) |
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236 | /* Instruction MMU Enable */ |
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237 | #define CPU_OR1K_SPR_SR_IME (1 << CPU_OR1K_SPR_SR_SHAMT_IME) |
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238 | /* Little Endian Enable */ |
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239 | #define CPU_OR1K_SPR_SR_LEE (1 << CPU_OR1K_SPR_SR_SHAMT_LEE) |
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240 | /* CID Enable */ |
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241 | #define CPU_OR1K_SPR_SR_CE (1 << CPU_OR1K_SPR_SR_SHAMT_CE) |
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242 | /* Conditional branch flag */ |
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243 | #define CPU_OR1K_SPR_SR_F (1 << CPU_OR1K_SPR_SR_SHAMT_F) |
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244 | /* Carry flag */ |
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245 | #define CPU_OR1K_SPR_SR_CY (1 << CPU_OR1K_SPR_SR_SHAMT_CY) |
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246 | /* Overflow flag */ |
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247 | #define CPU_OR1K_SPR_SR_OV (1 << CPU_OR1K_SPR_SR_SHAMT_OV) |
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248 | /* Overflow flag Exception */ |
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249 | #define CPU_OR1K_SPR_SR_OVE (1 << CPU_OR1K_SPR_SR_SHAMT_OVE) |
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250 | /* Delay Slot Exception */ |
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251 | #define CPU_OR1K_SPR_SR_DSX (1 << CPU_OR1K_SPR_SR_SHAMT_DSX) |
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252 | /* Exception Prefix High */ |
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253 | #define CPU_OR1K_SPR_SR_EPH (1 << CPU_OR1K_SPR_SR_SHAMT_EPH) |
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254 | /* Fixed One */ |
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255 | #define CPU_OR1K_SPR_SR_FO (1 << CPU_OR1K_SPR_SR_SHAMT_FO) |
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256 | /* SPRs User Mode Read Access */ |
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257 | #define CPU_OR1K_SPR_SR_SUMRA (1 << CPU_OR1K_SPR_SR_SHAMT_SUMRA) |
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258 | /*Context ID (Fast Context Switching) */ |
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259 | #define CPU_OR1K_SPR_SR_CID (F << CPU_OR1K_SPR_SR_SHAMT_CID) |
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260 | |
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261 | /* Tick timer configuration bits */ |
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262 | #define CPU_OR1K_SPR_TTMR_SHAMT_IP 28 |
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263 | #define CPU_OR1K_SPR_TTMR_SHAMT_IE 29 |
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264 | #define CPU_OR1K_SPR_TTMR_SHAMT_MODE 30 |
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265 | |
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266 | #define CPU_OR1K_SPR_TTMR_TP_MASK (0x0FFFFFFF) |
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267 | #define CPU_OR1K_SPR_TTMR_IP (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP) |
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268 | #define CPU_OR1K_SPR_TTMR_IE (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE) |
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269 | #define CPU_OR1K_SPR_TTMR_MODE_RESTART (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) |
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270 | #define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) |
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271 | #define CPU_OR1K_SPR_TTMR_MODE_CONT (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE) |
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272 | |
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273 | /* Power management register bits */ |
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274 | |
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275 | /* Shift amount macros for bit positions in Power Management register */ |
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276 | #define CPU_OR1K_SPR_PMR_SHAMT_SDF 0 |
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277 | #define CPU_OR1K_SPR_PMR_SHAMT_DME 4 |
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278 | #define CPU_OR1K_SPR_PMR_SHAMT_SME 5 |
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279 | #define CPU_OR1K_SPR_PMR_SHAMT_DCGE 6 |
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280 | #define CPU_OR1K_SPR_PMR_SHAMT_SUME 7 |
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281 | |
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282 | #define CPU_OR1K_SPR_PMR_SDF (0xF << CPU_OR1K_SPR_PMR_SHAMT_SDF) |
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283 | #define CPU_OR1K_SPR_PMR_DME (1 << CPU_OR1K_SPR_PMR_SHAMT_DME) |
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284 | #define CPU_OR1K_SPR_PMR_SME (1 << CPU_OR1K_SPR_PMR_SHAMT_SME) |
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285 | #define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE) |
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286 | #define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME) |
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287 | |
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288 | #ifndef ASM |
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289 | |
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290 | #include <stddef.h> |
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291 | #include <stdint.h> |
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292 | #include <stdbool.h> |
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293 | |
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294 | #ifdef __cplusplus |
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295 | extern "C" { |
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296 | #endif /* __cplusplus */ |
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297 | |
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298 | /** |
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299 | * @brief Supervision Mode registers definitions. |
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300 | * |
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301 | * @see OpenRISC architecture manual - revision 0. |
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302 | */ |
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303 | typedef enum { |
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304 | OR1K_EXCEPTION_RESET = 1, |
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305 | OR1K_EXCEPTION_BUS_ERR = 2, |
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306 | OR1K_EXCEPTION_D_PF = 3, /* Data Page Fault */ |
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307 | OR1K_EXCEPTION_I_PF = 4, /* Instruction Page Fault */ |
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308 | OR1K_EXCEPTION_TICK_TIMER = 5, |
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309 | OR1K_EXCEPTION_ALIGNMENT = 6, |
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310 | OR1K_EXCEPTION_I_UNDEF= 7, /* Undefiend instruction */ |
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311 | OR1K_EXCEPTION_IRQ = 8, /* External interrupt */ |
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312 | OR1K_EXCPETION_D_TLB = 9, /* Data TLB miss */ |
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313 | OR1K_EXCPETION_I_TLB = 10, /* Instruction TLB miss */ |
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314 | OR1K_EXCPETION_RANGE = 11, /* Range exception */ |
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315 | OR1K_EXCPETION_SYS_CALL = 12, |
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316 | OR1K_EXCPETION_FP = 13, /* Floating point exception */ |
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317 | OR1K_EXCPETION_TRAP = 14, /* Caused by l.trap instruction or by debug unit */ |
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318 | OR1K_EXCPETION_RESERVED1 = 15, |
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319 | OR1K_EXCPETION_RESERVED2 = 16, |
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320 | OR1K_EXCPETION_RESERVED3 = 17, |
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321 | MAX_EXCEPTIONS = 17, |
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322 | OR1K_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff |
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323 | } OR1K_Symbolic_exception_name; |
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324 | |
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325 | static inline uint32_t _OR1K_mfspr(uint32_t reg) |
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326 | { |
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327 | uint32_t spr_value; |
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328 | |
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329 | asm volatile ( |
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330 | "l.mfspr %0, %1, 0;\n\t" |
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331 | : "=r" (spr_value) : "r" (reg)); |
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332 | |
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333 | return spr_value; |
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334 | } |
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335 | |
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336 | static inline void _OR1K_mtspr(uint32_t reg, uint32_t value) |
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337 | { |
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338 | asm volatile ( |
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339 | "l.mtspr %1, %0, 0;\n\t" |
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340 | :: "r" (value), "r" (reg) |
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341 | ); |
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342 | } |
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343 | |
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344 | /** |
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345 | * @brief The slow down feature takes advantage of the low-power |
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346 | * dividers in external clock generation circuitry to enable full |
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347 | * functionality, but at a lower frequency so that power consumption |
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348 | * is reduced. @see OpenRISC architecture manual, power management section. |
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349 | * |
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350 | * @param[in] value is 4 bit value to be written in PMR[SDF]. |
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351 | * A lower value specifies higher expected performance from the processor core. |
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352 | * |
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353 | */ |
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354 | #define _OR1K_CPU_SlowDown(value) \ |
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355 | _OR1K_mtspr(CPU_OR1K_SPR_PMR, (value & CPU_OR1K_SPR_PMR_SDF)) |
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356 | |
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357 | |
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358 | #define _OR1K_CPU_Doze() \ |
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359 | _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_DME) |
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360 | |
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361 | |
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362 | #define _OR1K_CPU_Sleep() \ |
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363 | _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) |
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364 | |
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365 | #define _OR1K_CPU_Suspend() \ |
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366 | _OR1K_mtspr(CPU_OR1K_SPR_PMR, CPU_OR1K_SPR_PMR_SME) |
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367 | |
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368 | static inline void _OR1K_Sync_mem( void ) |
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369 | { |
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370 | asm volatile("l.msync"); |
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371 | } |
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372 | |
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373 | static inline void _OR1K_Sync_pipeline( void ) |
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374 | { |
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375 | asm volatile("l.psync"); |
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376 | } |
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377 | |
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378 | /** |
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379 | * @brief or1ksim simulator can be sent a halt signal from RTEMS to tell |
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380 | * the running or1ksim process on the host machine to exit. The following |
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381 | * implementation has no effect on QEMU or hardware implementation and will |
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382 | * be treated as normal l.nop. |
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383 | * |
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384 | */ |
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385 | #define _OR1KSIM_CPU_Halt() \ |
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386 | asm volatile ("l.nop 0xc") |
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387 | |
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388 | #else /* ASM */ |
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389 | |
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390 | #endif /* ASM */ |
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391 | |
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392 | #endif /* _RTEMS_SCORE_OR1K_UTILITY_H */ |
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