source: rtems/cpukit/score/cpu/or1k/rtems/score/cpu.h @ 4aa23c96

5
Last change on this file since 4aa23c96 was 4aa23c96, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 23, 2017 at 7:12:18 AM

Remove CPU_BIG_ENDIAN and CPU_LITTLE_ENDIAN

Use de-facto standard BYTE_ORDER instead.

Close #2803.

  • Property mode set to 100644
File size: 25.0 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains macros pertaining to the Opencores
7 *  or1k processor family.
8 *
9 *  COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
10 *  COPYRIGHT (c) 1989-1999.
11 *  On-Line Applications Research Corporation (OAR).
12 *
13 *  The license and distribution terms for this file may be
14 *  found in the file LICENSE in this distribution or at
15 *  http://www.rtems.org/license/LICENSE.
16 *
17 *  This file adapted from no_cpu example of the RTEMS distribution.
18 *  The body has been modified for the Opencores OR1k implementation by
19 *  Chris Ziomkowski. <chris@asics.ws>
20 *
21 */
22
23#ifndef _OR1K_CPU_H
24#define _OR1K_CPU_H
25
26#ifdef __cplusplus
27extern "C" {
28#endif
29
30
31#include <rtems/score/or1k.h>            /* pick up machine definitions */
32#include <rtems/score/or1k-utility.h>
33#include <rtems/score/types.h>
34#ifndef ASM
35#include <rtems/bspIo.h>
36#include <stdint.h>
37#include <stdio.h> /* for printk */
38#endif
39
40/* conditional compilation parameters */
41
42/*
43 *  Does RTEMS manage a dedicated interrupt stack in software?
44 *
45 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
46 *  If FALSE, nothing is done.
47 *
48 *  If the CPU supports a dedicated interrupt stack in hardware,
49 *  then it is generally the responsibility of the BSP to allocate it
50 *  and set it up.
51 *
52 *  If the CPU does not support a dedicated interrupt stack, then
53 *  the porter has two options: (1) execute interrupts on the
54 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
55 *  interrupt stack.
56 *
57 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
58 *
59 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
60 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
61 *  possible that both are FALSE for a particular CPU.  Although it
62 *  is unclear what that would imply about the interrupt processing
63 *  procedure on that CPU.
64 *
65 *  Currently, for or1k port, _ISR_Handler is responsible for switching to
66 *  RTEMS dedicated interrupt task.
67 *
68 */
69
70#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
71
72/*
73 *  Does this CPU have hardware support for a dedicated interrupt stack?
74 *
75 *  If TRUE, then it must be installed during initialization.
76 *  If FALSE, then no installation is performed.
77 *
78 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
79 *
80 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
81 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
82 *  possible that both are FALSE for a particular CPU.  Although it
83 *  is unclear what that would imply about the interrupt processing
84 *  procedure on that CPU.
85 *
86 */
87
88#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
89
90/*
91 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
92 *
93 *  If TRUE, then the memory is allocated during initialization.
94 *  If FALSE, then the memory is allocated during initialization.
95 *
96 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
97 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
98 *
99 */
100
101#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
102
103/*
104 *  Does the RTEMS invoke the user's ISR with the vector number and
105 *  a pointer to the saved interrupt frame (1) or just the vector
106 *  number (0)?
107 *
108 */
109
110#define CPU_ISR_PASSES_FRAME_POINTER TRUE
111
112/*
113 *  Does the CPU have hardware floating point?
114 *
115 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
116 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
117 *
118 *  If there is a FP coprocessor such as the i387 or mc68881, then
119 *  the answer is TRUE.
120 *
121 *  The macro name "OR1K_HAS_FPU" should be made CPU specific.
122 *  It indicates whether or not this CPU model has FP support.  For
123 *  example, it would be possible to have an i386_nofp CPU model
124 *  which set this to false to indicate that you have an i386 without
125 *  an i387 and wish to leave floating point support out of RTEMS.
126 *
127 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
128 *  is software implemented floating point that must be context
129 *  switched.  The determination of whether or not this applies
130 *  is very tool specific and the state saved/restored is also
131 *  compiler specific.
132 *
133 *  Or1k Specific Information:
134 *
135 *  At this time there are no implementations of Or1k that are
136 *  expected to implement floating point. More importantly, the
137 *  floating point architecture is expected to change significantly
138 *  before such chips are fabricated.
139 */
140
141#define CPU_HARDWARE_FP     FALSE
142#define CPU_SOFTWARE_FP     FALSE
143
144/*
145 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
146 *
147 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
148 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
149 *
150 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
151 *
152 */
153
154#define CPU_ALL_TASKS_ARE_FP     FALSE
155
156/*
157 *  Should the IDLE task have a floating point context?
158 *
159 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
160 *  and it has a floating point context which is switched in and out.
161 *  If FALSE, then the IDLE task does not have a floating point context.
162 *
163 *  Setting this to TRUE negatively impacts the time required to preempt
164 *  the IDLE task from an interrupt because the floating point context
165 *  must be saved as part of the preemption.
166 *
167 */
168
169#define CPU_IDLE_TASK_IS_FP      FALSE
170
171/*
172 *  Should the saving of the floating point registers be deferred
173 *  until a context switch is made to another different floating point
174 *  task?
175 *
176 *  If TRUE, then the floating point context will not be stored until
177 *  necessary.  It will remain in the floating point registers and not
178 *  disturned until another floating point task is switched to.
179 *
180 *  If FALSE, then the floating point context is saved when a floating
181 *  point task is switched out and restored when the next floating point
182 *  task is restored.  The state of the floating point registers between
183 *  those two operations is not specified.
184 *
185 *  If the floating point context does NOT have to be saved as part of
186 *  interrupt dispatching, then it should be safe to set this to TRUE.
187 *
188 *  Setting this flag to TRUE results in using a different algorithm
189 *  for deciding when to save and restore the floating point context.
190 *  The deferred FP switch algorithm minimizes the number of times
191 *  the FP context is saved and restored.  The FP context is not saved
192 *  until a context switch is made to another, different FP task.
193 *  Thus in a system with only one FP task, the FP context will never
194 *  be saved or restored.
195 *
196 */
197
198#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
199
200#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
201
202/*
203 *  Does this port provide a CPU dependent IDLE task implementation?
204 *
205 *  If TRUE, then the routine _CPU_Thread_Idle_body
206 *  must be provided and is the default IDLE thread body instead of
207 *  _CPU_Thread_Idle_body.
208 *
209 *  If FALSE, then use the generic IDLE thread body if the BSP does
210 *  not provide one.
211 *
212 *  This is intended to allow for supporting processors which have
213 *  a low power or idle mode.  When the IDLE thread is executed, then
214 *  the CPU can be powered down.
215 *
216 *  The order of precedence for selecting the IDLE thread body is:
217 *
218 *    1.  BSP provided
219 *    2.  CPU dependent (if provided)
220 *    3.  generic (if no BSP and no CPU dependent)
221 *
222 */
223
224#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
225
226/*
227 *  Does the stack grow up (toward higher addresses) or down
228 *  (toward lower addresses)?
229 *
230 *  If TRUE, then the grows upward.
231 *  If FALSE, then the grows toward smaller addresses.
232 *
233 */
234
235#define CPU_STACK_GROWS_UP               FALSE
236
237/* FIXME: Is this the right value? */
238#define CPU_CACHE_LINE_BYTES 32
239
240#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
241
242/*
243 *  Define what is required to specify how the network to host conversion
244 *  routines are handled.
245 *
246 *  Or1k Specific Information:
247 *
248 *  This version of RTEMS is designed specifically to run with
249 *  big endian architectures. If you want little endian, you'll
250 *  have to make the appropriate adjustments here and write
251 *  efficient routines for byte swapping. The Or1k architecture
252 *  doesn't do this very well.
253 */
254
255#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
256
257/*
258 *  The following defines the number of bits actually used in the
259 *  interrupt field of the task mode.  How those bits map to the
260 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
261 *
262 */
263
264#define CPU_MODES_INTERRUPT_MASK   0x00000001
265
266/*
267 *  Processor defined structures required for cpukit/score.
268 */
269
270
271/*
272 * Contexts
273 *
274 *  Generally there are 2 types of context to save.
275 *     1. Interrupt registers to save
276 *     2. Task level registers to save
277 *
278 *  This means we have the following 3 context items:
279 *     1. task level context stuff::  Context_Control
280 *     2. floating point task stuff:: Context_Control_fp
281 *     3. special interrupt level context :: Context_Control_interrupt
282 *
283 *  On some processors, it is cost-effective to save only the callee
284 *  preserved registers during a task context switch.  This means
285 *  that the ISR code needs to save those registers which do not
286 *  persist across function calls.  It is not mandatory to make this
287 *  distinctions between the caller/callee saves registers for the
288 *  purpose of minimizing context saved during task switch and on interrupts.
289 *  If the cost of saving extra registers is minimal, simplicity is the
290 *  choice.  Save the same context on interrupt entry as for tasks in
291 *  this case.
292 *
293 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
294 *  care should be used in designing the context area.
295 *
296 *  On some CPUs with hardware floating point support, the Context_Control_fp
297 *  structure will not be used or it simply consist of an array of a
298 *  fixed number of bytes.   This is done when the floating point context
299 *  is dumped by a "FP save context" type instruction and the format
300 *  is not really defined by the CPU.  In this case, there is no need
301 *  to figure out the exact format -- only the size.  Of course, although
302 *  this is enough information for RTEMS, it is probably not enough for
303 *  a debugger such as gdb.  But that is another problem.
304 *
305 *
306 */
307#ifndef ASM
308#ifdef OR1K_64BIT_ARCH
309#define or1kreg uint64_t
310#else
311#define or1kreg uint32_t
312#endif
313
314typedef struct {
315  uint32_t  r1;     /* Stack pointer */
316  uint32_t  r2;     /* Frame pointer */
317  uint32_t  r3;
318  uint32_t  r4;
319  uint32_t  r5;
320  uint32_t  r6;
321  uint32_t  r7;
322  uint32_t  r8;
323  uint32_t  r9;
324  uint32_t  r10;
325  uint32_t  r11;
326  uint32_t  r12;
327  uint32_t  r13;
328  uint32_t  r14;
329  uint32_t  r15;
330  uint32_t  r16;
331  uint32_t  r17;
332  uint32_t  r18;
333  uint32_t  r19;
334  uint32_t  r20;
335  uint32_t  r21;
336  uint32_t  r22;
337  uint32_t  r23;
338  uint32_t  r24;
339  uint32_t  r25;
340  uint32_t  r26;
341  uint32_t  r27;
342  uint32_t  r28;
343  uint32_t  r29;
344  uint32_t  r30;
345  uint32_t  r31;
346
347  uint32_t  sr;  /* Current supervision register non persistent values */
348  uint32_t  epcr;
349  uint32_t  eear;
350  uint32_t  esr;
351} Context_Control;
352
353#define _CPU_Context_Get_SP( _context ) \
354  (_context)->r1
355
356typedef struct {
357  /** FPU registers are listed here */
358  double      some_float_register;
359} Context_Control_fp;
360
361typedef Context_Control CPU_Interrupt_frame;
362
363/*
364 *  The size of the floating point context area.  On some CPUs this
365 *  will not be a "sizeof" because the format of the floating point
366 *  area is not defined -- only the size is.  This is usually on
367 *  CPUs with a "floating point save context" instruction.
368 *
369 *  Or1k Specific Information:
370 *
371 */
372
373#define CPU_CONTEXT_FP_SIZE  0
374
375/*
376 *  Amount of extra stack (above minimum stack size) required by
377 *  MPCI receive server thread.  Remember that in a multiprocessor
378 *  system this thread must exist and be able to process all directives.
379 *
380 */
381
382#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
383
384/*
385 *  Should be large enough to run all RTEMS tests.  This insures
386 *  that a "reasonable" small application should not have any problems.
387 *
388 */
389
390#define CPU_STACK_MINIMUM_SIZE  4096
391
392/*
393 *  CPU's worst alignment requirement for data types on a byte boundary.  This
394 *  alignment does not take into account the requirements for the stack.
395 *
396 */
397
398#define CPU_ALIGNMENT  8
399
400/*
401 *  This is defined if the port has a special way to report the ISR nesting
402 *  level.  Most ports maintain the variable _ISR_Nest_level.
403 */
404#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
405
406/**
407 * Size of a pointer.
408 *
409 * This must be an integer literal that can be used by the assembler.  This
410 * value will be used to calculate offsets of structure members.  These
411 * offsets will be used in assembler code.
412 */
413#define CPU_SIZEOF_POINTER         4
414
415/*
416 *  This number corresponds to the byte alignment requirement for the
417 *  heap handler.  This alignment requirement may be stricter than that
418 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
419 *  common for the heap to follow the same alignment requirement as
420 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
421 *  then this should be set to CPU_ALIGNMENT.
422 *
423 *  NOTE:  This does not have to be a power of 2 although it should be
424 *         a multiple of 2 greater than or equal to 2.  The requirement
425 *         to be a multiple of 2 is because the heap uses the least
426 *         significant field of the front and back flags to indicate
427 *         that a block is in use or free.  So you do not want any odd
428 *         length blocks really putting length data in that bit.
429 *
430 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
431 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
432 *         elements allocated from the heap meet all restrictions.
433 *
434 */
435
436#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
437
438/*
439 *  This number corresponds to the byte alignment requirement for memory
440 *  buffers allocated by the partition manager.  This alignment requirement
441 *  may be stricter than that for the data types alignment specified by
442 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
443 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
444 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
445 *
446 *  NOTE:  This does not have to be a power of 2.  It does have to
447 *         be greater or equal to than CPU_ALIGNMENT.
448 *
449 */
450
451#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
452
453/*
454 *  This number corresponds to the byte alignment requirement for the
455 *  stack.  This alignment requirement may be stricter than that for the
456 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
457 *  is strict enough for the stack, then this should be set to 0.
458 *
459 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
460 *
461 */
462
463#define CPU_STACK_ALIGNMENT        0
464
465/* ISR handler macros */
466
467/*
468 *  Support routine to initialize the RTEMS vector table after it is allocated.
469 *
470 *  NO_CPU Specific Information:
471 *
472 *  XXX document implementation including references if appropriate
473 */
474
475#define _CPU_Initialize_vectors()
476
477/*
478 *  Disable all interrupts for an RTEMS critical section.  The previous
479 *  level is returned in _level.
480 *
481 */
482
483static inline uint32_t or1k_interrupt_disable( void )
484{
485  uint32_t sr;
486  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
487
488  _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE));
489
490  return sr;
491}
492
493static inline void or1k_interrupt_enable(uint32_t level)
494{
495  uint32_t sr;
496
497  /* Enable interrupts and restore rs */
498  sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
499  _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
500
501}
502
503#define _CPU_ISR_Disable( _level ) \
504    _level = or1k_interrupt_disable()
505
506
507/*
508 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
509 *  This indicates the end of an RTEMS critical section.  The parameter
510 *  _level is not modified.
511 *
512 */
513
514#define _CPU_ISR_Enable( _level )  \
515  or1k_interrupt_enable( _level )
516
517/*
518 *  This temporarily restores the interrupt to _level before immediately
519 *  disabling them again.  This is used to divide long RTEMS critical
520 *  sections into two or more parts.  The parameter _level is not
521 *  modified.
522 *
523 */
524
525#define _CPU_ISR_Flash( _level ) \
526  do{ \
527      _CPU_ISR_Enable( _level ); \
528      _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \
529    } while(0)
530
531RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
532{
533  return ( level & CPU_OR1K_SPR_SR ) != 0;
534}
535
536/*
537 *  Map interrupt level in task mode onto the hardware that the CPU
538 *  actually provides.  Currently, interrupt levels which do not
539 *  map onto the CPU in a generic fashion are undefined.  Someday,
540 *  it would be nice if these were "mapped" by the application
541 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
542 *  8 - 255 would be available for bsp/application specific meaning.
543 *  This could be used to manage a programmable interrupt controller
544 *  via the rtems_task_mode directive.
545 *
546 *  The get routine usually must be implemented as a subroutine.
547 *
548 */
549
550void _CPU_ISR_Set_level( uint32_t level );
551
552uint32_t _CPU_ISR_Get_level( void );
553
554/* end of ISR handler macros */
555
556/* Context handler macros */
557
558#define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE
559/*
560 *  Initialize the context to a state suitable for starting a
561 *  task after a context restore operation.  Generally, this
562 *  involves:
563 *
564 *     - setting a starting address
565 *     - preparing the stack
566 *     - preparing the stack and frame pointers
567 *     - setting the proper interrupt level in the context
568 *     - initializing the floating point context
569 *
570 *  This routine generally does not set any unnecessary register
571 *  in the context.  The state of the "general data" registers is
572 *  undefined at task start time.
573 *
574 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
575 *        point thread.  This is typically only used on CPUs where the
576 *        FPU may be easily disabled by software such as on the SPARC
577 *        where the PSR contains an enable FPU bit.
578 *
579 */
580
581/**
582 * @brief Initializes the CPU context.
583 *
584 * The following steps are performed:
585 *  - setting a starting address
586 *  - preparing the stack
587 *  - preparing the stack and frame pointers
588 *  - setting the proper interrupt level in the context
589 *
590 * @param[in] context points to the context area
591 * @param[in] stack_area_begin is the low address of the allocated stack area
592 * @param[in] stack_area_size is the size of the stack area in bytes
593 * @param[in] new_level is the interrupt level for the task
594 * @param[in] entry_point is the task's entry point
595 * @param[in] is_fp is set to @c true if the task is a floating point task
596 * @param[in] tls_area is the thread-local storage (TLS) area
597 */
598void _CPU_Context_Initialize(
599  Context_Control *context,
600  void *stack_area_begin,
601  size_t stack_area_size,
602  uint32_t new_level,
603  void (*entry_point)( void ),
604  bool is_fp,
605  void *tls_area
606);
607
608/*
609 *  This routine is responsible for somehow restarting the currently
610 *  executing task.  If you are lucky, then all that is necessary
611 *  is restoring the context.  Otherwise, there will need to be
612 *  a special assembly routine which does something special in this
613 *  case.  Context_Restore should work most of the time.  It will
614 *  not work if restarting self conflicts with the stack frame
615 *  assumptions of restoring a context.
616 *
617 */
618
619#define _CPU_Context_Restart_self( _the_context ) \
620   _CPU_Context_restore( (_the_context) );
621
622/*
623 *  The purpose of this macro is to allow the initial pointer into
624 *  a floating point context area (used to save the floating point
625 *  context) to be at an arbitrary place in the floating point
626 *  context area.
627 *
628 *  This is necessary because some FP units are designed to have
629 *  their context saved as a stack which grows into lower addresses.
630 *  Other FP units can be saved by simply moving registers into offsets
631 *  from the base of the context area.  Finally some FP units provide
632 *  a "dump context" instruction which could fill in from high to low
633 *  or low to high based on the whim of the CPU designers.
634 *
635 */
636
637#define _CPU_Context_Fp_start( _base, _offset ) \
638   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
639
640#define _CPU_Context_Initialize_fp( _destination ) \
641  memset( *( _destination ), 0, CPU_CONTEXT_FP_SIZE );
642
643/* end of Context handler macros */
644
645/* Fatal Error manager macros */
646
647/*
648 *  This routine copies _error into a known place -- typically a stack
649 *  location or a register, optionally disables interrupts, and
650 *  halts/stops the CPU.
651 *
652 */
653
654#define _CPU_Fatal_halt(_source, _error ) \
655        printk("Fatal Error %d.%d Halted\n",_source, _error); \
656        _OR1KSIM_CPU_Halt(); \
657        for(;;)
658
659/* end of Fatal Error manager macros */
660
661#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
662
663#endif /* ASM */
664
665#define CPU_SIZEOF_POINTER 4
666
667#define CPU_MAXIMUM_PROCESSORS 32
668
669#ifndef ASM
670typedef uint32_t CPU_Counter_ticks;
671
672typedef struct {
673  uint32_t r[32];
674
675  /* The following registers must be saved if we have
676  fast context switch disabled and nested interrupt
677  levels are enabled.
678  */
679#if !OR1K_FAST_CONTEXT_SWITCH_ENABLED
680  uint32_t epcr; /* exception PC register */
681  uint32_t eear; /* exception effective address register */
682  uint32_t esr; /* exception supervision register */
683#endif
684
685} CPU_Exception_frame;
686
687/**
688 * @brief Prints the exception frame via printk().
689 *
690 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
691 */
692void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
693
694
695/* end of Priority handler macros */
696
697/* functions */
698
699/*
700 *  _CPU_Initialize
701 *
702 *  This routine performs CPU dependent initialization.
703 *
704 */
705
706void _CPU_Initialize(
707  void
708);
709
710/*
711 *  _CPU_ISR_install_raw_handler
712 *
713 *  This routine installs a "raw" interrupt handler directly into the
714 *  processor's vector table.
715 *
716 */
717
718void _CPU_ISR_install_raw_handler(
719  uint32_t    vector,
720  proc_ptr    new_handler,
721  proc_ptr   *old_handler
722);
723
724/*
725 *  _CPU_ISR_install_vector
726 *
727 *  This routine installs an interrupt vector.
728 *
729 *  NO_CPU Specific Information:
730 *
731 *  XXX document implementation including references if appropriate
732 */
733
734void _CPU_ISR_install_vector(
735  uint32_t    vector,
736  proc_ptr   new_handler,
737  proc_ptr   *old_handler
738);
739
740/*
741 *  _CPU_Install_interrupt_stack
742 *
743 *  This routine installs the hardware interrupt stack pointer.
744 *
745 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
746 *         is TRUE.
747 *
748 */
749
750void _CPU_Install_interrupt_stack( void );
751
752/*
753 *  _CPU_Thread_Idle_body
754 *
755 *  This routine is the CPU dependent IDLE thread body.
756 *
757 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
758 *         is TRUE.
759 *
760 */
761
762void *_CPU_Thread_Idle_body( uintptr_t ignored );
763
764/*
765 *  _CPU_Context_switch
766 *
767 *  This routine switches from the run context to the heir context.
768 *
769 *  Or1k Specific Information:
770 *
771 *  Please see the comments in the .c file for a description of how
772 *  this function works. There are several things to be aware of.
773 */
774
775void _CPU_Context_switch(
776  Context_Control  *run,
777  Context_Control  *heir
778);
779
780/*
781 *  _CPU_Context_restore
782 *
783 *  This routine is generally used only to restart self in an
784 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
785 *
786 *  NOTE: May be unnecessary to reload some registers.
787 *
788 */
789
790void _CPU_Context_restore(
791  Context_Control *new_context
792) RTEMS_NO_RETURN;
793
794/*
795 *  _CPU_Context_save_fp
796 *
797 *  This routine saves the floating point context passed to it.
798 *
799 */
800
801void _CPU_Context_save_fp(
802  void **fp_context_ptr
803);
804
805/*
806 *  _CPU_Context_restore_fp
807 *
808 *  This routine restores the floating point context passed to it.
809 *
810 */
811
812void _CPU_Context_restore_fp(
813  void **fp_context_ptr
814);
815
816/*  The following routine swaps the endian format of an unsigned int.
817 *  It must be static because it is referenced indirectly.
818 *
819 *  This version will work on any processor, but if there is a better
820 *  way for your CPU PLEASE use it.  The most common way to do this is to:
821 *
822 *     swap least significant two bytes with 16-bit rotate
823 *     swap upper and lower 16-bits
824 *     swap most significant two bytes with 16-bit rotate
825 *
826 *  Some CPUs have special instructions which swap a 32-bit quantity in
827 *  a single instruction (e.g. i486).  It is probably best to avoid
828 *  an "endian swapping control bit" in the CPU.  One good reason is
829 *  that interrupts would probably have to be disabled to insure that
830 *  an interrupt does not try to access the same "chunk" with the wrong
831 *  endian.  Another good reason is that on some CPUs, the endian bit
832 *  endianness for ALL fetches -- both code and data -- so the code
833 *  will be fetched incorrectly.
834 *
835 */
836
837void _CPU_Context_volatile_clobber( uintptr_t pattern );
838
839void _CPU_Context_validate( uintptr_t pattern );
840
841static inline unsigned int CPU_swap_u32(
842  unsigned int value
843)
844{
845  uint32_t   byte1, byte2, byte3, byte4, swapped;
846
847  byte4 = (value >> 24) & 0xff;
848  byte3 = (value >> 16) & 0xff;
849  byte2 = (value >> 8)  & 0xff;
850  byte1 =  value        & 0xff;
851
852  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
853  return( swapped );
854}
855
856#define CPU_swap_u16( value ) \
857  (((value&0xff) << 8) | ((value >> 8)&0xff))
858
859typedef uint32_t CPU_Counter_ticks;
860
861CPU_Counter_ticks _CPU_Counter_read( void );
862
863CPU_Counter_ticks _CPU_Counter_difference(
864  CPU_Counter_ticks second,
865  CPU_Counter_ticks first
866);
867
868#endif /* ASM */
869
870#ifdef __cplusplus
871}
872#endif
873
874#endif
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