source: rtems/cpukit/score/cpu/or1k/or1k-exception-handler-low.S @ 39594416

5
Last change on this file since 39594416 was 39594416, checked in by Andreas Dachsberger <andreas.dachsberger@…>, on Mar 26, 2019 at 10:40:41 AM

doxygen: score: Add or1k CPU architecture group

Update #3706.

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File size: 4.6 KB
Line 
1/**
2 * @file
3 *
4 * @addtogroup RTEMSScoreCPU
5 *
6 * @brief OR1K exception support implementation.
7 */
8
9/*
10 *  COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.org/license/LICENSE.
15 *
16 */
17
18#ifdef HAVE_CONFIG_H
19#include "config.h"
20#endif
21
22#include <rtems/asm.h>
23#include <rtems/score/percpu.h>
24#include "rtems/score/or1k-utility.h"
25
26.align 4
27.text
28PUBLIC(_ISR_Handler)
29.type    _ISR_Handler,@function
30
31 SYM(_ISR_Handler):
32
33  l.addi  r1, r1, -140
34
35  l.sw  8(r1),r2
36  /* r3 is saved by BSP exception handler */
37  l.sw  16(r1),r4
38  l.sw  20(r1),r5
39  l.sw  24(r1),r6
40  l.sw  28(r1),r7
41  l.sw  32(r1),r8
42  l.sw  36(r1),r9
43  l.sw  40(r1),r10
44  l.sw  44(r1),r11
45  l.sw  48(r1),r12
46  l.sw  52(r1),r13
47  l.sw  56(r1),r14
48  l.sw  60(r1),r15
49  l.sw  64(r1),r16
50  l.sw  68(r1),r17
51  l.sw  72(r1),r18
52  l.sw  76(r1),r19
53  l.sw  80(r1),r20
54  l.sw  84(r1),r21
55  l.sw  88(r1),r22
56  l.sw  92(r1),r23
57  l.sw  96(r1),r24
58  l.sw  100(r1),r25
59  l.sw  104(r1),r26
60  l.sw  108(r1),r27
61  l.sw  112(r1),r28
62  l.sw  116(r1),r29
63  l.sw  120(r1),r30
64  l.sw  124(r1),r31
65
66  /* Exception level related registers */
67
68  /* EPCR */
69  l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
70  l.sw  128(r1), r13 /* epcr */
71
72  /* EEAR */
73  l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
74  l.sw  132(r1), r13 /* eear */
75
76  /* ESR */
77  l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
78  l.sw  136(r1), r13  /* esr */
79
80  /* Increment nesting level */
81  l.movhi r6, hi(ISR_NEST_LEVEL)
82  l.ori   r6, r6, lo(ISR_NEST_LEVEL)
83
84  /* Disable multitasking */
85  l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL)
86  l.ori   r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL)
87
88  l.lwz   r5, 0(r6)
89  l.lwz   r7, 0(r8)
90  l.addi  r5, r5, 1
91  l.addi  r7, r7, 1
92  l.sw    0(r6), r5
93  l.sw    0(r8), r7
94
95  /* Save interrupted task stack pointer */
96  l.addi r4, r1, 340
97  l.sw   4(r1), r4
98
99  /* Save interrupted task r3 (first arg) value */
100  l.addi r4, r1, 140
101  l.lwz  r4, 0(r4)
102  l.sw  12(r1), r4
103
104  /* Keep r1 (Exception frame address) in r14 */
105  l.add   r14, r1, r0
106
107  /* Call the exception handler from vector table */
108
109  /* First function arg for C handler is vector number,
110   * and the second is a pointer to exception frame.
111   */
112  l.add  r13, r3, r0
113  l.add  r4, r1, r0
114  l.slli r13, r13, 2
115  l.addi r13, r13, lo(bsp_start_vector_table_begin)
116  l.lwz  r13, 0(r13)
117
118  /* Do not switch stacks if we are in a nested interrupt. At
119   * this point r5 should be holding ISR_NEST_LEVEL value.
120   */
121  l.sfgtui r5, 1
122  l.bf jump_to_c_handler
123  l.nop
124
125   /* Switch to RTEMS dedicated interrupt stack */
126  l.movhi r1, hi(INTERRUPT_STACK_HIGH)
127  l.ori   r1, r1, lo(INTERRUPT_STACK_HIGH)
128  l.lwz   r1, 0(r1)
129
130jump_to_c_handler:
131  l.jalr r13
132  l.nop
133
134  /* Switch back to the interrupted task stack */
135  l.add r1, r14, r0
136
137  /* Decrement nesting level */
138  l.movhi r6, hi(ISR_NEST_LEVEL)
139  l.ori   r6, r6, lo(ISR_NEST_LEVEL)
140
141  /* Enable multitasking */
142  l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL)
143  l.ori   r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL)
144
145  l.lwz   r5, 0(r6)
146  l.lwz   r7, 0(r8)
147  l.addi  r5, r5, -1
148  l.addi  r7, r7, -1
149  l.sw    0(r6), r5
150  l.sw    0(r8), r7
151
152  /* Check if _ISR_Nest_level > 0 */
153  l.sfgtui r5, 0
154  l.bf exception_frame_restore
155  l.nop
156
157  /* Check if _Thread_Dispatch_disable_level > 0 */
158  l.sfgtui r7, 0
159  l.bf exception_frame_restore
160  l.nop
161
162  /* Check if dispatch needed */
163  l.movhi r31, hi(DISPATCH_NEEDED)
164  l.ori   r31, r31, lo(DISPATCH_NEEDED)
165  l.lwz   r31, 0(r31)
166  l.sfeq  r31, r0
167  l.bf    exception_frame_restore
168  l.nop
169
170  l.movhi r13, hi(_Thread_Dispatch)
171  l.ori   r13, r13, lo(_Thread_Dispatch)
172  l.jalr  r13
173  l.nop
174
175 SYM(exception_frame_restore):
176
177  /* Exception level related registers */
178
179  /* EPCR */
180  l.lwz  r13,  128(r1)
181  l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
182
183  /* EEAR */
184  l.lwz  r13,  132(r1)
185  l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
186
187  /* ESR */
188  l.lwz  r13,  136(r1)
189  l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
190
191  l.lwz  r2,  8(r1)
192  l.lwz  r3,  12(r1)
193  l.lwz  r4,  16(r1)
194  l.lwz  r5,  20(r1)
195  l.lwz  r6,  24(r1)
196  l.lwz  r7,  28(r1)
197  l.lwz  r8,  32(r1)
198  l.lwz  r9,  36(r1)
199  l.lwz  r10, 40(r1)
200  l.lwz  r11, 44(r1)
201  l.lwz  r12, 48(r1)
202  l.lwz  r13, 52(r1)
203  l.lwz  r14, 56(r1)
204  l.lwz  r15, 60(r1)
205  l.lwz  r16, 64(r1)
206  l.lwz  r17, 68(r1)
207  l.lwz  r18, 72(r1)
208  l.lwz  r19, 76(r1)
209  l.lwz  r20, 80(r1)
210  l.lwz  r21, 84(r1)
211  l.lwz  r22, 88(r1)
212  l.lwz  r23, 92(r1)
213  l.lwz  r24, 96(r1)
214  l.lwz  r25, 100(r1)
215  l.lwz  r26, 104(r1)
216  l.lwz  r27, 108(r1)
217  l.lwz  r28, 112(r1)
218  l.lwz  r29, 116(r1)
219  l.lwz  r30, 120(r1)
220  l.lwz  r31, 124(r1)
221
222  /* Unwind exception frame */
223  l.addi r1, r1, 140
224
225  /* Red-zone */
226  l.addi r1, r1, 200
227
228  l.rfe
229  l.nop
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