[94d45f6] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup ScoreCPU |
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| 5 | * |
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| 6 | * @brief OR1K exception support implementation. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.org/license/LICENSE. |
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| 15 | * |
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| 16 | */ |
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| 17 | |
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| 18 | #ifdef HAVE_CONFIG_H |
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| 19 | #include "config.h" |
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| 20 | #endif |
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| 21 | |
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| 22 | #include <rtems/asm.h> |
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| 23 | #include <rtems/score/percpu.h> |
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| 24 | #include "rtems/score/or1k-utility.h" |
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| 25 | |
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| 26 | .align 4 |
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| 27 | .text |
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| 28 | PUBLIC(_ISR_Handler) |
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| 29 | .type _ISR_Handler,@function |
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| 30 | |
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| 31 | SYM(_ISR_Handler): |
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| 32 | |
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| 33 | l.addi r1, r1, -140 |
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| 34 | |
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| 35 | l.sw 8(r1),r2 |
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| 36 | /* r3 is saved by BSP exception handler */ |
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| 37 | l.sw 16(r1),r4 |
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| 38 | l.sw 20(r1),r5 |
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| 39 | l.sw 24(r1),r6 |
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| 40 | l.sw 28(r1),r7 |
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| 41 | l.sw 32(r1),r8 |
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| 42 | l.sw 36(r1),r9 |
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| 43 | l.sw 40(r1),r10 |
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| 44 | l.sw 44(r1),r11 |
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| 45 | l.sw 48(r1),r12 |
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| 46 | l.sw 52(r1),r13 |
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| 47 | l.sw 56(r1),r14 |
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| 48 | l.sw 60(r1),r15 |
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| 49 | l.sw 64(r1),r16 |
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| 50 | l.sw 68(r1),r17 |
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| 51 | l.sw 72(r1),r18 |
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| 52 | l.sw 76(r1),r19 |
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| 53 | l.sw 80(r1),r20 |
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| 54 | l.sw 84(r1),r21 |
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| 55 | l.sw 88(r1),r22 |
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| 56 | l.sw 92(r1),r23 |
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| 57 | l.sw 96(r1),r24 |
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| 58 | l.sw 100(r1),r25 |
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| 59 | l.sw 104(r1),r26 |
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| 60 | l.sw 108(r1),r27 |
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| 61 | l.sw 112(r1),r28 |
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| 62 | l.sw 116(r1),r29 |
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| 63 | l.sw 120(r1),r30 |
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| 64 | l.sw 124(r1),r31 |
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| 65 | |
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| 66 | /* Exception level related registers */ |
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| 67 | |
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| 68 | /* EPCR */ |
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| 69 | l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0 |
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| 70 | l.sw 128(r1), r13 /* epcr */ |
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| 71 | |
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| 72 | /* EEAR */ |
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| 73 | l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0 |
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| 74 | l.sw 132(r1), r13 /* eear */ |
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| 75 | |
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| 76 | /* ESR */ |
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| 77 | l.mfspr r13, r0, CPU_OR1K_SPR_ESR0 |
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| 78 | l.sw 136(r1), r13 /* esr */ |
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| 79 | |
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| 80 | /* Increment nesting level */ |
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| 81 | l.movhi r6, hi(ISR_NEST_LEVEL) |
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| 82 | l.ori r6, r6, lo(ISR_NEST_LEVEL) |
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| 83 | |
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| 84 | /* Disable multitasking */ |
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| 85 | l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL) |
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| 86 | l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL) |
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| 87 | |
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| 88 | l.lwz r5, 0(r6) |
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| 89 | l.lwz r7, 0(r8) |
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| 90 | l.addi r5, r5, 1 |
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| 91 | l.addi r7, r7, 1 |
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| 92 | l.sw 0(r6), r5 |
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| 93 | l.sw 0(r8), r7 |
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| 94 | |
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| 95 | /* Save interrupted task stack pointer */ |
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| 96 | l.addi r4, r1, 144 |
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| 97 | l.sw 4(r1), r4 |
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| 98 | |
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| 99 | /* Save interrupted task r3 (first arg) value */ |
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| 100 | l.addi r4, r1, 140 |
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| 101 | l.lwz r4, 0(r4) |
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| 102 | l.sw 12(r1), r4 |
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| 103 | |
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| 104 | /* Keep r1 (Exception frame address) in r14 */ |
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| 105 | l.add r14, r1, r0 |
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| 106 | |
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| 107 | /* Call the exception handler from vector table */ |
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| 108 | |
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| 109 | /* First function arg for C handler is vector number, |
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| 110 | * and the second is a pointer to exception frame. |
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| 111 | */ |
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| 112 | l.add r13, r3, r0 |
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| 113 | l.add r4, r1, r0 |
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| 114 | l.slli r13, r13, 2 |
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| 115 | l.addi r13, r13, lo(bsp_start_vector_table_begin) |
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| 116 | l.lwz r13, 0(r13) |
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| 117 | |
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| 118 | /* Do not switch stacks if we are in a nested interrupt. At |
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| 119 | * this point r5 should be holding ISR_NEST_LEVEL value. |
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| 120 | */ |
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| 121 | l.sfgtui r5, 2 |
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| 122 | l.bf jump_to_c_handler |
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| 123 | l.nop |
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| 124 | |
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| 125 | /* Switch to RTEMS dedicated interrupt stack */ |
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| 126 | l.movhi r1, hi(INTERRUPT_STACK_HIGH) |
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| 127 | l.ori r1, r1, lo(INTERRUPT_STACK_HIGH) |
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| 128 | l.lwz r1, 0(r1) |
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| 129 | |
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| 130 | jump_to_c_handler: |
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| 131 | l.jalr r13 |
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| 132 | l.nop |
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| 133 | |
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| 134 | /* Switch back to the interrupted task stack */ |
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| 135 | l.add r1, r14, r0 |
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| 136 | |
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| 137 | /* Check if dispatch needed */ |
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| 138 | l.movhi r31, hi(DISPATCH_NEEDED) |
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| 139 | l.ori r31, r31, lo(DISPATCH_NEEDED) |
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| 140 | l.lwz r31, 0(r31) |
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| 141 | l.sfeq r31, r0 |
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| 142 | l.bf exception_frame_restore |
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| 143 | l.nop |
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| 144 | |
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| 145 | l.movhi r13, hi(_Thread_Dispatch) |
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| 146 | l.ori r13, r13, lo(_Thread_Dispatch) |
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| 147 | l.jalr r13 |
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| 148 | l.nop |
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| 149 | |
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| 150 | SYM(exception_frame_restore): |
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| 151 | |
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| 152 | /* Exception level related registers */ |
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| 153 | |
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| 154 | /* EPCR */ |
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| 155 | l.lwz r13, 128(r1) |
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| 156 | l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0 |
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| 157 | |
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| 158 | /* EEAR */ |
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| 159 | l.lwz r13, 132(r1) |
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| 160 | l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0 |
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| 161 | |
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| 162 | /* ESR */ |
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| 163 | l.lwz r13, 136(r1) |
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| 164 | l.mtspr r0, r13, CPU_OR1K_SPR_ESR0 |
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| 165 | |
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| 166 | /* Increment nesting level */ |
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| 167 | l.movhi r6, hi(ISR_NEST_LEVEL) |
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| 168 | l.ori r6, r6, lo(ISR_NEST_LEVEL) |
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| 169 | |
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| 170 | /* Disable multitasking */ |
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| 171 | l.movhi r8, hi(THREAD_DISPATCH_DISABLE_LEVEL) |
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| 172 | l.ori r8, r8, lo(THREAD_DISPATCH_DISABLE_LEVEL) |
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| 173 | |
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| 174 | l.lwz r5, 0(r6) |
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| 175 | l.lwz r7, 0(r8) |
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| 176 | l.addi r5, r5, -1 |
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| 177 | l.addi r7, r7, -1 |
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| 178 | l.sw 0(r6), r5 |
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| 179 | l.sw 0(r8), r7 |
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| 180 | |
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| 181 | l.lwz r2, 8(r1) |
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| 182 | l.lwz r3, 12(r1) |
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| 183 | l.lwz r4, 16(r1) |
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| 184 | l.lwz r5, 20(r1) |
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| 185 | l.lwz r6, 24(r1) |
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| 186 | l.lwz r7, 28(r1) |
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| 187 | l.lwz r8, 32(r1) |
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| 188 | l.lwz r9, 36(r1) |
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| 189 | l.lwz r10, 40(r1) |
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| 190 | l.lwz r11, 44(r1) |
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| 191 | l.lwz r12, 48(r1) |
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| 192 | l.lwz r13, 52(r1) |
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| 193 | l.lwz r14, 56(r1) |
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| 194 | l.lwz r15, 60(r1) |
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| 195 | l.lwz r16, 64(r1) |
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| 196 | l.lwz r17, 68(r1) |
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| 197 | l.lwz r18, 72(r1) |
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| 198 | l.lwz r19, 76(r1) |
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| 199 | l.lwz r20, 80(r1) |
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| 200 | l.lwz r21, 84(r1) |
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| 201 | l.lwz r22, 88(r1) |
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| 202 | l.lwz r23, 92(r1) |
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| 203 | l.lwz r24, 96(r1) |
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| 204 | l.lwz r25, 100(r1) |
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| 205 | l.lwz r26, 104(r1) |
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| 206 | l.lwz r27, 108(r1) |
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| 207 | l.lwz r28, 112(r1) |
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| 208 | l.lwz r29, 116(r1) |
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| 209 | l.lwz r30, 120(r1) |
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[23e8f3d] | 210 | l.lwz r31, 124(r1) |
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[94d45f6] | 211 | |
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| 212 | l.addi r1, r1, 140 |
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| 213 | |
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| 214 | l.addi r1, r1, 4 |
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| 215 | |
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| 216 | l.rfe |
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| 217 | l.nop |
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