source: rtems/cpukit/score/cpu/or1k/or1k-context-switch.S @ 94d45f6

4.115
Last change on this file since 94d45f6 was 94d45f6, checked in by Hesham ALMatary <heshamelmatary@…>, on Aug 12, 2014 at 3:57:42 PM

Add support for OpenRISC - Fixed issues

This work is based on the old or32 port (that has been
removed back in 2005) authored by Chris Ziomkowski. The patch includes the
basic functions every port should implement like: context switch, exception
handling, OpenRISC ABI and machine definitions and configurations.

  • Property mode set to 100644
File size: 2.2 KB
Line 
1/*
2 * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com>
3 *
4 * The license and distribution terms for this file may be
5 * found in the file LICENSE in this distribution or at
6 * http://www.rtems.org/license/LICENSE.
7 */
8
9#ifdef HAVE_CONFIG_H
10  #include "config.h"
11#endif
12
13#include <rtems/asm.h>
14#include "rtems/score/or1k-utility.h"
15
16.text
17.align 4
18
19PUBLIC(_CPU_Context_switch)
20PUBLIC(_CPU_Context_restore)
21PUBLIC(_CPU_Context_restore_fp)
22PUBLIC(_CPU_Context_save_fp)
23
24SYM(_CPU_Context_switch):
25  l.sw  0(r3),r1
26  l.sw  4(r3),r2
27  l.sw  8(r3),r3
28  l.sw  12(r3),r4
29  l.sw  16(r3),r5
30  l.sw  20(r3),r6
31  l.sw  24(r3),r7
32  l.sw  28(r3),r8
33  l.sw  32(r3),r9
34  /* Skip r10 as it's preserved to be used by TLS */
35  /* The following set if registers are preserved across function calls */
36  l.sw  52(r3),r14
37  l.sw  60(r3),r16
38  l.sw  68(r3),r18
39  l.sw  76(r3),r20
40  l.sw  84(r3),r22
41  l.sw  92(r3),r24
42  l.sw  100(r3),r26
43  l.sw  108(r3),r28
44  l.sw  116(r3),r30
45
46  /* Supervision Register */
47  l.mfspr r13,r0, CPU_OR1K_SPR_SR
48  l.sw  124(r3),r13
49
50  /* EPCR */
51  l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0
52  l.sw  128(r3), r13 /* epcr */
53
54  /* EEAR */
55  l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0
56  l.sw  132(r3), r13 /* eear */
57
58  /* ESR */
59  l.mfspr r13, r0, CPU_OR1K_SPR_ESR0
60  l.sw  136(r3), r13  /* esr */
61
62SYM(restore):
63  l.lwz   r13,124(r4)
64  l.mtspr r0,r13, CPU_OR1K_SPR_SR
65
66  /* Exception level related registers */
67
68  /* EPCR */
69  l.lwz  r13,  128(r4)
70  l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0
71
72  /* EEAR */
73  l.lwz  r13,  132(r4)
74  l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0
75
76  /* ESR */
77  l.lwz  r13,  136(r4)
78  l.mtspr r0, r13, CPU_OR1K_SPR_ESR0
79
80  l.lwz  r1,0(r4)
81  l.lwz  r2,4(r4)
82  l.lwz  r3,8(r4)
83  /* Skip r4 as it contains the current buffer address */
84  l.lwz  r5,16(r4)
85  l.lwz  r6,20(r4)
86  l.lwz  r7,24(r4)
87  l.lwz  r8,28(r4)
88  l.lwz  r9,32(r4)
89  l.lwz  r14,52(r4)
90  l.lwz  r16,60(r4)
91  l.lwz  r18,68(r4)
92  l.lwz  r20,76(r4)
93  l.lwz  r22,84(r4)
94  l.lwz  r24,92(r4)
95  l.lwz  r26,100(r4)
96  l.lwz  r28,108(r4)
97  l.lwz  r30,116(r4)
98
99  l.lwz  r4,12(r4)
100
101  l.jr   r9
102  l.nop
103
104 SYM(_CPU_Context_restore):
105  l.add   r4,r3,r0
106  l.add   r13,r0,r0
107  l.j     restore
108  l.nop
109
110 SYM(_CPU_Context_restore_fp):
111  l.nop
112
113 SYM(_CPU_Context_save_fp):
114  l.nop
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