1 | /* |
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2 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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3 | * |
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4 | * The license and distribution terms for this file may be |
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5 | * found in the file LICENSE in this distribution or at |
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6 | * http://www.rtems.org/license/LICENSE. |
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7 | */ |
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8 | |
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9 | #ifdef HAVE_CONFIG_H |
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10 | #include "config.h" |
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11 | #endif |
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12 | |
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13 | #include <rtems/asm.h> |
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14 | #include "rtems/score/or1k-utility.h" |
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15 | |
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16 | .text |
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17 | .align 4 |
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18 | |
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19 | PUBLIC(_CPU_Context_switch) |
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20 | PUBLIC(_CPU_Context_restore) |
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21 | PUBLIC(_CPU_Context_restore_fp) |
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22 | PUBLIC(_CPU_Context_save_fp) |
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23 | |
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24 | SYM(_CPU_Context_switch): |
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25 | l.sw 0(r3),r1 |
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26 | l.sw 4(r3),r2 |
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27 | l.sw 8(r3),r3 |
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28 | l.sw 12(r3),r4 |
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29 | l.sw 16(r3),r5 |
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30 | l.sw 20(r3),r6 |
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31 | l.sw 24(r3),r7 |
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32 | l.sw 28(r3),r8 |
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33 | l.sw 32(r3),r9 |
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34 | /* Skip r10 as it's preserved to be used by TLS */ |
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35 | /* The following set if registers are preserved across function calls */ |
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36 | l.sw 52(r3),r14 |
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37 | l.sw 60(r3),r16 |
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38 | l.sw 68(r3),r18 |
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39 | l.sw 76(r3),r20 |
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40 | l.sw 84(r3),r22 |
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41 | l.sw 92(r3),r24 |
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42 | l.sw 100(r3),r26 |
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43 | l.sw 108(r3),r28 |
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44 | l.sw 116(r3),r30 |
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45 | |
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46 | /* Supervision Register */ |
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47 | l.mfspr r13,r0, CPU_OR1K_SPR_SR |
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48 | l.sw 124(r3),r13 |
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49 | |
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50 | /* EPCR */ |
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51 | l.mfspr r13, r0, CPU_OR1K_SPR_EPCR0 |
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52 | l.sw 128(r3), r13 /* epcr */ |
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53 | |
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54 | /* EEAR */ |
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55 | l.mfspr r13, r0, CPU_OR1K_SPR_EEAR0 |
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56 | l.sw 132(r3), r13 /* eear */ |
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57 | |
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58 | /* ESR */ |
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59 | l.mfspr r13, r0, CPU_OR1K_SPR_ESR0 |
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60 | l.sw 136(r3), r13 /* esr */ |
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61 | |
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62 | SYM(restore): |
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63 | l.lwz r13,124(r4) |
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64 | l.mtspr r0,r13, CPU_OR1K_SPR_SR |
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65 | |
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66 | /* Exception level related registers */ |
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67 | |
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68 | /* EPCR */ |
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69 | l.lwz r13, 128(r4) |
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70 | l.mtspr r0, r13, CPU_OR1K_SPR_EPCR0 |
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71 | |
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72 | /* EEAR */ |
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73 | l.lwz r13, 132(r4) |
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74 | l.mtspr r0, r13, CPU_OR1K_SPR_EEAR0 |
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75 | |
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76 | /* ESR */ |
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77 | l.lwz r13, 136(r4) |
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78 | l.mtspr r0, r13, CPU_OR1K_SPR_ESR0 |
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79 | |
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80 | l.lwz r1,0(r4) |
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81 | l.lwz r2,4(r4) |
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82 | l.lwz r3,8(r4) |
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83 | /* Skip r4 as it contains the current buffer address */ |
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84 | l.lwz r5,16(r4) |
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85 | l.lwz r6,20(r4) |
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86 | l.lwz r7,24(r4) |
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87 | l.lwz r8,28(r4) |
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88 | l.lwz r9,32(r4) |
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89 | l.lwz r14,52(r4) |
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90 | l.lwz r16,60(r4) |
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91 | l.lwz r18,68(r4) |
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92 | l.lwz r20,76(r4) |
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93 | l.lwz r22,84(r4) |
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94 | l.lwz r24,92(r4) |
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95 | l.lwz r26,100(r4) |
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96 | l.lwz r28,108(r4) |
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97 | l.lwz r30,116(r4) |
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98 | |
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99 | l.lwz r4,12(r4) |
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100 | |
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101 | l.jr r9 |
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102 | l.nop |
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103 | |
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104 | SYM(_CPU_Context_restore): |
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105 | l.add r4,r3,r0 |
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106 | l.add r13,r0,r0 |
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107 | l.j restore |
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108 | l.nop |
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109 | |
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110 | SYM(_CPU_Context_restore_fp): |
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111 | l.nop |
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112 | |
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113 | SYM(_CPU_Context_save_fp): |
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114 | l.nop |
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