1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | */ |
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4 | |
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5 | /* |
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6 | * This include file contains macros pertaining to the Opencores |
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7 | * or1k processor family. |
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8 | * |
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9 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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10 | * COPYRIGHT (c) 1989-1999. |
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11 | * On-Line Applications Research Corporation (OAR). |
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12 | * |
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13 | * The license and distribution terms for this file may be |
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14 | * found in the file LICENSE in this distribution or at |
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15 | * http://www.rtems.org/license/LICENSE. |
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16 | * |
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17 | * This file adapted from no_cpu example of the RTEMS distribution. |
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18 | * The body has been modified for the Opencores OR1k implementation by |
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19 | * Chris Ziomkowski. <chris@asics.ws> |
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20 | * |
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21 | */ |
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22 | |
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23 | #ifndef _OR1K_CPU_H |
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24 | #define _OR1K_CPU_H |
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25 | |
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26 | #ifdef __cplusplus |
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27 | extern "C" { |
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28 | #endif |
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29 | |
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30 | |
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31 | #include <rtems/score/or1k.h> /* pick up machine definitions */ |
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32 | #include <rtems/score/or1k-utility.h> |
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33 | #include <rtems/score/basedefs.h> |
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34 | #ifndef ASM |
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35 | #include <rtems/bspIo.h> |
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36 | #include <stdint.h> |
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37 | #include <stdio.h> /* for printk */ |
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38 | #endif |
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39 | |
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40 | /* conditional compilation parameters */ |
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41 | |
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42 | /* |
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43 | * Does RTEMS manage a dedicated interrupt stack in software? |
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44 | * |
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45 | * If TRUE, then a stack is allocated in _ISR_Handler_initialization. |
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46 | * If FALSE, nothing is done. |
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47 | * |
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48 | * If the CPU supports a dedicated interrupt stack in hardware, |
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49 | * then it is generally the responsibility of the BSP to allocate it |
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50 | * and set it up. |
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51 | * |
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52 | * If the CPU does not support a dedicated interrupt stack, then |
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53 | * the porter has two options: (1) execute interrupts on the |
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54 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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55 | * interrupt stack. |
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56 | * |
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57 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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58 | * |
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59 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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60 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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61 | * possible that both are FALSE for a particular CPU. Although it |
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62 | * is unclear what that would imply about the interrupt processing |
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63 | * procedure on that CPU. |
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64 | * |
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65 | * Currently, for or1k port, _ISR_Handler is responsible for switching to |
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66 | * RTEMS dedicated interrupt task. |
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67 | * |
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68 | */ |
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69 | |
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70 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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71 | |
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72 | /* |
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73 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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74 | * |
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75 | * If TRUE, then it must be installed during initialization. |
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76 | * If FALSE, then no installation is performed. |
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77 | * |
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78 | * If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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79 | * |
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80 | * Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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81 | * CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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82 | * possible that both are FALSE for a particular CPU. Although it |
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83 | * is unclear what that would imply about the interrupt processing |
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84 | * procedure on that CPU. |
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85 | * |
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86 | */ |
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87 | |
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88 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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89 | |
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90 | /* |
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91 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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92 | * |
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93 | * If TRUE, then the memory is allocated during initialization. |
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94 | * If FALSE, then the memory is allocated during initialization. |
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95 | * |
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96 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE |
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97 | * or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE. |
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98 | * |
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99 | */ |
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100 | |
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101 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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102 | |
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103 | /* |
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104 | * Does the RTEMS invoke the user's ISR with the vector number and |
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105 | * a pointer to the saved interrupt frame (1) or just the vector |
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106 | * number (0)? |
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107 | * |
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108 | */ |
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109 | |
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110 | #define CPU_ISR_PASSES_FRAME_POINTER TRUE |
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111 | |
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112 | /* |
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113 | * Does the CPU have hardware floating point? |
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114 | * |
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115 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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116 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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117 | * |
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118 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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119 | * the answer is TRUE. |
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120 | * |
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121 | * The macro name "OR1K_HAS_FPU" should be made CPU specific. |
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122 | * It indicates whether or not this CPU model has FP support. For |
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123 | * example, it would be possible to have an i386_nofp CPU model |
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124 | * which set this to false to indicate that you have an i386 without |
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125 | * an i387 and wish to leave floating point support out of RTEMS. |
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126 | * |
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127 | * The CPU_SOFTWARE_FP is used to indicate whether or not there |
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128 | * is software implemented floating point that must be context |
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129 | * switched. The determination of whether or not this applies |
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130 | * is very tool specific and the state saved/restored is also |
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131 | * compiler specific. |
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132 | * |
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133 | * Or1k Specific Information: |
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134 | * |
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135 | * At this time there are no implementations of Or1k that are |
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136 | * expected to implement floating point. More importantly, the |
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137 | * floating point architecture is expected to change significantly |
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138 | * before such chips are fabricated. |
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139 | */ |
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140 | |
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141 | #define CPU_HARDWARE_FP FALSE |
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142 | #define CPU_SOFTWARE_FP FALSE |
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143 | |
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144 | /* |
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145 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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146 | * |
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147 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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148 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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149 | * |
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150 | * If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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151 | * |
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152 | */ |
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153 | |
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154 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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155 | |
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156 | /* |
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157 | * Should the IDLE task have a floating point context? |
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158 | * |
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159 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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160 | * and it has a floating point context which is switched in and out. |
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161 | * If FALSE, then the IDLE task does not have a floating point context. |
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162 | * |
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163 | * Setting this to TRUE negatively impacts the time required to preempt |
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164 | * the IDLE task from an interrupt because the floating point context |
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165 | * must be saved as part of the preemption. |
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166 | * |
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167 | */ |
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168 | |
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169 | #define CPU_IDLE_TASK_IS_FP FALSE |
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170 | |
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171 | /* |
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172 | * Should the saving of the floating point registers be deferred |
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173 | * until a context switch is made to another different floating point |
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174 | * task? |
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175 | * |
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176 | * If TRUE, then the floating point context will not be stored until |
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177 | * necessary. It will remain in the floating point registers and not |
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178 | * disturned until another floating point task is switched to. |
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179 | * |
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180 | * If FALSE, then the floating point context is saved when a floating |
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181 | * point task is switched out and restored when the next floating point |
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182 | * task is restored. The state of the floating point registers between |
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183 | * those two operations is not specified. |
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184 | * |
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185 | * If the floating point context does NOT have to be saved as part of |
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186 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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187 | * |
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188 | * Setting this flag to TRUE results in using a different algorithm |
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189 | * for deciding when to save and restore the floating point context. |
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190 | * The deferred FP switch algorithm minimizes the number of times |
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191 | * the FP context is saved and restored. The FP context is not saved |
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192 | * until a context switch is made to another, different FP task. |
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193 | * Thus in a system with only one FP task, the FP context will never |
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194 | * be saved or restored. |
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195 | * |
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196 | */ |
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197 | |
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198 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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199 | |
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200 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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201 | |
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202 | /* |
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203 | * Does this port provide a CPU dependent IDLE task implementation? |
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204 | * |
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205 | * If TRUE, then the routine _CPU_Thread_Idle_body |
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206 | * must be provided and is the default IDLE thread body instead of |
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207 | * _CPU_Thread_Idle_body. |
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208 | * |
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209 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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210 | * not provide one. |
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211 | * |
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212 | * This is intended to allow for supporting processors which have |
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213 | * a low power or idle mode. When the IDLE thread is executed, then |
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214 | * the CPU can be powered down. |
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215 | * |
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216 | * The order of precedence for selecting the IDLE thread body is: |
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217 | * |
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218 | * 1. BSP provided |
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219 | * 2. CPU dependent (if provided) |
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220 | * 3. generic (if no BSP and no CPU dependent) |
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221 | * |
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222 | */ |
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223 | |
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224 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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225 | |
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226 | /* |
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227 | * Does the stack grow up (toward higher addresses) or down |
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228 | * (toward lower addresses)? |
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229 | * |
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230 | * If TRUE, then the grows upward. |
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231 | * If FALSE, then the grows toward smaller addresses. |
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232 | * |
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233 | */ |
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234 | |
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235 | #define CPU_STACK_GROWS_UP FALSE |
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236 | |
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237 | /* FIXME: Is this the right value? */ |
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238 | #define CPU_CACHE_LINE_BYTES 32 |
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239 | |
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240 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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241 | |
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242 | /* |
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243 | * Define what is required to specify how the network to host conversion |
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244 | * routines are handled. |
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245 | * |
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246 | * Or1k Specific Information: |
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247 | * |
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248 | * This version of RTEMS is designed specifically to run with |
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249 | * big endian architectures. If you want little endian, you'll |
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250 | * have to make the appropriate adjustments here and write |
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251 | * efficient routines for byte swapping. The Or1k architecture |
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252 | * doesn't do this very well. |
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253 | */ |
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254 | |
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255 | #define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE |
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256 | |
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257 | /* |
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258 | * The following defines the number of bits actually used in the |
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259 | * interrupt field of the task mode. How those bits map to the |
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260 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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261 | * |
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262 | */ |
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263 | |
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264 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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265 | |
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266 | /* |
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267 | * Processor defined structures required for cpukit/score. |
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268 | */ |
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269 | |
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270 | |
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271 | /* |
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272 | * Contexts |
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273 | * |
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274 | * Generally there are 2 types of context to save. |
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275 | * 1. Interrupt registers to save |
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276 | * 2. Task level registers to save |
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277 | * |
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278 | * This means we have the following 3 context items: |
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279 | * 1. task level context stuff:: Context_Control |
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280 | * 2. floating point task stuff:: Context_Control_fp |
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281 | * 3. special interrupt level context :: Context_Control_interrupt |
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282 | * |
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283 | * On some processors, it is cost-effective to save only the callee |
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284 | * preserved registers during a task context switch. This means |
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285 | * that the ISR code needs to save those registers which do not |
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286 | * persist across function calls. It is not mandatory to make this |
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287 | * distinctions between the caller/callee saves registers for the |
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288 | * purpose of minimizing context saved during task switch and on interrupts. |
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289 | * If the cost of saving extra registers is minimal, simplicity is the |
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290 | * choice. Save the same context on interrupt entry as for tasks in |
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291 | * this case. |
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292 | * |
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293 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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294 | * care should be used in designing the context area. |
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295 | * |
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296 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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297 | * structure will not be used or it simply consist of an array of a |
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298 | * fixed number of bytes. This is done when the floating point context |
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299 | * is dumped by a "FP save context" type instruction and the format |
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300 | * is not really defined by the CPU. In this case, there is no need |
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301 | * to figure out the exact format -- only the size. Of course, although |
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302 | * this is enough information for RTEMS, it is probably not enough for |
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303 | * a debugger such as gdb. But that is another problem. |
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304 | * |
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305 | * |
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306 | */ |
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307 | #ifndef ASM |
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308 | #ifdef OR1K_64BIT_ARCH |
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309 | #define or1kreg uint64_t |
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310 | #else |
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311 | #define or1kreg uint32_t |
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312 | #endif |
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313 | |
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314 | typedef struct { |
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315 | uint32_t r1; /* Stack pointer */ |
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316 | uint32_t r2; /* Frame pointer */ |
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317 | uint32_t r3; |
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318 | uint32_t r4; |
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319 | uint32_t r5; |
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320 | uint32_t r6; |
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321 | uint32_t r7; |
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322 | uint32_t r8; |
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323 | uint32_t r9; |
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324 | uint32_t r10; |
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325 | uint32_t r11; |
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326 | uint32_t r12; |
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327 | uint32_t r13; |
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328 | uint32_t r14; |
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329 | uint32_t r15; |
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330 | uint32_t r16; |
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331 | uint32_t r17; |
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332 | uint32_t r18; |
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333 | uint32_t r19; |
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334 | uint32_t r20; |
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335 | uint32_t r21; |
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336 | uint32_t r22; |
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337 | uint32_t r23; |
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338 | uint32_t r24; |
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339 | uint32_t r25; |
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340 | uint32_t r26; |
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341 | uint32_t r27; |
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342 | uint32_t r28; |
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343 | uint32_t r29; |
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344 | uint32_t r30; |
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345 | uint32_t r31; |
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346 | |
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347 | uint32_t sr; /* Current supervision register non persistent values */ |
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348 | uint32_t epcr; |
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349 | uint32_t eear; |
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350 | uint32_t esr; |
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351 | } Context_Control; |
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352 | |
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353 | #define _CPU_Context_Get_SP( _context ) \ |
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354 | (_context)->r1 |
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355 | |
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356 | typedef struct { |
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357 | /** FPU registers are listed here */ |
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358 | double some_float_register; |
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359 | } Context_Control_fp; |
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360 | |
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361 | typedef Context_Control CPU_Interrupt_frame; |
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362 | |
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363 | /* |
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364 | * The size of the floating point context area. On some CPUs this |
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365 | * will not be a "sizeof" because the format of the floating point |
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366 | * area is not defined -- only the size is. This is usually on |
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367 | * CPUs with a "floating point save context" instruction. |
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368 | * |
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369 | * Or1k Specific Information: |
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370 | * |
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371 | */ |
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372 | |
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373 | #define CPU_CONTEXT_FP_SIZE 0 |
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374 | |
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375 | /* |
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376 | * Amount of extra stack (above minimum stack size) required by |
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377 | * MPCI receive server thread. Remember that in a multiprocessor |
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378 | * system this thread must exist and be able to process all directives. |
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379 | * |
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380 | */ |
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381 | |
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382 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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383 | |
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384 | /* |
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385 | * Should be large enough to run all RTEMS tests. This insures |
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386 | * that a "reasonable" small application should not have any problems. |
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387 | * |
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388 | */ |
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389 | |
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390 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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391 | |
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392 | /* |
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393 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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394 | * alignment does not take into account the requirements for the stack. |
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395 | * |
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396 | */ |
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397 | |
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398 | #define CPU_ALIGNMENT 8 |
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399 | |
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400 | /* |
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401 | * This is defined if the port has a special way to report the ISR nesting |
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402 | * level. Most ports maintain the variable _ISR_Nest_level. |
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403 | */ |
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404 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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405 | |
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406 | /** |
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407 | * Size of a pointer. |
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408 | * |
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409 | * This must be an integer literal that can be used by the assembler. This |
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410 | * value will be used to calculate offsets of structure members. These |
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411 | * offsets will be used in assembler code. |
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412 | */ |
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413 | #define CPU_SIZEOF_POINTER 4 |
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414 | |
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415 | /* |
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416 | * This number corresponds to the byte alignment requirement for the |
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417 | * heap handler. This alignment requirement may be stricter than that |
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418 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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419 | * common for the heap to follow the same alignment requirement as |
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420 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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421 | * then this should be set to CPU_ALIGNMENT. |
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422 | * |
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423 | * NOTE: This does not have to be a power of 2 although it should be |
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424 | * a multiple of 2 greater than or equal to 2. The requirement |
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425 | * to be a multiple of 2 is because the heap uses the least |
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426 | * significant field of the front and back flags to indicate |
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427 | * that a block is in use or free. So you do not want any odd |
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428 | * length blocks really putting length data in that bit. |
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429 | * |
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430 | * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will |
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431 | * have to be greater or equal to than CPU_ALIGNMENT to ensure that |
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432 | * elements allocated from the heap meet all restrictions. |
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433 | * |
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434 | */ |
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435 | |
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436 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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437 | |
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438 | /* |
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439 | * This number corresponds to the byte alignment requirement for memory |
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440 | * buffers allocated by the partition manager. This alignment requirement |
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441 | * may be stricter than that for the data types alignment specified by |
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442 | * CPU_ALIGNMENT. It is common for the partition to follow the same |
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443 | * alignment requirement as CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict |
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444 | * enough for the partition, then this should be set to CPU_ALIGNMENT. |
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445 | * |
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446 | * NOTE: This does not have to be a power of 2. It does have to |
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447 | * be greater or equal to than CPU_ALIGNMENT. |
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448 | * |
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449 | */ |
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450 | |
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451 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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452 | |
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453 | /* |
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454 | * This number corresponds to the byte alignment requirement for the |
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455 | * stack. This alignment requirement may be stricter than that for the |
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456 | * data types alignment specified by CPU_ALIGNMENT. If the CPU_ALIGNMENT |
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457 | * is strict enough for the stack, then this should be set to 0. |
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458 | * |
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459 | * NOTE: This must be a power of 2 either 0 or greater than CPU_ALIGNMENT. |
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460 | * |
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461 | */ |
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462 | |
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463 | #define CPU_STACK_ALIGNMENT 0 |
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464 | |
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465 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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466 | |
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467 | /* ISR handler macros */ |
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468 | |
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469 | /* |
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470 | * Support routine to initialize the RTEMS vector table after it is allocated. |
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471 | * |
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472 | * NO_CPU Specific Information: |
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473 | * |
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474 | * XXX document implementation including references if appropriate |
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475 | */ |
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476 | |
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477 | #define _CPU_Initialize_vectors() |
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478 | |
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479 | /* |
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480 | * Disable all interrupts for an RTEMS critical section. The previous |
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481 | * level is returned in _level. |
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482 | * |
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483 | */ |
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484 | |
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485 | static inline uint32_t or1k_interrupt_disable( void ) |
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486 | { |
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487 | uint32_t sr; |
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488 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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489 | |
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490 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); |
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491 | |
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492 | return sr; |
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493 | } |
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494 | |
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495 | static inline void or1k_interrupt_enable(uint32_t level) |
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496 | { |
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497 | uint32_t sr; |
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498 | |
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499 | /* Enable interrupts and restore rs */ |
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500 | sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; |
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501 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); |
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502 | |
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503 | } |
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504 | |
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505 | #define _CPU_ISR_Disable( _level ) \ |
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506 | _level = or1k_interrupt_disable() |
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507 | |
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508 | |
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509 | /* |
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510 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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511 | * This indicates the end of an RTEMS critical section. The parameter |
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512 | * _level is not modified. |
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513 | * |
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514 | */ |
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515 | |
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516 | #define _CPU_ISR_Enable( _level ) \ |
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517 | or1k_interrupt_enable( _level ) |
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518 | |
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519 | /* |
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520 | * This temporarily restores the interrupt to _level before immediately |
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521 | * disabling them again. This is used to divide long RTEMS critical |
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522 | * sections into two or more parts. The parameter _level is not |
---|
523 | * modified. |
---|
524 | * |
---|
525 | */ |
---|
526 | |
---|
527 | #define _CPU_ISR_Flash( _level ) \ |
---|
528 | do{ \ |
---|
529 | _CPU_ISR_Enable( _level ); \ |
---|
530 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ |
---|
531 | } while(0) |
---|
532 | |
---|
533 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
---|
534 | { |
---|
535 | return ( level & CPU_OR1K_SPR_SR ) != 0; |
---|
536 | } |
---|
537 | |
---|
538 | /* |
---|
539 | * Map interrupt level in task mode onto the hardware that the CPU |
---|
540 | * actually provides. Currently, interrupt levels which do not |
---|
541 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
542 | * it would be nice if these were "mapped" by the application |
---|
543 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
544 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
545 | * This could be used to manage a programmable interrupt controller |
---|
546 | * via the rtems_task_mode directive. |
---|
547 | * |
---|
548 | * The get routine usually must be implemented as a subroutine. |
---|
549 | * |
---|
550 | */ |
---|
551 | |
---|
552 | void _CPU_ISR_Set_level( uint32_t level ); |
---|
553 | |
---|
554 | uint32_t _CPU_ISR_Get_level( void ); |
---|
555 | |
---|
556 | /* end of ISR handler macros */ |
---|
557 | |
---|
558 | /* Context handler macros */ |
---|
559 | |
---|
560 | #define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE |
---|
561 | /* |
---|
562 | * Initialize the context to a state suitable for starting a |
---|
563 | * task after a context restore operation. Generally, this |
---|
564 | * involves: |
---|
565 | * |
---|
566 | * - setting a starting address |
---|
567 | * - preparing the stack |
---|
568 | * - preparing the stack and frame pointers |
---|
569 | * - setting the proper interrupt level in the context |
---|
570 | * - initializing the floating point context |
---|
571 | * |
---|
572 | * This routine generally does not set any unnecessary register |
---|
573 | * in the context. The state of the "general data" registers is |
---|
574 | * undefined at task start time. |
---|
575 | * |
---|
576 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
---|
577 | * point thread. This is typically only used on CPUs where the |
---|
578 | * FPU may be easily disabled by software such as on the SPARC |
---|
579 | * where the PSR contains an enable FPU bit. |
---|
580 | * |
---|
581 | */ |
---|
582 | |
---|
583 | /** |
---|
584 | * @brief Initializes the CPU context. |
---|
585 | * |
---|
586 | * The following steps are performed: |
---|
587 | * - setting a starting address |
---|
588 | * - preparing the stack |
---|
589 | * - preparing the stack and frame pointers |
---|
590 | * - setting the proper interrupt level in the context |
---|
591 | * |
---|
592 | * @param[in] context points to the context area |
---|
593 | * @param[in] stack_area_begin is the low address of the allocated stack area |
---|
594 | * @param[in] stack_area_size is the size of the stack area in bytes |
---|
595 | * @param[in] new_level is the interrupt level for the task |
---|
596 | * @param[in] entry_point is the task's entry point |
---|
597 | * @param[in] is_fp is set to @c true if the task is a floating point task |
---|
598 | * @param[in] tls_area is the thread-local storage (TLS) area |
---|
599 | */ |
---|
600 | void _CPU_Context_Initialize( |
---|
601 | Context_Control *context, |
---|
602 | void *stack_area_begin, |
---|
603 | size_t stack_area_size, |
---|
604 | uint32_t new_level, |
---|
605 | void (*entry_point)( void ), |
---|
606 | bool is_fp, |
---|
607 | void *tls_area |
---|
608 | ); |
---|
609 | |
---|
610 | /* |
---|
611 | * This routine is responsible for somehow restarting the currently |
---|
612 | * executing task. If you are lucky, then all that is necessary |
---|
613 | * is restoring the context. Otherwise, there will need to be |
---|
614 | * a special assembly routine which does something special in this |
---|
615 | * case. Context_Restore should work most of the time. It will |
---|
616 | * not work if restarting self conflicts with the stack frame |
---|
617 | * assumptions of restoring a context. |
---|
618 | * |
---|
619 | */ |
---|
620 | |
---|
621 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
622 | _CPU_Context_restore( (_the_context) ); |
---|
623 | |
---|
624 | /* |
---|
625 | * This routine is responsible to initialize the FP context. |
---|
626 | * |
---|
627 | * The FP area pointer is passed by reference to allow the initial pointer |
---|
628 | * into a floating point context area (used to save the floating point |
---|
629 | * context) to be at an arbitrary place in the floating point context area. |
---|
630 | * |
---|
631 | * This is necessary because some FP units are designed to have |
---|
632 | * their context saved as a stack which grows into lower addresses. |
---|
633 | * Other FP units can be saved by simply moving registers into offsets |
---|
634 | * from the base of the context area. Finally some FP units provide |
---|
635 | * a "dump context" instruction which could fill in from high to low |
---|
636 | * or low to high based on the whim of the CPU designers. |
---|
637 | */ |
---|
638 | #define _CPU_Context_Initialize_fp( _fp_area_p ) \ |
---|
639 | memset( *( _fp_area_p ), 0, CPU_CONTEXT_FP_SIZE ) |
---|
640 | |
---|
641 | /* end of Context handler macros */ |
---|
642 | |
---|
643 | /* Fatal Error manager macros */ |
---|
644 | |
---|
645 | /* |
---|
646 | * This routine copies _error into a known place -- typically a stack |
---|
647 | * location or a register, optionally disables interrupts, and |
---|
648 | * halts/stops the CPU. |
---|
649 | * |
---|
650 | */ |
---|
651 | |
---|
652 | #include <inttypes.h> |
---|
653 | |
---|
654 | #define _CPU_Fatal_halt(_source, _error ) \ |
---|
655 | printk("Fatal Error %d.%" PRId32 " Halted\n",_source, _error); \ |
---|
656 | _OR1KSIM_CPU_Halt(); \ |
---|
657 | for(;;) |
---|
658 | |
---|
659 | /* end of Fatal Error manager macros */ |
---|
660 | |
---|
661 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
662 | |
---|
663 | #endif /* ASM */ |
---|
664 | |
---|
665 | #define CPU_SIZEOF_POINTER 4 |
---|
666 | |
---|
667 | #define CPU_MAXIMUM_PROCESSORS 32 |
---|
668 | |
---|
669 | #ifndef ASM |
---|
670 | typedef struct { |
---|
671 | uint32_t r[32]; |
---|
672 | |
---|
673 | /* The following registers must be saved if we have |
---|
674 | fast context switch disabled and nested interrupt |
---|
675 | levels are enabled. |
---|
676 | */ |
---|
677 | #if !OR1K_FAST_CONTEXT_SWITCH_ENABLED |
---|
678 | uint32_t epcr; /* exception PC register */ |
---|
679 | uint32_t eear; /* exception effective address register */ |
---|
680 | uint32_t esr; /* exception supervision register */ |
---|
681 | #endif |
---|
682 | |
---|
683 | } CPU_Exception_frame; |
---|
684 | |
---|
685 | /** |
---|
686 | * @brief Prints the exception frame via printk(). |
---|
687 | * |
---|
688 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
---|
689 | */ |
---|
690 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
691 | |
---|
692 | |
---|
693 | /* end of Priority handler macros */ |
---|
694 | |
---|
695 | /* functions */ |
---|
696 | |
---|
697 | /* |
---|
698 | * _CPU_Initialize |
---|
699 | * |
---|
700 | * This routine performs CPU dependent initialization. |
---|
701 | * |
---|
702 | */ |
---|
703 | |
---|
704 | void _CPU_Initialize( |
---|
705 | void |
---|
706 | ); |
---|
707 | |
---|
708 | /* |
---|
709 | * _CPU_ISR_install_raw_handler |
---|
710 | * |
---|
711 | * This routine installs a "raw" interrupt handler directly into the |
---|
712 | * processor's vector table. |
---|
713 | * |
---|
714 | */ |
---|
715 | |
---|
716 | void _CPU_ISR_install_raw_handler( |
---|
717 | uint32_t vector, |
---|
718 | proc_ptr new_handler, |
---|
719 | proc_ptr *old_handler |
---|
720 | ); |
---|
721 | |
---|
722 | /* |
---|
723 | * _CPU_ISR_install_vector |
---|
724 | * |
---|
725 | * This routine installs an interrupt vector. |
---|
726 | * |
---|
727 | * NO_CPU Specific Information: |
---|
728 | * |
---|
729 | * XXX document implementation including references if appropriate |
---|
730 | */ |
---|
731 | |
---|
732 | void _CPU_ISR_install_vector( |
---|
733 | uint32_t vector, |
---|
734 | proc_ptr new_handler, |
---|
735 | proc_ptr *old_handler |
---|
736 | ); |
---|
737 | |
---|
738 | /* |
---|
739 | * _CPU_Install_interrupt_stack |
---|
740 | * |
---|
741 | * This routine installs the hardware interrupt stack pointer. |
---|
742 | * |
---|
743 | * NOTE: It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
744 | * is TRUE. |
---|
745 | * |
---|
746 | */ |
---|
747 | |
---|
748 | void _CPU_Install_interrupt_stack( void ); |
---|
749 | |
---|
750 | /* |
---|
751 | * _CPU_Thread_Idle_body |
---|
752 | * |
---|
753 | * This routine is the CPU dependent IDLE thread body. |
---|
754 | * |
---|
755 | * NOTE: It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY |
---|
756 | * is TRUE. |
---|
757 | * |
---|
758 | */ |
---|
759 | |
---|
760 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
761 | |
---|
762 | /* |
---|
763 | * _CPU_Context_switch |
---|
764 | * |
---|
765 | * This routine switches from the run context to the heir context. |
---|
766 | * |
---|
767 | * Or1k Specific Information: |
---|
768 | * |
---|
769 | * Please see the comments in the .c file for a description of how |
---|
770 | * this function works. There are several things to be aware of. |
---|
771 | */ |
---|
772 | |
---|
773 | void _CPU_Context_switch( |
---|
774 | Context_Control *run, |
---|
775 | Context_Control *heir |
---|
776 | ); |
---|
777 | |
---|
778 | /* |
---|
779 | * _CPU_Context_restore |
---|
780 | * |
---|
781 | * This routine is generally used only to restart self in an |
---|
782 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
---|
783 | * |
---|
784 | * NOTE: May be unnecessary to reload some registers. |
---|
785 | * |
---|
786 | */ |
---|
787 | |
---|
788 | void _CPU_Context_restore( |
---|
789 | Context_Control *new_context |
---|
790 | ) RTEMS_NO_RETURN; |
---|
791 | |
---|
792 | /* |
---|
793 | * _CPU_Context_save_fp |
---|
794 | * |
---|
795 | * This routine saves the floating point context passed to it. |
---|
796 | * |
---|
797 | */ |
---|
798 | |
---|
799 | void _CPU_Context_save_fp( |
---|
800 | void **fp_context_ptr |
---|
801 | ); |
---|
802 | |
---|
803 | /* |
---|
804 | * _CPU_Context_restore_fp |
---|
805 | * |
---|
806 | * This routine restores the floating point context passed to it. |
---|
807 | * |
---|
808 | */ |
---|
809 | |
---|
810 | void _CPU_Context_restore_fp( |
---|
811 | void **fp_context_ptr |
---|
812 | ); |
---|
813 | |
---|
814 | /* The following routine swaps the endian format of an unsigned int. |
---|
815 | * It must be static because it is referenced indirectly. |
---|
816 | * |
---|
817 | * This version will work on any processor, but if there is a better |
---|
818 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
819 | * |
---|
820 | * swap least significant two bytes with 16-bit rotate |
---|
821 | * swap upper and lower 16-bits |
---|
822 | * swap most significant two bytes with 16-bit rotate |
---|
823 | * |
---|
824 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
825 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
826 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
827 | * that interrupts would probably have to be disabled to insure that |
---|
828 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
829 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
830 | * endianness for ALL fetches -- both code and data -- so the code |
---|
831 | * will be fetched incorrectly. |
---|
832 | * |
---|
833 | */ |
---|
834 | |
---|
835 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
---|
836 | |
---|
837 | void _CPU_Context_validate( uintptr_t pattern ); |
---|
838 | |
---|
839 | static inline unsigned int CPU_swap_u32( |
---|
840 | unsigned int value |
---|
841 | ) |
---|
842 | { |
---|
843 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
844 | |
---|
845 | byte4 = (value >> 24) & 0xff; |
---|
846 | byte3 = (value >> 16) & 0xff; |
---|
847 | byte2 = (value >> 8) & 0xff; |
---|
848 | byte1 = value & 0xff; |
---|
849 | |
---|
850 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
851 | return( swapped ); |
---|
852 | } |
---|
853 | |
---|
854 | #define CPU_swap_u16( value ) \ |
---|
855 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
856 | |
---|
857 | typedef uint32_t CPU_Counter_ticks; |
---|
858 | |
---|
859 | uint32_t _CPU_Counter_frequency( void ); |
---|
860 | |
---|
861 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
862 | |
---|
863 | CPU_Counter_ticks _CPU_Counter_difference( |
---|
864 | CPU_Counter_ticks second, |
---|
865 | CPU_Counter_ticks first |
---|
866 | ); |
---|
867 | |
---|
868 | /** Type that can store a 32-bit integer or a pointer. */ |
---|
869 | typedef uintptr_t CPU_Uint32ptr; |
---|
870 | |
---|
871 | #endif /* ASM */ |
---|
872 | |
---|
873 | #ifdef __cplusplus |
---|
874 | } |
---|
875 | #endif |
---|
876 | |
---|
877 | #endif |
---|