1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup RTEMScoreCPUor1k |
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5 | */ |
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6 | |
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7 | /* |
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8 | * This include file contains macros pertaining to the Opencores |
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9 | * or1k processor family. |
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10 | * |
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11 | * COPYRIGHT (c) 2014 Hesham ALMatary <heshamelmatary@gmail.com> |
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12 | * COPYRIGHT (c) 1989-1999. |
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13 | * On-Line Applications Research Corporation (OAR). |
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14 | * |
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15 | * The license and distribution terms for this file may be |
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16 | * found in the file LICENSE in this distribution or at |
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17 | * http://www.rtems.org/license/LICENSE. |
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18 | * |
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19 | * This file adapted from no_cpu example of the RTEMS distribution. |
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20 | * The body has been modified for the Opencores OR1k implementation by |
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21 | * Chris Ziomkowski. <chris@asics.ws> |
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22 | * |
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23 | */ |
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24 | |
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25 | #ifndef _OR1K_CPU_H |
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26 | #define _OR1K_CPU_H |
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27 | |
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28 | #ifdef __cplusplus |
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29 | extern "C" { |
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30 | #endif |
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31 | |
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32 | |
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33 | #include <rtems/score/or1k.h> /* pick up machine definitions */ |
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34 | #include <rtems/score/or1k-utility.h> |
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35 | #include <rtems/score/basedefs.h> |
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36 | |
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37 | /* conditional compilation parameters */ |
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38 | |
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39 | /* |
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40 | * Does the RTEMS invoke the user's ISR with the vector number and |
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41 | * a pointer to the saved interrupt frame (1) or just the vector |
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42 | * number (0)? |
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43 | * |
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44 | */ |
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45 | |
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46 | #define CPU_ISR_PASSES_FRAME_POINTER TRUE |
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47 | |
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48 | #define CPU_HARDWARE_FP FALSE |
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49 | |
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50 | #define CPU_SOFTWARE_FP FALSE |
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51 | |
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52 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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53 | |
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54 | #define CPU_IDLE_TASK_IS_FP FALSE |
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55 | |
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56 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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57 | |
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58 | #define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE |
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59 | |
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60 | /* |
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61 | * Does the stack grow up (toward higher addresses) or down |
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62 | * (toward lower addresses)? |
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63 | * |
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64 | * If TRUE, then the grows upward. |
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65 | * If FALSE, then the grows toward smaller addresses. |
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66 | * |
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67 | */ |
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68 | |
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69 | #define CPU_STACK_GROWS_UP FALSE |
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70 | |
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71 | /* FIXME: Is this the right value? */ |
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72 | #define CPU_CACHE_LINE_BYTES 32 |
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73 | |
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74 | #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) |
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75 | |
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76 | /* |
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77 | * The following defines the number of bits actually used in the |
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78 | * interrupt field of the task mode. How those bits map to the |
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79 | * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level(). |
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80 | * |
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81 | */ |
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82 | |
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83 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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84 | |
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85 | /* |
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86 | * Processor defined structures required for cpukit/score. |
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87 | */ |
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88 | |
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89 | |
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90 | /* |
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91 | * Contexts |
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92 | * |
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93 | * Generally there are 2 types of context to save. |
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94 | * 1. Interrupt registers to save |
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95 | * 2. Task level registers to save |
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96 | * |
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97 | * This means we have the following 3 context items: |
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98 | * 1. task level context stuff:: Context_Control |
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99 | * 2. floating point task stuff:: Context_Control_fp |
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100 | * 3. special interrupt level context :: Context_Control_interrupt |
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101 | * |
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102 | * On some processors, it is cost-effective to save only the callee |
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103 | * preserved registers during a task context switch. This means |
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104 | * that the ISR code needs to save those registers which do not |
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105 | * persist across function calls. It is not mandatory to make this |
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106 | * distinctions between the caller/callee saves registers for the |
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107 | * purpose of minimizing context saved during task switch and on interrupts. |
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108 | * If the cost of saving extra registers is minimal, simplicity is the |
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109 | * choice. Save the same context on interrupt entry as for tasks in |
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110 | * this case. |
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111 | * |
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112 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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113 | * care should be used in designing the context area. |
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114 | * |
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115 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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116 | * structure will not be used or it simply consist of an array of a |
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117 | * fixed number of bytes. This is done when the floating point context |
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118 | * is dumped by a "FP save context" type instruction and the format |
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119 | * is not really defined by the CPU. In this case, there is no need |
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120 | * to figure out the exact format -- only the size. Of course, although |
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121 | * this is enough information for RTEMS, it is probably not enough for |
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122 | * a debugger such as gdb. But that is another problem. |
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123 | * |
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124 | * |
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125 | */ |
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126 | #ifndef ASM |
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127 | #ifdef OR1K_64BIT_ARCH |
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128 | #define or1kreg uint64_t |
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129 | #else |
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130 | #define or1kreg uint32_t |
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131 | #endif |
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132 | |
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133 | typedef struct { |
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134 | uint32_t r1; /* Stack pointer */ |
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135 | uint32_t r2; /* Frame pointer */ |
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136 | uint32_t r3; |
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137 | uint32_t r4; |
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138 | uint32_t r5; |
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139 | uint32_t r6; |
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140 | uint32_t r7; |
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141 | uint32_t r8; |
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142 | uint32_t r9; |
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143 | uint32_t r10; |
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144 | uint32_t r11; |
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145 | uint32_t r12; |
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146 | uint32_t r13; |
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147 | uint32_t r14; |
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148 | uint32_t r15; |
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149 | uint32_t r16; |
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150 | uint32_t r17; |
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151 | uint32_t r18; |
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152 | uint32_t r19; |
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153 | uint32_t r20; |
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154 | uint32_t r21; |
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155 | uint32_t r22; |
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156 | uint32_t r23; |
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157 | uint32_t r24; |
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158 | uint32_t r25; |
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159 | uint32_t r26; |
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160 | uint32_t r27; |
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161 | uint32_t r28; |
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162 | uint32_t r29; |
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163 | uint32_t r30; |
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164 | uint32_t r31; |
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165 | |
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166 | uint32_t sr; /* Current supervision register non persistent values */ |
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167 | uint32_t epcr; |
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168 | uint32_t eear; |
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169 | uint32_t esr; |
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170 | } Context_Control; |
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171 | |
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172 | #define _CPU_Context_Get_SP( _context ) \ |
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173 | (_context)->r1 |
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174 | |
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175 | typedef Context_Control CPU_Interrupt_frame; |
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176 | |
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177 | /* |
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178 | * Amount of extra stack (above minimum stack size) required by |
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179 | * MPCI receive server thread. Remember that in a multiprocessor |
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180 | * system this thread must exist and be able to process all directives. |
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181 | * |
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182 | */ |
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183 | |
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184 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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185 | |
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186 | /* |
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187 | * Should be large enough to run all RTEMS tests. This insures |
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188 | * that a "reasonable" small application should not have any problems. |
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189 | * |
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190 | */ |
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191 | |
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192 | #define CPU_STACK_MINIMUM_SIZE 4096 |
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193 | |
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194 | /* |
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195 | * CPU's worst alignment requirement for data types on a byte boundary. This |
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196 | * alignment does not take into account the requirements for the stack. |
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197 | * |
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198 | */ |
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199 | |
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200 | #define CPU_ALIGNMENT 8 |
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201 | |
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202 | /* |
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203 | * This is defined if the port has a special way to report the ISR nesting |
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204 | * level. Most ports maintain the variable _ISR_Nest_level. |
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205 | */ |
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206 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
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207 | |
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208 | /** |
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209 | * Size of a pointer. |
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210 | * |
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211 | * This must be an integer literal that can be used by the assembler. This |
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212 | * value will be used to calculate offsets of structure members. These |
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213 | * offsets will be used in assembler code. |
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214 | */ |
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215 | #define CPU_SIZEOF_POINTER 4 |
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216 | |
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217 | /* |
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218 | * This number corresponds to the byte alignment requirement for the |
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219 | * heap handler. This alignment requirement may be stricter than that |
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220 | * for the data types alignment specified by CPU_ALIGNMENT. It is |
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221 | * common for the heap to follow the same alignment requirement as |
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222 | * CPU_ALIGNMENT. If the CPU_ALIGNMENT is strict enough for the heap, |
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223 | * then this should be set to CPU_ALIGNMENT. |
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224 | * |
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225 | * NOTE: This does not have to be a power of 2 although it should be |
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226 | * a multiple of 2 greater than or equal to 2. The requirement |
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227 | * to be a multiple of 2 is because the heap uses the least |
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228 | * significant field of the front and back flags to indicate |
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229 | * that a block is in use or free. So you do not want any odd |
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230 | * length blocks really putting length data in that bit. |
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231 | * |
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232 | * On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will |
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233 | * have to be greater or equal to than CPU_ALIGNMENT to ensure that |
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234 | * elements allocated from the heap meet all restrictions. |
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235 | * |
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236 | */ |
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237 | |
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238 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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239 | |
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240 | #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT |
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241 | |
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242 | #define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES |
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243 | |
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244 | /* ISR handler macros */ |
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245 | |
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246 | /* |
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247 | * Disable all interrupts for an RTEMS critical section. The previous |
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248 | * level is returned in _level. |
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249 | * |
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250 | */ |
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251 | |
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252 | static inline uint32_t or1k_interrupt_disable( void ) |
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253 | { |
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254 | uint32_t sr; |
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255 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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256 | |
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257 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (sr & ~CPU_OR1K_SPR_SR_IEE)); |
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258 | |
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259 | return sr; |
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260 | } |
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261 | |
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262 | static inline void or1k_interrupt_enable(uint32_t level) |
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263 | { |
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264 | uint32_t sr; |
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265 | |
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266 | /* Enable interrupts and restore rs */ |
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267 | sr = level | CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; |
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268 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); |
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269 | |
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270 | } |
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271 | |
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272 | #define _CPU_ISR_Disable( _level ) \ |
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273 | _level = or1k_interrupt_disable() |
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274 | |
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275 | |
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276 | /* |
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277 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
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278 | * This indicates the end of an RTEMS critical section. The parameter |
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279 | * _level is not modified. |
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280 | * |
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281 | */ |
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282 | |
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283 | #define _CPU_ISR_Enable( _level ) \ |
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284 | or1k_interrupt_enable( _level ) |
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285 | |
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286 | /* |
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287 | * This temporarily restores the interrupt to _level before immediately |
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288 | * disabling them again. This is used to divide long RTEMS critical |
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289 | * sections into two or more parts. The parameter _level is not |
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290 | * modified. |
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291 | * |
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292 | */ |
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293 | |
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294 | #define _CPU_ISR_Flash( _level ) \ |
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295 | do{ \ |
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296 | _CPU_ISR_Enable( _level ); \ |
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297 | _OR1K_mtspr(CPU_OR1K_SPR_SR, (_level & ~CPU_OR1K_SPR_SR_IEE)); \ |
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298 | } while(0) |
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299 | |
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300 | RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level ) |
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301 | { |
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302 | return ( level & CPU_OR1K_SPR_SR ) != 0; |
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303 | } |
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304 | |
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305 | /* |
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306 | * Map interrupt level in task mode onto the hardware that the CPU |
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307 | * actually provides. Currently, interrupt levels which do not |
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308 | * map onto the CPU in a generic fashion are undefined. Someday, |
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309 | * it would be nice if these were "mapped" by the application |
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310 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
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311 | * 8 - 255 would be available for bsp/application specific meaning. |
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312 | * This could be used to manage a programmable interrupt controller |
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313 | * via the rtems_task_mode directive. |
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314 | * |
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315 | * The get routine usually must be implemented as a subroutine. |
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316 | * |
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317 | */ |
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318 | |
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319 | void _CPU_ISR_Set_level( uint32_t level ); |
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320 | |
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321 | uint32_t _CPU_ISR_Get_level( void ); |
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322 | |
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323 | /* end of ISR handler macros */ |
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324 | |
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325 | /* Context handler macros */ |
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326 | |
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327 | #define OR1K_FAST_CONTEXT_SWITCH_ENABLED FALSE |
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328 | /* |
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329 | * Initialize the context to a state suitable for starting a |
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330 | * task after a context restore operation. Generally, this |
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331 | * involves: |
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332 | * |
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333 | * - setting a starting address |
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334 | * - preparing the stack |
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335 | * - preparing the stack and frame pointers |
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336 | * - setting the proper interrupt level in the context |
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337 | * - initializing the floating point context |
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338 | * |
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339 | * This routine generally does not set any unnecessary register |
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340 | * in the context. The state of the "general data" registers is |
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341 | * undefined at task start time. |
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342 | * |
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343 | * NOTE: This is_fp parameter is TRUE if the thread is to be a floating |
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344 | * point thread. This is typically only used on CPUs where the |
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345 | * FPU may be easily disabled by software such as on the SPARC |
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346 | * where the PSR contains an enable FPU bit. |
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347 | * |
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348 | */ |
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349 | |
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350 | /** |
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351 | * @brief Initializes the CPU context. |
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352 | * |
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353 | * The following steps are performed: |
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354 | * - setting a starting address |
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355 | * - preparing the stack |
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356 | * - preparing the stack and frame pointers |
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357 | * - setting the proper interrupt level in the context |
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358 | * |
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359 | * @param[in] context points to the context area |
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360 | * @param[in] stack_area_begin is the low address of the allocated stack area |
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361 | * @param[in] stack_area_size is the size of the stack area in bytes |
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362 | * @param[in] new_level is the interrupt level for the task |
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363 | * @param[in] entry_point is the task's entry point |
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364 | * @param[in] is_fp is set to @c true if the task is a floating point task |
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365 | * @param[in] tls_area is the thread-local storage (TLS) area |
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366 | */ |
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367 | void _CPU_Context_Initialize( |
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368 | Context_Control *context, |
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369 | void *stack_area_begin, |
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370 | size_t stack_area_size, |
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371 | uint32_t new_level, |
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372 | void (*entry_point)( void ), |
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373 | bool is_fp, |
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374 | void *tls_area |
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375 | ); |
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376 | |
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377 | /* |
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378 | * This routine is responsible for somehow restarting the currently |
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379 | * executing task. If you are lucky, then all that is necessary |
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380 | * is restoring the context. Otherwise, there will need to be |
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381 | * a special assembly routine which does something special in this |
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382 | * case. Context_Restore should work most of the time. It will |
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383 | * not work if restarting self conflicts with the stack frame |
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384 | * assumptions of restoring a context. |
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385 | * |
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386 | */ |
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387 | |
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388 | #define _CPU_Context_Restart_self( _the_context ) \ |
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389 | _CPU_Context_restore( (_the_context) ); |
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390 | |
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391 | /* end of Context handler macros */ |
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392 | |
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393 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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394 | |
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395 | #define CPU_USE_LIBC_INIT_FINI_ARRAY TRUE |
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396 | |
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397 | #endif /* ASM */ |
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398 | |
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399 | #define CPU_SIZEOF_POINTER 4 |
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400 | |
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401 | #define CPU_MAXIMUM_PROCESSORS 32 |
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402 | |
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403 | #ifndef ASM |
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404 | typedef struct { |
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405 | uint32_t r[32]; |
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406 | |
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407 | /* The following registers must be saved if we have |
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408 | fast context switch disabled and nested interrupt |
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409 | levels are enabled. |
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410 | */ |
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411 | #if !OR1K_FAST_CONTEXT_SWITCH_ENABLED |
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412 | uint32_t epcr; /* exception PC register */ |
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413 | uint32_t eear; /* exception effective address register */ |
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414 | uint32_t esr; /* exception supervision register */ |
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415 | #endif |
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416 | |
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417 | } CPU_Exception_frame; |
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418 | |
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419 | /** |
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420 | * @brief Prints the exception frame via printk(). |
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421 | * |
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422 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
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423 | */ |
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424 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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425 | |
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426 | |
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427 | /* end of Priority handler macros */ |
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428 | |
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429 | /* functions */ |
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430 | |
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431 | /* |
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432 | * _CPU_Initialize |
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433 | * |
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434 | * This routine performs CPU dependent initialization. |
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435 | * |
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436 | */ |
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437 | |
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438 | void _CPU_Initialize( |
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439 | void |
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440 | ); |
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441 | |
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442 | typedef void ( *CPU_ISR_raw_handler )( uint32_t, CPU_Exception_frame * ); |
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443 | |
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444 | void _CPU_ISR_install_raw_handler( |
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445 | uint32_t vector, |
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446 | CPU_ISR_raw_handler new_handler, |
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447 | CPU_ISR_raw_handler *old_handler |
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448 | ); |
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449 | |
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450 | typedef void ( *CPU_ISR_handler )( uint32_t ); |
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451 | |
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452 | RTEMS_INLINE_ROUTINE void _CPU_ISR_install_vector( |
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453 | uint32_t vector, |
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454 | CPU_ISR_handler new_handler, |
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455 | CPU_ISR_handler *old_handler |
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456 | ) |
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457 | { |
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458 | _CPU_ISR_install_raw_handler( |
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459 | vector, |
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460 | (CPU_ISR_raw_handler) new_handler, |
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461 | (CPU_ISR_raw_handler *) old_handler |
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462 | ); |
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463 | } |
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464 | |
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465 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
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466 | |
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467 | /* |
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468 | * _CPU_Context_switch |
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469 | * |
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470 | * This routine switches from the run context to the heir context. |
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471 | * |
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472 | * Or1k Specific Information: |
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473 | * |
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474 | * Please see the comments in the .c file for a description of how |
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475 | * this function works. There are several things to be aware of. |
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476 | */ |
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477 | |
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478 | void _CPU_Context_switch( |
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479 | Context_Control *run, |
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480 | Context_Control *heir |
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481 | ); |
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482 | |
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483 | /* |
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484 | * _CPU_Context_restore |
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485 | * |
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486 | * This routine is generally used only to restart self in an |
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487 | * efficient manner. It may simply be a label in _CPU_Context_switch. |
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488 | * |
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489 | * NOTE: May be unnecessary to reload some registers. |
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490 | * |
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491 | */ |
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492 | |
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493 | RTEMS_NO_RETURN void _CPU_Context_restore( Context_Control *new_context ); |
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494 | |
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495 | /* |
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496 | * _CPU_Context_save_fp |
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497 | * |
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498 | * This routine saves the floating point context passed to it. |
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499 | * |
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500 | */ |
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501 | |
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502 | void _CPU_Context_save_fp( |
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503 | void **fp_context_ptr |
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504 | ); |
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505 | |
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506 | /* |
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507 | * _CPU_Context_restore_fp |
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508 | * |
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509 | * This routine restores the floating point context passed to it. |
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510 | * |
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511 | */ |
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512 | |
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513 | void _CPU_Context_restore_fp( |
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514 | void **fp_context_ptr |
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515 | ); |
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516 | |
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517 | /* The following routine swaps the endian format of an unsigned int. |
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518 | * It must be static because it is referenced indirectly. |
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519 | * |
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520 | * This version will work on any processor, but if there is a better |
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521 | * way for your CPU PLEASE use it. The most common way to do this is to: |
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522 | * |
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523 | * swap least significant two bytes with 16-bit rotate |
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524 | * swap upper and lower 16-bits |
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525 | * swap most significant two bytes with 16-bit rotate |
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526 | * |
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527 | * Some CPUs have special instructions which swap a 32-bit quantity in |
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528 | * a single instruction (e.g. i486). It is probably best to avoid |
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529 | * an "endian swapping control bit" in the CPU. One good reason is |
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530 | * that interrupts would probably have to be disabled to insure that |
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531 | * an interrupt does not try to access the same "chunk" with the wrong |
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532 | * endian. Another good reason is that on some CPUs, the endian bit |
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533 | * endianness for ALL fetches -- both code and data -- so the code |
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534 | * will be fetched incorrectly. |
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535 | * |
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536 | */ |
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537 | |
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538 | static inline unsigned int CPU_swap_u32( |
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539 | unsigned int value |
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540 | ) |
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541 | { |
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542 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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543 | |
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544 | byte4 = (value >> 24) & 0xff; |
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545 | byte3 = (value >> 16) & 0xff; |
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546 | byte2 = (value >> 8) & 0xff; |
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547 | byte1 = value & 0xff; |
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548 | |
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549 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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550 | return( swapped ); |
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551 | } |
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552 | |
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553 | #define CPU_swap_u16( value ) \ |
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554 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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555 | |
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556 | typedef uint32_t CPU_Counter_ticks; |
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557 | |
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558 | uint32_t _CPU_Counter_frequency( void ); |
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559 | |
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560 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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561 | |
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562 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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563 | CPU_Counter_ticks second, |
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564 | CPU_Counter_ticks first |
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565 | ) |
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566 | { |
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567 | return second - first; |
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568 | } |
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569 | |
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570 | /** Type that can store a 32-bit integer or a pointer. */ |
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571 | typedef uintptr_t CPU_Uint32ptr; |
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572 | |
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573 | #endif /* ASM */ |
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574 | |
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575 | #ifdef __cplusplus |
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576 | } |
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577 | #endif |
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578 | |
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579 | #endif |
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