1 | /* |
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2 | * Opencore OR1K CPU Dependent Source |
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3 | * |
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4 | * COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com> |
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5 | * COPYRIGHT (c) 1989-1999. |
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6 | * On-Line Applications Research Corporation (OAR). |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in the file LICENSE in this distribution or at |
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10 | * http://www.rtems.org/license/LICENSE. |
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11 | * |
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12 | */ |
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13 | |
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14 | #include <rtems/score/cpuimpl.h> |
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15 | #include <rtems/score/isr.h> |
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16 | |
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17 | /* bsp_start_vector_table_begin is the start address of the vector table |
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18 | * containing addresses to ISR Handlers. It's defined at the BSP linkcmds |
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19 | * and may differ from one BSP to another. |
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20 | */ |
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21 | extern char bsp_start_vector_table_begin[]; |
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22 | |
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23 | /** |
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24 | * @brief Performs processor dependent initialization. |
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25 | */ |
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26 | void _CPU_Initialize(void) |
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27 | { |
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28 | /* Do nothing */ |
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29 | } |
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30 | |
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31 | void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) |
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32 | { |
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33 | ISR_Level level; |
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34 | |
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35 | _CPU_ISR_Disable( level ); |
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36 | (void) level; |
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37 | |
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38 | _OR1KSIM_CPU_Halt(); |
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39 | |
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40 | while ( true ) { |
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41 | /* Do nothing */ |
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42 | } |
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43 | } |
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44 | |
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45 | /* end of Fatal Error manager macros */ |
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46 | |
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47 | /** |
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48 | * @brief Sets the hardware interrupt level by the level value. |
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49 | * |
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50 | * @param[in] level for or1k can only range over two values: |
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51 | * 0 (enable interrupts) and 1 (disable interrupts). In future |
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52 | * implementations if fast context switch is implemented, the level |
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53 | * can range from 0 to 15. @see OpenRISC architecture manual. |
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54 | * |
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55 | */ |
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56 | void _CPU_ISR_Set_level(uint32_t level) |
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57 | { |
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58 | uint32_t sr = 0; |
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59 | level = (level > 0)? 1 : 0; |
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60 | |
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61 | /* map level bit to or1k interrupt enable/disable bit in sr register */ |
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62 | level <<= CPU_OR1K_SPR_SR_SHAMT_IEE; |
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63 | |
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64 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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65 | |
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66 | if (level == 0){ /* Enable all interrupts */ |
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67 | sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE; |
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68 | |
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69 | } else{ |
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70 | sr &= ~CPU_OR1K_SPR_SR_IEE; |
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71 | } |
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72 | |
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73 | _OR1K_mtspr(CPU_OR1K_SPR_SR, sr); |
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74 | } |
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75 | |
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76 | uint32_t _CPU_ISR_Get_level( void ) |
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77 | { |
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78 | uint32_t sr = 0; |
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79 | |
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80 | sr = _OR1K_mfspr(CPU_OR1K_SPR_SR); |
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81 | |
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82 | return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1; |
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83 | } |
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84 | |
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85 | void _CPU_ISR_install_raw_handler( |
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86 | uint32_t vector, |
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87 | CPU_ISR_raw_handler new_handler, |
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88 | CPU_ISR_raw_handler *old_handler |
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89 | ) |
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90 | { |
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91 | CPU_ISR_raw_handler *table = |
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92 | (CPU_ISR_raw_handler *) bsp_start_vector_table_begin; |
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93 | CPU_ISR_raw_handler current_handler; |
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94 | |
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95 | ISR_Level level; |
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96 | |
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97 | _ISR_Local_disable( level ); |
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98 | |
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99 | current_handler = table [vector]; |
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100 | |
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101 | /* The current handler is now the old one */ |
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102 | if (old_handler != NULL) { |
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103 | *old_handler = current_handler; |
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104 | } |
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105 | |
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106 | /* Write only if necessary to avoid writes to a maybe read-only memory */ |
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107 | if (current_handler != new_handler) { |
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108 | table [vector] = new_handler; |
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109 | } |
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110 | |
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111 | _ISR_Local_enable( level ); |
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112 | } |
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113 | |
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114 | void *_CPU_Thread_Idle_body( uintptr_t ignored ) |
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115 | { |
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116 | do { |
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117 | _OR1K_CPU_Sleep(); |
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118 | } while (1); |
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119 | } |
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