source: rtems/cpukit/score/cpu/or1k/cpu.c @ 2a11a46f

4.11
Last change on this file since 2a11a46f was 2a11a46f, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 8, 2015 at 6:52:00 PM

or1k: Correct _CPU_Thread_Idle_body prototype

  • Property mode set to 100644
File size: 2.6 KB
Line 
1/*
2 *  Opencore OR1K CPU Dependent Source
3 *
4 *  COPYRIGHT (c) 2014-2015 Hesham ALMatary <heshamelmatary@gmail.com>
5 *  COPYRIGHT (c) 1989-1999.
6 *  On-Line Applications Research Corporation (OAR).
7 *
8 *  The license and distribution terms for this file may be
9 *  found in the file LICENSE in this distribution or at
10 *  http://www.rtems.com/license/LICENSE.
11 *
12 */
13
14#include <rtems/system.h>
15#include <rtems/score/isr.h>
16#include <rtems/score/wkspace.h>
17#include <rtems/score/cpu.h>
18
19/* bsp_start_vector_table_begin is the start address of the vector table
20 * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
21 * and may differ from one BSP to another.
22 */
23extern char bsp_start_vector_table_begin[];
24
25/**
26 * @brief Performs processor dependent initialization.
27 */
28void _CPU_Initialize(void)
29{
30  /* Do nothing */
31}
32
33/**
34 * @brief Sets the hardware interrupt level by the level value.
35 *
36 * @param[in] level for or1k can only range over two values:
37 * 0 (enable interrupts) and 1 (disable interrupts). In future
38 * implementations if fast context switch is implemented, the level
39 * can range from 0 to 15. @see OpenRISC architecture manual.
40 *
41 */
42void _CPU_ISR_Set_level(uint32_t level)
43{
44  uint32_t sr = 0;
45  level = (level > 0)? 1 : 0;
46
47  /* map level bit to or1k interrupt enable/disable bit in sr register */
48  level <<= CPU_OR1K_SPR_SR_SHAMT_IEE;
49
50  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
51
52  if (level == 0){ /* Enable all interrupts */
53    sr |= CPU_OR1K_SPR_SR_IEE | CPU_OR1K_SPR_SR_TEE;
54
55  } else{
56    sr &= ~CPU_OR1K_SPR_SR_IEE;
57  }
58
59  _OR1K_mtspr(CPU_OR1K_SPR_SR, sr);
60 }
61
62uint32_t  _CPU_ISR_Get_level( void )
63{
64  uint32_t sr = 0;
65
66  sr = _OR1K_mfspr(CPU_OR1K_SPR_SR);
67
68  return (sr & CPU_OR1K_SPR_SR_IEE)? 0 : 1;
69}
70
71void _CPU_ISR_install_raw_handler(
72  uint32_t   vector,
73  proc_ptr    new_handler,
74  proc_ptr   *old_handler
75)
76{
77}
78
79void _CPU_ISR_install_vector(
80  uint32_t    vector,
81  proc_ptr    new_handler,
82  proc_ptr   *old_handler
83)
84{
85   proc_ptr *table =
86     (proc_ptr *) bsp_start_vector_table_begin;
87   proc_ptr current_handler;
88
89   ISR_Level level;
90
91  _ISR_Disable( level );
92
93  current_handler = table [vector];
94
95  /* The current handler is now the old one */
96  if (old_handler != NULL) {
97    *old_handler = (proc_ptr) current_handler;
98  }
99
100  /* Write only if necessary to avoid writes to a maybe read-only memory */
101  if (current_handler != new_handler) {
102    table [vector] = new_handler;
103  }
104
105   _ISR_Enable( level );
106}
107
108void _CPU_Install_interrupt_stack( void )
109{
110}
111
112void *_CPU_Thread_Idle_body( uintptr_t ignored )
113{
114  do {
115     _OR1K_CPU_Sleep();
116  } while (1);
117}
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