source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ f8a39cdc

4.11
Last change on this file since f8a39cdc was f8a39cdc, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 14, 2013 at 11:27:13 PM

no_cpu/.../cpu.h: Comment improvement

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1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief NO_CPU Department Source
5 *
6 * This include file contains information pertaining to the NO_CPU
7 * processor.
8 */
9
10/*
11 *  This include file contains information pertaining to the XXX
12 *  processor.
13 *
14 *  @note This file is part of a porting template that is intended
15 *  to be used as the starting point when porting RTEMS to a new
16 *  CPU family.  The following needs to be done when using this as
17 *  the starting point for a new port:
18 *
19 *  + Anywhere there is an XXX, it should be replaced
20 *    with information about the CPU family being ported to.
21 *
22 *  + At the end of each comment section, there is a heading which
23 *    says "Port Specific Information:".  When porting to RTEMS,
24 *    add CPU family specific information in this section
25 */
26
27/*
28 *  COPYRIGHT (c) 1989-2008.
29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.com/license/LICENSE.
34 */
35
36#ifndef _RTEMS_SCORE_CPU_H
37#define _RTEMS_SCORE_CPU_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/types.h>
44#include <rtems/score/no_cpu.h>
45
46/* conditional compilation parameters */
47
48/**
49 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
50 *
51 * If TRUE, then they are inlined.
52 * If FALSE, then a subroutine call is made.
53 *
54 * This conditional is an example of the classic trade-off of size
55 * versus speed.  Inlining the call (TRUE) typically increases the
56 * size of RTEMS while speeding up the enabling of dispatching.
57 *
58 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
59 * only be 0 or 1 unless you are in an interrupt handler and that
60 * interrupt handler invokes the executive.]  When not inlined
61 * something calls @ref _Thread_Enable_dispatch which in turns calls
62 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
63 * one subroutine call is avoided entirely.
64 *
65 * Port Specific Information:
66 *
67 * XXX document implementation including references if appropriate
68 */
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/**
72 * Should the body of the search loops in _Thread_queue_Enqueue_priority
73 * be unrolled one time?  In unrolled each iteration of the loop examines
74 * two "nodes" on the chain being searched.  Otherwise, only one node
75 * is examined per iteration.
76 *
77 * If TRUE, then the loops are unrolled.
78 * If FALSE, then the loops are not unrolled.
79 *
80 * The primary factor in making this decision is the cost of disabling
81 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 * body of the loop.  On some CPUs, the flash is more expensive than
83 * one iteration of the loop body.  In this case, it might be desirable
84 * to unroll the loop.  It is important to note that on some CPUs, this
85 * code is the longest interrupt disable period in RTEMS.  So it is
86 * necessary to strike a balance when setting this parameter.
87 *
88 * Port Specific Information:
89 *
90 * XXX document implementation including references if appropriate
91 */
92#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
93
94/**
95 * Does RTEMS manage a dedicated interrupt stack in software?
96 *
97 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
98 * If FALSE, nothing is done.
99 *
100 * If the CPU supports a dedicated interrupt stack in hardware,
101 * then it is generally the responsibility of the BSP to allocate it
102 * and set it up.
103 *
104 * If the CPU does not support a dedicated interrupt stack, then
105 * the porter has two options: (1) execute interrupts on the
106 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
107 * interrupt stack.
108 *
109 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
110 *
111 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
112 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
113 * possible that both are FALSE for a particular CPU.  Although it
114 * is unclear what that would imply about the interrupt processing
115 * procedure on that CPU.
116 *
117 * Port Specific Information:
118 *
119 * XXX document implementation including references if appropriate
120 */
121#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
122
123/**
124 * Does the CPU follow the simple vectored interrupt model?
125 *
126 * If TRUE, then RTEMS allocates the vector table it internally manages.
127 * If FALSE, then the BSP is assumed to allocate and manage the vector
128 * table
129 *
130 * Port Specific Information:
131 *
132 * XXX document implementation including references if appropriate
133 */
134#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
135
136/**
137 * Does this CPU have hardware support for a dedicated interrupt stack?
138 *
139 * If TRUE, then it must be installed during initialization.
140 * If FALSE, then no installation is performed.
141 *
142 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
143 *
144 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
145 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
146 * possible that both are FALSE for a particular CPU.  Although it
147 * is unclear what that would imply about the interrupt processing
148 * procedure on that CPU.
149 *
150 * Port Specific Information:
151 *
152 * XXX document implementation including references if appropriate
153 */
154#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
155
156/**
157 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
158 *
159 * If TRUE, then the memory is allocated during initialization.
160 * If FALSE, then the memory is allocated during initialization.
161 *
162 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
163 *
164 * Port Specific Information:
165 *
166 * XXX document implementation including references if appropriate
167 */
168#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
169
170/**
171 * Does the RTEMS invoke the user's ISR with the vector number and
172 * a pointer to the saved interrupt frame (1) or just the vector
173 * number (0)?
174 *
175 * Port Specific Information:
176 *
177 * XXX document implementation including references if appropriate
178 */
179#define CPU_ISR_PASSES_FRAME_POINTER 0
180
181/**
182 * @def CPU_HARDWARE_FP
183 *
184 * Does the CPU have hardware floating point?
185 *
186 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
187 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
188 *
189 * If there is a FP coprocessor such as the i387 or mc68881, then
190 * the answer is TRUE.
191 *
192 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
193 * It indicates whether or not this CPU model has FP support.  For
194 * example, it would be possible to have an i386_nofp CPU model
195 * which set this to false to indicate that you have an i386 without
196 * an i387 and wish to leave floating point support out of RTEMS.
197 */
198
199/**
200 * @def CPU_SOFTWARE_FP
201 *
202 * Does the CPU have no hardware floating point and GCC provides a
203 * software floating point implementation which must be context
204 * switched?
205 *
206 * This feature conditional is used to indicate whether or not there
207 * is software implemented floating point that must be context
208 * switched.  The determination of whether or not this applies
209 * is very tool specific and the state saved/restored is also
210 * compiler specific.
211 *
212 * Port Specific Information:
213 *
214 * XXX document implementation including references if appropriate
215 */
216#if ( NO_CPU_HAS_FPU == 1 )
217#define CPU_HARDWARE_FP     TRUE
218#else
219#define CPU_HARDWARE_FP     FALSE
220#endif
221#define CPU_SOFTWARE_FP     FALSE
222
223/**
224 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
225 *
226 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
227 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
228 *
229 * So far, the only CPUs in which this option has been used are the
230 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
231 * gcc both implicitly used the floating point registers to perform
232 * integer multiplies.  Similarly, the PowerPC port of gcc has been
233 * seen to allocate floating point local variables and touch the FPU
234 * even when the flow through a subroutine (like vfprintf()) might
235 * not use floating point formats.
236 *
237 * If a function which you would not think utilize the FP unit DOES,
238 * then one can not easily predict which tasks will use the FP hardware.
239 * In this case, this option should be TRUE.
240 *
241 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
242 *
243 * Port Specific Information:
244 *
245 * XXX document implementation including references if appropriate
246 */
247#define CPU_ALL_TASKS_ARE_FP     TRUE
248
249/**
250 * Should the IDLE task have a floating point context?
251 *
252 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
253 * and it has a floating point context which is switched in and out.
254 * If FALSE, then the IDLE task does not have a floating point context.
255 *
256 * Setting this to TRUE negatively impacts the time required to preempt
257 * the IDLE task from an interrupt because the floating point context
258 * must be saved as part of the preemption.
259 *
260 * Port Specific Information:
261 *
262 * XXX document implementation including references if appropriate
263 */
264#define CPU_IDLE_TASK_IS_FP      FALSE
265
266/**
267 * Should the saving of the floating point registers be deferred
268 * until a context switch is made to another different floating point
269 * task?
270 *
271 * If TRUE, then the floating point context will not be stored until
272 * necessary.  It will remain in the floating point registers and not
273 * disturned until another floating point task is switched to.
274 *
275 * If FALSE, then the floating point context is saved when a floating
276 * point task is switched out and restored when the next floating point
277 * task is restored.  The state of the floating point registers between
278 * those two operations is not specified.
279 *
280 * If the floating point context does NOT have to be saved as part of
281 * interrupt dispatching, then it should be safe to set this to TRUE.
282 *
283 * Setting this flag to TRUE results in using a different algorithm
284 * for deciding when to save and restore the floating point context.
285 * The deferred FP switch algorithm minimizes the number of times
286 * the FP context is saved and restored.  The FP context is not saved
287 * until a context switch is made to another, different FP task.
288 * Thus in a system with only one FP task, the FP context will never
289 * be saved or restored.
290 *
291 * Port Specific Information:
292 *
293 * XXX document implementation including references if appropriate
294 */
295#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
296
297/**
298 * Does this port provide a CPU dependent IDLE task implementation?
299 *
300 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
301 * must be provided and is the default IDLE thread body instead of
302 * @ref _CPU_Thread_Idle_body.
303 *
304 * If FALSE, then use the generic IDLE thread body if the BSP does
305 * not provide one.
306 *
307 * This is intended to allow for supporting processors which have
308 * a low power or idle mode.  When the IDLE thread is executed, then
309 * the CPU can be powered down.
310 *
311 * The order of precedence for selecting the IDLE thread body is:
312 *
313 *   -#  BSP provided
314 *   -#  CPU dependent (if provided)
315 *   -#  generic (if no BSP and no CPU dependent)
316 *
317 * Port Specific Information:
318 *
319 * XXX document implementation including references if appropriate
320 */
321#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
322
323/**
324 * Does the stack grow up (toward higher addresses) or down
325 * (toward lower addresses)?
326 *
327 * If TRUE, then the grows upward.
328 * If FALSE, then the grows toward smaller addresses.
329 *
330 * Port Specific Information:
331 *
332 * XXX document implementation including references if appropriate
333 */
334#define CPU_STACK_GROWS_UP               TRUE
335
336/**
337 * The following is the variable attribute used to force alignment
338 * of critical RTEMS structures.  On some processors it may make
339 * sense to have these aligned on tighter boundaries than
340 * the minimum requirements of the compiler in order to have as
341 * much of the critical data area as possible in a cache line.
342 *
343 * The placement of this macro in the declaration of the variables
344 * is based on the syntactically requirements of the GNU C
345 * "__attribute__" extension.  For example with GNU C, use
346 * the following to force a structures to a 32 byte boundary.
347 *
348 *     __attribute__ ((aligned (32)))
349 *
350 * NOTE: Currently only the Priority Bit Map table uses this feature.
351 *       To benefit from using this, the data must be heavily
352 *       used so it will stay in the cache and used frequently enough
353 *       in the executive to justify turning this on.
354 *
355 * Port Specific Information:
356 *
357 * XXX document implementation including references if appropriate
358 */
359#define CPU_STRUCTURE_ALIGNMENT
360
361/**
362 * @defgroup CPUTimestamp Processor Dependent Timestamp Support
363 *
364 * This group assists in issues related to timestamp implementation.
365 *
366 * The port must choose exactly one of the following defines:
367 * - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
368 * - #define CPU_TIMESTAMP_USE_INT64 TRUE
369 * - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
370 *
371 * Performance of int64_t versus struct timespec
372 * =============================================
373 *
374 * On PowerPC/psim, inlined int64_t saves ~50 instructions on each
375 *   _Thread_Dispatch operation which results in a context switch.
376 *   This works out to be about 10% faster dispatches and 7.5% faster
377 *   blocking semaphore obtains.  The following numbers are in instructions
378 *   and from tm02 and tm26.
379 *
380 *                        timespec  int64  inlined int64
381 *   dispatch:              446      446      400
382 *   blocking sem obtain:   627      626      581
383 *
384 * On SPARC/sis, inlined int64_t shows the same percentage gains.
385 *   The following numbers are in microseconds and from tm02 and tm26.
386 *
387 *                        timespec  int64  inlined int64
388 *   dispatch:               59       61       53
389 *   blocking sem obtain:    98      100       92
390 *
391 * Inlining appears to have a tendency to increase the size of
392 *   some executables.
393 * Not inlining reduces the execution improvement but does not seem to
394 *   be an improvement on the PowerPC and SPARC. The struct timespec
395 *   and the executables with int64 not inlined are about the same size.
396 *
397 */
398/**@{**/
399
400/**
401 * Selects the timestamp implementation using struct timespec.
402 *
403 * Port Specific Information:
404 *
405 * XXX document implementation including references if appropriate
406 */
407#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
408
409/**
410 * Selects the timestamp implementation using int64_t and no inlined methods.
411 *
412 * Port Specific Information:
413 *
414 * XXX document implementation including references if appropriate
415 */
416#define CPU_TIMESTAMP_USE_INT64 TRUE
417
418/**
419 * Selects the timestamp implementation using int64_t and inlined methods.
420 *
421 * Port Specific Information:
422 *
423 * XXX document implementation including references if appropriate
424 */
425#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
426
427/** @} */
428
429/**
430 * @defgroup CPUEndian Processor Dependent Endianness Support
431 *
432 * This group assists in issues related to processor endianness.
433 *
434 */
435/**@{**/
436
437/**
438 * Define what is required to specify how the network to host conversion
439 * routines are handled.
440 *
441 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
442 * same values.
443 *
444 * @see CPU_LITTLE_ENDIAN
445 *
446 * Port Specific Information:
447 *
448 * XXX document implementation including references if appropriate
449 */
450#define CPU_BIG_ENDIAN                           TRUE
451
452/**
453 * Define what is required to specify how the network to host conversion
454 * routines are handled.
455 *
456 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
457 * same values.
458 *
459 * @see CPU_BIG_ENDIAN
460 *
461 * Port Specific Information:
462 *
463 * XXX document implementation including references if appropriate
464 */
465#define CPU_LITTLE_ENDIAN                        FALSE
466
467/** @} */
468
469/**
470 * @ingroup CPUInterrupt
471 *
472 * The following defines the number of bits actually used in the
473 * interrupt field of the task mode.  How those bits map to the
474 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
475 *
476 * Port Specific Information:
477 *
478 * XXX document implementation including references if appropriate
479 */
480#define CPU_MODES_INTERRUPT_MASK   0x00000001
481
482/**
483 * @brief The size of the CPU specific per-CPU control.
484 *
485 * This define must be visible to assember files since it is used to derive
486 * structure offsets.
487 */
488#define CPU_PER_CPU_CONTROL_SIZE 0
489
490/*
491 *  Processor defined structures required for cpukit/score.
492 *
493 *  Port Specific Information:
494 *
495 *  XXX document implementation including references if appropriate
496 */
497
498/* may need to put some structures here.  */
499
500/**
501 * @brief The CPU specific per-CPU control.
502 *
503 * The CPU port can place here all state information that must be available and
504 * maintained for each CPU in the system.
505 */
506typedef struct {
507  /* CPU specific per-CPU state */
508} CPU_Per_CPU_control;
509
510/**
511 * @defgroup CPUContext Processor Dependent Context Management
512 *
513 * From the highest level viewpoint, there are 2 types of context to save.
514 *
515 *    -# Interrupt registers to save
516 *    -# Task level registers to save
517 *
518 * Since RTEMS handles integer and floating point contexts separately, this
519 * means we have the following 3 context items:
520 *
521 *    -# task level context stuff::  Context_Control
522 *    -# floating point task stuff:: Context_Control_fp
523 *    -# special interrupt level context :: CPU_Interrupt_frame
524 *
525 * On some processors, it is cost-effective to save only the callee
526 * preserved registers during a task context switch.  This means
527 * that the ISR code needs to save those registers which do not
528 * persist across function calls.  It is not mandatory to make this
529 * distinctions between the caller/callee saves registers for the
530 * purpose of minimizing context saved during task switch and on interrupts.
531 * If the cost of saving extra registers is minimal, simplicity is the
532 * choice.  Save the same context on interrupt entry as for tasks in
533 * this case.
534 *
535 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
536 * care should be used in designing the context area.
537 *
538 * On some CPUs with hardware floating point support, the Context_Control_fp
539 * structure will not be used or it simply consist of an array of a
540 * fixed number of bytes.   This is done when the floating point context
541 * is dumped by a "FP save context" type instruction and the format
542 * is not really defined by the CPU.  In this case, there is no need
543 * to figure out the exact format -- only the size.  Of course, although
544 * this is enough information for RTEMS, it is probably not enough for
545 * a debugger such as gdb.  But that is another problem.
546 *
547 * Port Specific Information:
548 *
549 * XXX document implementation including references if appropriate
550 *
551 */
552/**@{**/
553
554/**
555 * @ingroup Management
556 * This defines the minimal set of integer and processor state registers
557 * that must be saved during a voluntary context switch from one thread
558 * to another.
559 */
560typedef struct {
561    /**
562     * This field is a hint that a port will have a number of integer
563     * registers that need to be saved at a context switch.
564     */
565    uint32_t   some_integer_register;
566    /**
567     * This field is a hint that a port will have a number of system
568     * registers that need to be saved at a context switch.
569     */
570    uint32_t   some_system_register;
571
572    /**
573     * This field is a hint that a port will have a register that
574     * is the stack pointer.
575     */
576    uint32_t   stack_pointer;
577} Context_Control;
578
579/**
580 * @ingroup Management
581 *
582 * This macro returns the stack pointer associated with @a _context.
583 *
584 * @param[in] _context is the thread context area to access
585 *
586 * @return This method returns the stack pointer.
587 */
588#define _CPU_Context_Get_SP( _context ) \
589  (_context)->stack_pointer
590
591/**
592 * @ingroup Management
593 *
594 * This defines the complete set of floating point registers that must
595 * be saved during any context switch from one thread to another.
596 */
597typedef struct {
598    /** FPU registers are listed here */
599    double      some_float_register;
600} Context_Control_fp;
601
602/**
603 * @ingroup Management
604 *
605 * This defines the set of integer and processor state registers that must
606 * be saved during an interrupt.  This set does not include any which are
607 * in @ref Context_Control.
608 */
609typedef struct {
610    /**
611     * This field is a hint that a port will have a number of integer
612     * registers that need to be saved when an interrupt occurs or
613     * when a context switch occurs at the end of an ISR.
614     */
615    uint32_t   special_interrupt_register;
616} CPU_Interrupt_frame;
617
618/**
619 * This variable is optional.  It is used on CPUs on which it is difficult
620 * to generate an "uninitialized" FP context.  It is filled in by
621 * @ref _CPU_Initialize and copied into the task's FP context area during
622 * @ref _CPU_Context_Initialize.
623 *
624 * Port Specific Information:
625 *
626 * XXX document implementation including references if appropriate
627 */
628SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
629
630/** @} */
631
632/**
633 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
634 *
635 * On some CPUs, RTEMS supports a software managed interrupt stack.
636 * This stack is allocated by the Interrupt Manager and the switch
637 * is performed in @ref _ISR_Handler.  These variables contain pointers
638 * to the lowest and highest addresses in the chunk of memory allocated
639 * for the interrupt stack.  Since it is unknown whether the stack
640 * grows up or down (in general), this give the CPU dependent
641 * code the option of picking the version it wants to use.
642 *
643 * NOTE: These two variables are required if the macro
644 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
645 *
646 * Port Specific Information:
647 *
648 * XXX document implementation including references if appropriate
649 */
650
651/*
652 *  Nothing prevents the porter from declaring more CPU specific variables.
653 *
654 *  Port Specific Information:
655 *
656 *  XXX document implementation including references if appropriate
657 */
658
659/* XXX: if needed, put more variables here */
660
661/**
662 * @ingroup CPUContext
663 *
664 * The size of the floating point context area.  On some CPUs this
665 * will not be a "sizeof" because the format of the floating point
666 * area is not defined -- only the size is.  This is usually on
667 * CPUs with a "floating point save context" instruction.
668 *
669 * Port Specific Information:
670 *
671 * XXX document implementation including references if appropriate
672 */
673#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
674
675/**
676 * Amount of extra stack (above minimum stack size) required by
677 * MPCI receive server thread.  Remember that in a multiprocessor
678 * system this thread must exist and be able to process all directives.
679 *
680 * Port Specific Information:
681 *
682 * XXX document implementation including references if appropriate
683 */
684#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
685
686/**
687 * @ingroup CPUInterrupt
688 *
689 * This defines the number of entries in the @ref _ISR_Vector_table managed
690 * by RTEMS.
691 *
692 * Port Specific Information:
693 *
694 * XXX document implementation including references if appropriate
695 */
696#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
697
698/**
699 * @ingroup CPUInterrupt
700 *
701 * This defines the highest interrupt vector number for this port.
702 */
703#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
704
705/**
706 * @ingroup CPUInterrupt
707 *
708 * This is defined if the port has a special way to report the ISR nesting
709 * level.  Most ports maintain the variable @a _ISR_Nest_level.
710 */
711#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
712
713/**
714 * @ingroup CPUContext
715 *
716 * Should be large enough to run all RTEMS tests.  This ensures
717 * that a "reasonable" small application should not have any problems.
718 *
719 * Port Specific Information:
720 *
721 * XXX document implementation including references if appropriate
722 */
723#define CPU_STACK_MINIMUM_SIZE          (1024*4)
724
725/**
726 * Size of a pointer.
727 *
728 * This must be an integer literal that can be used by the assembler.  This
729 * value will be used to calculate offsets of structure members.  These
730 * offsets will be used in assembler code.
731 */
732#define CPU_SIZEOF_POINTER         4
733
734/**
735 * CPU's worst alignment requirement for data types on a byte boundary.  This
736 * alignment does not take into account the requirements for the stack.
737 *
738 * Port Specific Information:
739 *
740 * XXX document implementation including references if appropriate
741 */
742#define CPU_ALIGNMENT              8
743
744/**
745 * This number corresponds to the byte alignment requirement for the
746 * heap handler.  This alignment requirement may be stricter than that
747 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
748 * common for the heap to follow the same alignment requirement as
749 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
750 * the heap, then this should be set to @ref CPU_ALIGNMENT.
751 *
752 * NOTE:  This does not have to be a power of 2 although it should be
753 *        a multiple of 2 greater than or equal to 2.  The requirement
754 *        to be a multiple of 2 is because the heap uses the least
755 *        significant field of the front and back flags to indicate
756 *        that a block is in use or free.  So you do not want any odd
757 *        length blocks really putting length data in that bit.
758 *
759 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
760 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
761 *        elements allocated from the heap meet all restrictions.
762 *
763 * Port Specific Information:
764 *
765 * XXX document implementation including references if appropriate
766 */
767#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
768
769/**
770 * This number corresponds to the byte alignment requirement for memory
771 * buffers allocated by the partition manager.  This alignment requirement
772 * may be stricter than that for the data types alignment specified by
773 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
774 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
775 * strict enough for the partition, then this should be set to
776 * @ref CPU_ALIGNMENT.
777 *
778 * NOTE:  This does not have to be a power of 2.  It does have to
779 *        be greater or equal to than @ref CPU_ALIGNMENT.
780 *
781 * Port Specific Information:
782 *
783 * XXX document implementation including references if appropriate
784 */
785#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
786
787/**
788 * This number corresponds to the byte alignment requirement for the
789 * stack.  This alignment requirement may be stricter than that for the
790 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
791 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
792 * set to 0.
793 *
794 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
795 *
796 * Port Specific Information:
797 *
798 * XXX document implementation including references if appropriate
799 */
800#define CPU_STACK_ALIGNMENT        0
801
802/*
803 *  ISR handler macros
804 */
805
806/**
807 * @ingroup CPUInterrupt
808 *
809 * Support routine to initialize the RTEMS vector table after it is allocated.
810 *
811 * Port Specific Information:
812 *
813 * XXX document implementation including references if appropriate
814 */
815#define _CPU_Initialize_vectors()
816
817/**
818 * @ingroup CPUInterrupt
819 *
820 * Disable all interrupts for an RTEMS critical section.  The previous
821 * level is returned in @a _isr_cookie.
822 *
823 * @param[out] _isr_cookie will contain the previous level cookie
824 *
825 * Port Specific Information:
826 *
827 * XXX document implementation including references if appropriate
828 */
829#define _CPU_ISR_Disable( _isr_cookie ) \
830  { \
831    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
832  }
833
834/**
835 * @ingroup CPUInterrupt
836 *
837 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
838 * This indicates the end of an RTEMS critical section.  The parameter
839 * @a _isr_cookie is not modified.
840 *
841 * @param[in] _isr_cookie contain the previous level cookie
842 *
843 * Port Specific Information:
844 *
845 * XXX document implementation including references if appropriate
846 */
847#define _CPU_ISR_Enable( _isr_cookie )  \
848  { \
849  }
850
851/**
852 * @ingroup CPUInterrupt
853 *
854 * This temporarily restores the interrupt to @a _isr_cookie before immediately
855 * disabling them again.  This is used to divide long RTEMS critical
856 * sections into two or more parts.  The parameter @a _isr_cookie is not
857 * modified.
858 *
859 * @param[in] _isr_cookie contain the previous level cookie
860 *
861 * Port Specific Information:
862 *
863 * XXX document implementation including references if appropriate
864 */
865#define _CPU_ISR_Flash( _isr_cookie ) \
866  { \
867  }
868
869/**
870 * @ingroup CPUInterrupt
871 *
872 * This routine and @ref _CPU_ISR_Get_level
873 * Map the interrupt level in task mode onto the hardware that the CPU
874 * actually provides.  Currently, interrupt levels which do not
875 * map onto the CPU in a generic fashion are undefined.  Someday,
876 * it would be nice if these were "mapped" by the application
877 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
878 * 8 - 255 would be available for bsp/application specific meaning.
879 * This could be used to manage a programmable interrupt controller
880 * via the rtems_task_mode directive.
881 *
882 * Port Specific Information:
883 *
884 * XXX document implementation including references if appropriate
885 */
886#define _CPU_ISR_Set_level( new_level ) \
887  { \
888  }
889
890/**
891 * @ingroup CPUInterrupt
892 *
893 * Return the current interrupt disable level for this task in
894 * the format used by the interrupt level portion of the task mode.
895 *
896 * NOTE: This routine usually must be implemented as a subroutine.
897 *
898 * Port Specific Information:
899 *
900 * XXX document implementation including references if appropriate
901 */
902uint32_t   _CPU_ISR_Get_level( void );
903
904/* end of ISR handler macros */
905
906/* Context handler macros */
907
908/**
909 *  @ingroup CPUContext
910 *
911 * Initialize the context to a state suitable for starting a
912 * task after a context restore operation.  Generally, this
913 * involves:
914 *
915 *    - setting a starting address
916 *    - preparing the stack
917 *    - preparing the stack and frame pointers
918 *    - setting the proper interrupt level in the context
919 *    - initializing the floating point context
920 *
921 * This routine generally does not set any unnecessary register
922 * in the context.  The state of the "general data" registers is
923 * undefined at task start time.
924 *
925 * @param[in] _the_context is the context structure to be initialized
926 * @param[in] _stack_base is the lowest physical address of this task's stack
927 * @param[in] _size is the size of this task's stack
928 * @param[in] _isr is the interrupt disable level
929 * @param[in] _entry_point is the thread's entry point.  This is
930 *        always @a _Thread_Handler
931 * @param[in] _is_fp is TRUE if the thread is to be a floating
932 *       point thread.  This is typically only used on CPUs where the
933 *       FPU may be easily disabled by software such as on the SPARC
934 *       where the PSR contains an enable FPU bit.
935 *
936 * Port Specific Information:
937 *
938 * XXX document implementation including references if appropriate
939 */
940#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
941                                 _isr, _entry_point, _is_fp ) \
942  { \
943  }
944
945/**
946 * This routine is responsible for somehow restarting the currently
947 * executing task.  If you are lucky, then all that is necessary
948 * is restoring the context.  Otherwise, there will need to be
949 * a special assembly routine which does something special in this
950 * case.  For many ports, simply adding a label to the restore path
951 * of @ref _CPU_Context_switch will work.  On other ports, it may be
952 * possibly to load a few arguments and jump to the restore path. It will
953 * not work if restarting self conflicts with the stack frame
954 * assumptions of restoring a context.
955 *
956 * Port Specific Information:
957 *
958 * XXX document implementation including references if appropriate
959 */
960#define _CPU_Context_Restart_self( _the_context ) \
961   _CPU_Context_restore( (_the_context) );
962
963/**
964 * @ingroup CPUContext
965 *
966 * The purpose of this macro is to allow the initial pointer into
967 * a floating point context area (used to save the floating point
968 * context) to be at an arbitrary place in the floating point
969 *context area.
970 *
971 * This is necessary because some FP units are designed to have
972 * their context saved as a stack which grows into lower addresses.
973 * Other FP units can be saved by simply moving registers into offsets
974 * from the base of the context area.  Finally some FP units provide
975 * a "dump context" instruction which could fill in from high to low
976 * or low to high based on the whim of the CPU designers.
977 *
978 * @param[in] _base is the lowest physical address of the floating point
979 *        context area
980 * @param[in] _offset is the offset into the floating point area
981 *
982 * Port Specific Information:
983 *
984 * XXX document implementation including references if appropriate
985 */
986#define _CPU_Context_Fp_start( _base, _offset ) \
987   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
988
989/**
990 * This routine initializes the FP context area passed to it to.
991 * There are a few standard ways in which to initialize the
992 * floating point context.  The code included for this macro assumes
993 * that this is a CPU in which a "initial" FP context was saved into
994 * @a _CPU_Null_fp_context and it simply copies it to the destination
995 * context passed to it.
996 *
997 * Other floating point context save/restore models include:
998 *   -# not doing anything, and
999 *   -# putting a "null FP status word" in the correct place in the FP context.
1000 *
1001 * @param[in] _destination is the floating point context area
1002 *
1003 * Port Specific Information:
1004 *
1005 * XXX document implementation including references if appropriate
1006 */
1007#define _CPU_Context_Initialize_fp( _destination ) \
1008  { \
1009   *(*(_destination)) = _CPU_Null_fp_context; \
1010  }
1011
1012/* end of Context handler macros */
1013
1014/* Fatal Error manager macros */
1015
1016/**
1017 * This routine copies _error into a known place -- typically a stack
1018 * location or a register, optionally disables interrupts, and
1019 * halts/stops the CPU.
1020 *
1021 * Port Specific Information:
1022 *
1023 * XXX document implementation including references if appropriate
1024 */
1025#define _CPU_Fatal_halt( _error ) \
1026  { \
1027  }
1028
1029/* end of Fatal Error manager macros */
1030
1031/* Bitfield handler macros */
1032
1033/**
1034 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1035 *
1036 * This set of routines are used to implement fast searches for
1037 * the most important ready task.
1038 *
1039 */
1040/**@{**/
1041
1042/**
1043 * This definition is set to TRUE if the port uses the generic bitfield
1044 * manipulation implementation.
1045 */
1046#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1047
1048/**
1049 * This definition is set to TRUE if the port uses the data tables provided
1050 * by the generic bitfield manipulation implementation.
1051 * This can occur when actually using the generic bitfield manipulation
1052 * implementation or when implementing the same algorithm in assembly
1053 * language for improved performance.  It is unlikely that a port will use
1054 * the data if it has a bitfield scan instruction.
1055 */
1056#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1057
1058/**
1059 * This routine sets @a _output to the bit number of the first bit
1060 * set in @a _value.  @a _value is of CPU dependent type
1061 * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
1062 * wide although only the 16 least significant bits will be used.
1063 *
1064 * There are a number of variables in using a "find first bit" type
1065 * instruction.
1066 *
1067 *   -# What happens when run on a value of zero?
1068 *   -# Bits may be numbered from MSB to LSB or vice-versa.
1069 *   -# The numbering may be zero or one based.
1070 *   -# The "find first bit" instruction may search from MSB or LSB.
1071 *
1072 * RTEMS guarantees that (1) will never happen so it is not a concern.
1073 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1074 * @ref _CPU_Priority_bits_index.  These three form a set of routines
1075 * which must logically operate together.  Bits in the _value are
1076 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
1077 * The basic major and minor values calculated by @ref _Priority_Major
1078 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1079 * to properly range between the values returned by the "find first bit"
1080 * instruction.  This makes it possible for @ref _Priority_Get_highest to
1081 * calculate the major and directly index into the minor table.
1082 * This mapping is necessary to ensure that 0 (a high priority major/minor)
1083 * is the first bit found.
1084 *
1085 * This entire "find first bit" and mapping process depends heavily
1086 * on the manner in which a priority is broken into a major and minor
1087 * components with the major being the 4 MSB of a priority and minor
1088 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1089 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1090 * to the lowest priority.
1091 *
1092 * If your CPU does not have a "find first bit" instruction, then
1093 * there are ways to make do without it.  Here are a handful of ways
1094 * to implement this in software:
1095 *
1096@verbatim
1097      - a series of 16 bit test instructions
1098      - a "binary search using if's"
1099      - _number = 0
1100        if _value > 0x00ff
1101          _value >>=8
1102          _number = 8;
1103
1104        if _value > 0x0000f
1105          _value >=8
1106          _number += 4
1107
1108        _number += bit_set_table[ _value ]
1109@endverbatim
1110
1111 *   where bit_set_table[ 16 ] has values which indicate the first
1112 *     bit set
1113 *
1114 * @param[in] _value is the value to be scanned
1115 * @param[in] _output is the first bit set
1116 *
1117 * Port Specific Information:
1118 *
1119 * XXX document implementation including references if appropriate
1120 */
1121
1122#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1123#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1124  { \
1125    (_output) = 0;   /* do something to prevent warnings */ \
1126  }
1127#endif
1128
1129/** @} */
1130
1131/* end of Bitfield handler macros */
1132
1133/**
1134 * This routine builds the mask which corresponds to the bit fields
1135 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1136 * for that routine.
1137 *
1138 * Port Specific Information:
1139 *
1140 * XXX document implementation including references if appropriate
1141 */
1142#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1143
1144#define _CPU_Priority_Mask( _bit_number ) \
1145  ( 1 << (_bit_number) )
1146
1147#endif
1148
1149/**
1150 * @ingroup CPUBitfield
1151 *
1152 * This routine translates the bit numbers returned by
1153 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1154 * a major or minor component of a priority.  See the discussion
1155 * for that routine.
1156 *
1157 * @param[in] _priority is the major or minor number to translate
1158 *
1159 * Port Specific Information:
1160 *
1161 * XXX document implementation including references if appropriate
1162 */
1163#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1164
1165#define _CPU_Priority_bits_index( _priority ) \
1166  (_priority)
1167
1168#endif
1169
1170/* end of Priority handler macros */
1171
1172/* functions */
1173
1174/**
1175 * This routine performs CPU dependent initialization.
1176 *
1177 * Port Specific Information:
1178 *
1179 * XXX document implementation including references if appropriate
1180 */
1181void _CPU_Initialize(void);
1182
1183/**
1184 * @ingroup CPUInterrupt
1185 *
1186 * This routine installs a "raw" interrupt handler directly into the
1187 * processor's vector table.
1188 *
1189 * @param[in] vector is the vector number
1190 * @param[in] new_handler is the raw ISR handler to install
1191 * @param[in] old_handler is the previously installed ISR Handler
1192 *
1193 * Port Specific Information:
1194 *
1195 * XXX document implementation including references if appropriate
1196 */
1197void _CPU_ISR_install_raw_handler(
1198  uint32_t    vector,
1199  proc_ptr    new_handler,
1200  proc_ptr   *old_handler
1201);
1202
1203/**
1204 * @ingroup CPUInterrupt
1205 *
1206 * This routine installs an interrupt vector.
1207 *
1208 * @param[in] vector is the vector number
1209 * @param[in] new_handler is the RTEMS ISR handler to install
1210 * @param[in] old_handler is the previously installed ISR Handler
1211 *
1212 * Port Specific Information:
1213 *
1214 * XXX document implementation including references if appropriate
1215 */
1216void _CPU_ISR_install_vector(
1217  uint32_t    vector,
1218  proc_ptr    new_handler,
1219  proc_ptr   *old_handler
1220);
1221
1222/**
1223 * @ingroup CPUInterrupt
1224 * This routine installs the hardware interrupt stack pointer.
1225 *
1226 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1227 *        is TRUE.
1228 *
1229 * Port Specific Information:
1230 *
1231 * XXX document implementation including references if appropriate
1232 */
1233void _CPU_Install_interrupt_stack( void );
1234
1235/**
1236 * This routine is the CPU dependent IDLE thread body.
1237 *
1238 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1239 *         is TRUE.
1240 *
1241 * Port Specific Information:
1242 *
1243 * XXX document implementation including references if appropriate
1244 */
1245void *_CPU_Thread_Idle_body( uintptr_t ignored );
1246
1247/**
1248 * @ingroup CPUContext
1249 *
1250 * This routine switches from the run context to the heir context.
1251 *
1252 * @param[in] run points to the context of the currently executing task
1253 * @param[in] heir points to the context of the heir task
1254 *
1255 * Port Specific Information:
1256 *
1257 * XXX document implementation including references if appropriate
1258 */
1259void _CPU_Context_switch(
1260  Context_Control  *run,
1261  Context_Control  *heir
1262);
1263
1264/**
1265 * @ingroup CPUContext
1266 *
1267 * This routine is generally used only to restart self in an
1268 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1269 *
1270 * @param[in] new_context points to the context to be restored.
1271 *
1272 * NOTE: May be unnecessary to reload some registers.
1273 *
1274 * Port Specific Information:
1275 *
1276 * XXX document implementation including references if appropriate
1277 */
1278void _CPU_Context_restore(
1279  Context_Control *new_context
1280) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1281
1282/**
1283 * @ingroup CPUContext
1284 *
1285 * This routine saves the floating point context passed to it.
1286 *
1287 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1288 * point context area
1289 *
1290 * @return on output @a *fp_context_ptr will contain the address that
1291 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1292 *
1293 * Port Specific Information:
1294 *
1295 * XXX document implementation including references if appropriate
1296 */
1297void _CPU_Context_save_fp(
1298  Context_Control_fp **fp_context_ptr
1299);
1300
1301/**
1302 * @ingroup CPUContext
1303 *
1304 * This routine restores the floating point context passed to it.
1305 *
1306 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1307 * point context area to restore
1308 *
1309 * @return on output @a *fp_context_ptr will contain the address that
1310 * should be used with @ref _CPU_Context_save_fp to save this context.
1311 *
1312 * Port Specific Information:
1313 *
1314 * XXX document implementation including references if appropriate
1315 */
1316void _CPU_Context_restore_fp(
1317  Context_Control_fp **fp_context_ptr
1318);
1319
1320/**
1321 * @ingroup CPUContext
1322 *
1323 * @brief Clobbers all volatile registers with values derived from the pattern
1324 * parameter.
1325 *
1326 * This function is used only in test sptests/spcontext01.
1327 *
1328 * @param[in] pattern Pattern used to generate distinct register values.
1329 *
1330 * @see _CPU_Context_validate().
1331 */
1332void _CPU_Context_volatile_clobber( uintptr_t pattern );
1333
1334/**
1335 * @ingroup CPUContext
1336 *
1337 * @brief Initializes and validates the CPU context with values derived from
1338 * the pattern parameter.
1339 *
1340 * This function will not return if the CPU context remains consistent.  In
1341 * case this function returns the CPU port is broken.
1342 *
1343 * This function is used only in test sptests/spcontext01.
1344 *
1345 * @param[in] pattern Pattern used to generate distinct register values.
1346 *
1347 * @see _CPU_Context_volatile_clobber().
1348 */
1349void _CPU_Context_validate( uintptr_t pattern );
1350
1351/**
1352 * @brief The set of registers that specifies the complete processor state.
1353 *
1354 * The CPU exception frame may be available in fatal error conditions like for
1355 * example illegal opcodes, instruction fetch errors, or data access errors.
1356 *
1357 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1358 * rtems_exception_frame_print().
1359 */
1360typedef struct {
1361  uint32_t processor_state_register;
1362  uint32_t integer_registers [1];
1363  double float_registers [1];
1364} CPU_Exception_frame;
1365
1366/**
1367 * @brief Prints the exception frame via printk().
1368 *
1369 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1370 */
1371void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1372
1373/**
1374 * @ingroup CPUEndian
1375 *
1376 * The following routine swaps the endian format of an unsigned int.
1377 * It must be static because it is referenced indirectly.
1378 *
1379 * This version will work on any processor, but if there is a better
1380 * way for your CPU PLEASE use it.  The most common way to do this is to:
1381 *
1382 *    swap least significant two bytes with 16-bit rotate
1383 *    swap upper and lower 16-bits
1384 *    swap most significant two bytes with 16-bit rotate
1385 *
1386 * Some CPUs have special instructions which swap a 32-bit quantity in
1387 * a single instruction (e.g. i486).  It is probably best to avoid
1388 * an "endian swapping control bit" in the CPU.  One good reason is
1389 * that interrupts would probably have to be disabled to ensure that
1390 * an interrupt does not try to access the same "chunk" with the wrong
1391 * endian.  Another good reason is that on some CPUs, the endian bit
1392 * endianness for ALL fetches -- both code and data -- so the code
1393 * will be fetched incorrectly.
1394 *
1395 * @param[in] value is the value to be swapped
1396 * @return the value after being endian swapped
1397 *
1398 * Port Specific Information:
1399 *
1400 * XXX document implementation including references if appropriate
1401 */
1402static inline uint32_t CPU_swap_u32(
1403  uint32_t value
1404)
1405{
1406  uint32_t byte1, byte2, byte3, byte4, swapped;
1407
1408  byte4 = (value >> 24) & 0xff;
1409  byte3 = (value >> 16) & 0xff;
1410  byte2 = (value >> 8)  & 0xff;
1411  byte1 =  value        & 0xff;
1412
1413  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1414  return swapped;
1415}
1416
1417/**
1418 * @ingroup CPUEndian
1419 *
1420 * This routine swaps a 16 bir quantity.
1421 *
1422 * @param[in] value is the value to be swapped
1423 * @return the value after being endian swapped
1424 */
1425#define CPU_swap_u16( value ) \
1426  (((value&0xff) << 8) | ((value >> 8)&0xff))
1427
1428#ifdef RTEMS_SMP
1429  /**
1430   * @brief Returns the index of the current processor.
1431   *
1432   * An architecture specific method must be used to obtain the index of the
1433   * current processor in the system.  The set of processor indices is the
1434   * range of integers starting with zero up to the processor count minus one.
1435   */
1436  RTEMS_COMPILER_PURE_ATTRIBUTE static inline uint32_t
1437    _CPU_SMP_Get_current_processor( void )
1438  {
1439    return 123;
1440  }
1441
1442  /**
1443   * @brief Sends an inter-processor interrupt to the specified target
1444   * processor.
1445   *
1446   * This operation is undefined for target processor indices out of range.
1447   *
1448   * @param[in] target_processor_index The target processor index.
1449   */
1450  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1451
1452  /**
1453   * @brief Broadcasts a processor event.
1454   *
1455   * Some architectures provide a low-level synchronization primitive for
1456   * processors in a multi-processor environment.  Processors waiting for this
1457   * event may go into a low-power state and stop generating system bus
1458   * transactions.  This function must ensure that preceding store operations
1459   * can be observed by other processors.
1460   *
1461   * @see _CPU_SMP_Processor_event_receive().
1462   */
1463  static inline void _CPU_SMP_Processor_event_broadcast( void )
1464  {
1465    __asm__ volatile ( "" : : : "memory" );
1466  }
1467
1468  /**
1469   * @brief Receives a processor event.
1470   *
1471   * This function will wait for the processor event and may wait forever if no
1472   * such event arrives.
1473   *
1474   * @see _CPU_SMP_Processor_event_broadcast().
1475   */
1476  static inline void _CPU_SMP_Processor_event_receive( void )
1477  {
1478    __asm__ volatile ( "" : : : "memory" );
1479  }
1480#endif
1481
1482#ifdef __cplusplus
1483}
1484#endif
1485
1486#endif
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