source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 52.0 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief NO_CPU Department Source
5 *
6 * This include file contains information pertaining to the NO_CPU
7 * processor.
8 */
9
10/*
11 *  This include file contains information pertaining to the XXX
12 *  processor.
13 *
14 *  @note This file is part of a porting template that is intended
15 *  to be used as the starting point when porting RTEMS to a new
16 *  CPU family.  The following needs to be done when using this as
17 *  the starting point for a new port:
18 *
19 *  + Anywhere there is an XXX, it should be replaced
20 *    with information about the CPU family being ported to.
21 *
22 *  + At the end of each comment section, there is a heading which
23 *    says "Port Specific Information:".  When porting to RTEMS,
24 *    add CPU family specific information in this section
25 */
26
27/*
28 *  COPYRIGHT (c) 1989-2008.
29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.org/license/LICENSE.
34 */
35
36#ifndef _RTEMS_SCORE_CPU_H
37#define _RTEMS_SCORE_CPU_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/types.h>
44#include <rtems/score/no_cpu.h>
45
46/* conditional compilation parameters */
47
48/**
49 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
50 *
51 * If TRUE, then they are inlined.
52 * If FALSE, then a subroutine call is made.
53 *
54 * This conditional is an example of the classic trade-off of size
55 * versus speed.  Inlining the call (TRUE) typically increases the
56 * size of RTEMS while speeding up the enabling of dispatching.
57 *
58 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
59 * only be 0 or 1 unless you are in an interrupt handler and that
60 * interrupt handler invokes the executive.]  When not inlined
61 * something calls @ref _Thread_Enable_dispatch which in turns calls
62 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
63 * one subroutine call is avoided entirely.
64 *
65 * Port Specific Information:
66 *
67 * XXX document implementation including references if appropriate
68 */
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/**
72 * Should the body of the search loops in _Thread_queue_Enqueue_priority
73 * be unrolled one time?  In unrolled each iteration of the loop examines
74 * two "nodes" on the chain being searched.  Otherwise, only one node
75 * is examined per iteration.
76 *
77 * If TRUE, then the loops are unrolled.
78 * If FALSE, then the loops are not unrolled.
79 *
80 * The primary factor in making this decision is the cost of disabling
81 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 * body of the loop.  On some CPUs, the flash is more expensive than
83 * one iteration of the loop body.  In this case, it might be desirable
84 * to unroll the loop.  It is important to note that on some CPUs, this
85 * code is the longest interrupt disable period in RTEMS.  So it is
86 * necessary to strike a balance when setting this parameter.
87 *
88 * Port Specific Information:
89 *
90 * XXX document implementation including references if appropriate
91 */
92#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
93
94/**
95 * Does RTEMS manage a dedicated interrupt stack in software?
96 *
97 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
98 * If FALSE, nothing is done.
99 *
100 * If the CPU supports a dedicated interrupt stack in hardware,
101 * then it is generally the responsibility of the BSP to allocate it
102 * and set it up.
103 *
104 * If the CPU does not support a dedicated interrupt stack, then
105 * the porter has two options: (1) execute interrupts on the
106 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
107 * interrupt stack.
108 *
109 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
110 *
111 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
112 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
113 * possible that both are FALSE for a particular CPU.  Although it
114 * is unclear what that would imply about the interrupt processing
115 * procedure on that CPU.
116 *
117 * Port Specific Information:
118 *
119 * XXX document implementation including references if appropriate
120 */
121#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
122
123/**
124 * Does the CPU follow the simple vectored interrupt model?
125 *
126 * If TRUE, then RTEMS allocates the vector table it internally manages.
127 * If FALSE, then the BSP is assumed to allocate and manage the vector
128 * table
129 *
130 * Port Specific Information:
131 *
132 * XXX document implementation including references if appropriate
133 */
134#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
135
136/**
137 * Does this CPU have hardware support for a dedicated interrupt stack?
138 *
139 * If TRUE, then it must be installed during initialization.
140 * If FALSE, then no installation is performed.
141 *
142 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
143 *
144 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
145 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
146 * possible that both are FALSE for a particular CPU.  Although it
147 * is unclear what that would imply about the interrupt processing
148 * procedure on that CPU.
149 *
150 * Port Specific Information:
151 *
152 * XXX document implementation including references if appropriate
153 */
154#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
155
156/**
157 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
158 *
159 * If TRUE, then the memory is allocated during initialization.
160 * If FALSE, then the memory is allocated during initialization.
161 *
162 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
163 *
164 * Port Specific Information:
165 *
166 * XXX document implementation including references if appropriate
167 */
168#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
169
170/**
171 * Does the RTEMS invoke the user's ISR with the vector number and
172 * a pointer to the saved interrupt frame (1) or just the vector
173 * number (0)?
174 *
175 * Port Specific Information:
176 *
177 * XXX document implementation including references if appropriate
178 */
179#define CPU_ISR_PASSES_FRAME_POINTER 0
180
181/**
182 * @def CPU_HARDWARE_FP
183 *
184 * Does the CPU have hardware floating point?
185 *
186 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
187 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
188 *
189 * If there is a FP coprocessor such as the i387 or mc68881, then
190 * the answer is TRUE.
191 *
192 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
193 * It indicates whether or not this CPU model has FP support.  For
194 * example, it would be possible to have an i386_nofp CPU model
195 * which set this to false to indicate that you have an i386 without
196 * an i387 and wish to leave floating point support out of RTEMS.
197 */
198
199/**
200 * @def CPU_SOFTWARE_FP
201 *
202 * Does the CPU have no hardware floating point and GCC provides a
203 * software floating point implementation which must be context
204 * switched?
205 *
206 * This feature conditional is used to indicate whether or not there
207 * is software implemented floating point that must be context
208 * switched.  The determination of whether or not this applies
209 * is very tool specific and the state saved/restored is also
210 * compiler specific.
211 *
212 * Port Specific Information:
213 *
214 * XXX document implementation including references if appropriate
215 */
216#if ( NO_CPU_HAS_FPU == 1 )
217#define CPU_HARDWARE_FP     TRUE
218#else
219#define CPU_HARDWARE_FP     FALSE
220#endif
221#define CPU_SOFTWARE_FP     FALSE
222
223/**
224 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
225 *
226 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
227 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
228 *
229 * So far, the only CPUs in which this option has been used are the
230 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
231 * gcc both implicitly used the floating point registers to perform
232 * integer multiplies.  Similarly, the PowerPC port of gcc has been
233 * seen to allocate floating point local variables and touch the FPU
234 * even when the flow through a subroutine (like vfprintf()) might
235 * not use floating point formats.
236 *
237 * If a function which you would not think utilize the FP unit DOES,
238 * then one can not easily predict which tasks will use the FP hardware.
239 * In this case, this option should be TRUE.
240 *
241 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
242 *
243 * Port Specific Information:
244 *
245 * XXX document implementation including references if appropriate
246 */
247#define CPU_ALL_TASKS_ARE_FP     TRUE
248
249/**
250 * Should the IDLE task have a floating point context?
251 *
252 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
253 * and it has a floating point context which is switched in and out.
254 * If FALSE, then the IDLE task does not have a floating point context.
255 *
256 * Setting this to TRUE negatively impacts the time required to preempt
257 * the IDLE task from an interrupt because the floating point context
258 * must be saved as part of the preemption.
259 *
260 * Port Specific Information:
261 *
262 * XXX document implementation including references if appropriate
263 */
264#define CPU_IDLE_TASK_IS_FP      FALSE
265
266/**
267 * Should the saving of the floating point registers be deferred
268 * until a context switch is made to another different floating point
269 * task?
270 *
271 * If TRUE, then the floating point context will not be stored until
272 * necessary.  It will remain in the floating point registers and not
273 * disturned until another floating point task is switched to.
274 *
275 * If FALSE, then the floating point context is saved when a floating
276 * point task is switched out and restored when the next floating point
277 * task is restored.  The state of the floating point registers between
278 * those two operations is not specified.
279 *
280 * If the floating point context does NOT have to be saved as part of
281 * interrupt dispatching, then it should be safe to set this to TRUE.
282 *
283 * Setting this flag to TRUE results in using a different algorithm
284 * for deciding when to save and restore the floating point context.
285 * The deferred FP switch algorithm minimizes the number of times
286 * the FP context is saved and restored.  The FP context is not saved
287 * until a context switch is made to another, different FP task.
288 * Thus in a system with only one FP task, the FP context will never
289 * be saved or restored.
290 *
291 * Port Specific Information:
292 *
293 * XXX document implementation including references if appropriate
294 */
295#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
296
297/**
298 * Does this port provide a CPU dependent IDLE task implementation?
299 *
300 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
301 * must be provided and is the default IDLE thread body instead of
302 * @ref _CPU_Thread_Idle_body.
303 *
304 * If FALSE, then use the generic IDLE thread body if the BSP does
305 * not provide one.
306 *
307 * This is intended to allow for supporting processors which have
308 * a low power or idle mode.  When the IDLE thread is executed, then
309 * the CPU can be powered down.
310 *
311 * The order of precedence for selecting the IDLE thread body is:
312 *
313 *   -#  BSP provided
314 *   -#  CPU dependent (if provided)
315 *   -#  generic (if no BSP and no CPU dependent)
316 *
317 * Port Specific Information:
318 *
319 * XXX document implementation including references if appropriate
320 */
321#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
322
323/**
324 * Does the stack grow up (toward higher addresses) or down
325 * (toward lower addresses)?
326 *
327 * If TRUE, then the grows upward.
328 * If FALSE, then the grows toward smaller addresses.
329 *
330 * Port Specific Information:
331 *
332 * XXX document implementation including references if appropriate
333 */
334#define CPU_STACK_GROWS_UP               TRUE
335
336/**
337 * The following is the variable attribute used to force alignment
338 * of critical RTEMS structures.  On some processors it may make
339 * sense to have these aligned on tighter boundaries than
340 * the minimum requirements of the compiler in order to have as
341 * much of the critical data area as possible in a cache line.
342 *
343 * The placement of this macro in the declaration of the variables
344 * is based on the syntactically requirements of the GNU C
345 * "__attribute__" extension.  For example with GNU C, use
346 * the following to force a structures to a 32 byte boundary.
347 *
348 *     __attribute__ ((aligned (32)))
349 *
350 * NOTE: Currently only the Priority Bit Map table uses this feature.
351 *       To benefit from using this, the data must be heavily
352 *       used so it will stay in the cache and used frequently enough
353 *       in the executive to justify turning this on.
354 *
355 * Port Specific Information:
356 *
357 * XXX document implementation including references if appropriate
358 */
359#define CPU_STRUCTURE_ALIGNMENT
360
361/**
362 * @defgroup CPUTimestamp Processor Dependent Timestamp Support
363 *
364 * This group assists in issues related to timestamp implementation.
365 *
366 * The port must choose exactly one of the following defines:
367 * - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
368 * - #define CPU_TIMESTAMP_USE_INT64 TRUE
369 * - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
370 *
371 * Performance of int64_t versus struct timespec
372 * =============================================
373 *
374 * On PowerPC/psim, inlined int64_t saves ~50 instructions on each
375 *   _Thread_Dispatch operation which results in a context switch.
376 *   This works out to be about 10% faster dispatches and 7.5% faster
377 *   blocking semaphore obtains.  The following numbers are in instructions
378 *   and from tm02 and tm26.
379 *
380 *                        timespec  int64  inlined int64
381 *   dispatch:              446      446      400
382 *   blocking sem obtain:   627      626      581
383 *
384 * On SPARC/sis, inlined int64_t shows the same percentage gains.
385 *   The following numbers are in microseconds and from tm02 and tm26.
386 *
387 *                        timespec  int64  inlined int64
388 *   dispatch:               59       61       53
389 *   blocking sem obtain:    98      100       92
390 *
391 * Inlining appears to have a tendency to increase the size of
392 *   some executables.
393 * Not inlining reduces the execution improvement but does not seem to
394 *   be an improvement on the PowerPC and SPARC. The struct timespec
395 *   and the executables with int64 not inlined are about the same size.
396 *
397 */
398/**@{**/
399
400/**
401 * Selects the timestamp implementation using struct timespec.
402 *
403 * Port Specific Information:
404 *
405 * XXX document implementation including references if appropriate
406 */
407#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
408
409/**
410 * Selects the timestamp implementation using int64_t and no inlined methods.
411 *
412 * Port Specific Information:
413 *
414 * XXX document implementation including references if appropriate
415 */
416#define CPU_TIMESTAMP_USE_INT64 TRUE
417
418/**
419 * Selects the timestamp implementation using int64_t and inlined methods.
420 *
421 * Port Specific Information:
422 *
423 * XXX document implementation including references if appropriate
424 */
425#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
426
427/** @} */
428
429/**
430 * @defgroup CPUEndian Processor Dependent Endianness Support
431 *
432 * This group assists in issues related to processor endianness.
433 *
434 */
435/**@{**/
436
437/**
438 * Define what is required to specify how the network to host conversion
439 * routines are handled.
440 *
441 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
442 * same values.
443 *
444 * @see CPU_LITTLE_ENDIAN
445 *
446 * Port Specific Information:
447 *
448 * XXX document implementation including references if appropriate
449 */
450#define CPU_BIG_ENDIAN                           TRUE
451
452/**
453 * Define what is required to specify how the network to host conversion
454 * routines are handled.
455 *
456 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
457 * same values.
458 *
459 * @see CPU_BIG_ENDIAN
460 *
461 * Port Specific Information:
462 *
463 * XXX document implementation including references if appropriate
464 */
465#define CPU_LITTLE_ENDIAN                        FALSE
466
467/** @} */
468
469/**
470 * @ingroup CPUInterrupt
471 *
472 * The following defines the number of bits actually used in the
473 * interrupt field of the task mode.  How those bits map to the
474 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
475 *
476 * Port Specific Information:
477 *
478 * XXX document implementation including references if appropriate
479 */
480#define CPU_MODES_INTERRUPT_MASK   0x00000001
481
482/**
483 * @brief The size of the CPU specific per-CPU control.
484 *
485 * This define must be visible to assember files since it is used to derive
486 * structure offsets.
487 */
488#define CPU_PER_CPU_CONTROL_SIZE 0
489
490/*
491 *  Processor defined structures required for cpukit/score.
492 *
493 *  Port Specific Information:
494 *
495 *  XXX document implementation including references if appropriate
496 */
497
498/* may need to put some structures here.  */
499
500/**
501 * @brief The CPU specific per-CPU control.
502 *
503 * The CPU port can place here all state information that must be available and
504 * maintained for each CPU in the system.
505 */
506typedef struct {
507  /* CPU specific per-CPU state */
508} CPU_Per_CPU_control;
509
510/**
511 * @defgroup CPUContext Processor Dependent Context Management
512 *
513 * From the highest level viewpoint, there are 2 types of context to save.
514 *
515 *    -# Interrupt registers to save
516 *    -# Task level registers to save
517 *
518 * Since RTEMS handles integer and floating point contexts separately, this
519 * means we have the following 3 context items:
520 *
521 *    -# task level context stuff::  Context_Control
522 *    -# floating point task stuff:: Context_Control_fp
523 *    -# special interrupt level context :: CPU_Interrupt_frame
524 *
525 * On some processors, it is cost-effective to save only the callee
526 * preserved registers during a task context switch.  This means
527 * that the ISR code needs to save those registers which do not
528 * persist across function calls.  It is not mandatory to make this
529 * distinctions between the caller/callee saves registers for the
530 * purpose of minimizing context saved during task switch and on interrupts.
531 * If the cost of saving extra registers is minimal, simplicity is the
532 * choice.  Save the same context on interrupt entry as for tasks in
533 * this case.
534 *
535 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
536 * care should be used in designing the context area.
537 *
538 * On some CPUs with hardware floating point support, the Context_Control_fp
539 * structure will not be used or it simply consist of an array of a
540 * fixed number of bytes.   This is done when the floating point context
541 * is dumped by a "FP save context" type instruction and the format
542 * is not really defined by the CPU.  In this case, there is no need
543 * to figure out the exact format -- only the size.  Of course, although
544 * this is enough information for RTEMS, it is probably not enough for
545 * a debugger such as gdb.  But that is another problem.
546 *
547 * Port Specific Information:
548 *
549 * XXX document implementation including references if appropriate
550 *
551 */
552/**@{**/
553
554/**
555 * @ingroup Management
556 * This defines the minimal set of integer and processor state registers
557 * that must be saved during a voluntary context switch from one thread
558 * to another.
559 */
560typedef struct {
561    /**
562     * This field is a hint that a port will have a number of integer
563     * registers that need to be saved at a context switch.
564     */
565    uint32_t   some_integer_register;
566    /**
567     * This field is a hint that a port will have a number of system
568     * registers that need to be saved at a context switch.
569     */
570    uint32_t   some_system_register;
571
572    /**
573     * This field is a hint that a port will have a register that
574     * is the stack pointer.
575     */
576    uint32_t   stack_pointer;
577
578#ifdef RTEMS_SMP
579    /**
580     * @brief On SMP configurations the thread context must contain a boolean
581     * indicator to signal if this context is executing on a processor.
582     *
583     * This field must be updated during a context switch.  The context switch
584     * to the heir must wait until the heir context indicates that it is no
585     * longer executing on a processor.  The context switch must also check if
586     * a thread dispatch is necessary to honor updates of the heir thread for
587     * this processor.  This indicator must be updated using an atomic test and
588     * set operation to ensure that at most one processor uses the heir
589     * context at the same time.
590     *
591     * @code
592     * void _CPU_Context_switch(
593     *   Context_Control *executing,
594     *   Context_Control *heir
595     * )
596     * {
597     *   save( executing );
598     *
599     *   executing->is_executing = false;
600     *   memory_barrier();
601     *
602     *   if ( test_and_set( &heir->is_executing ) ) {
603     *     do {
604     *       Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot();
605     *
606     *       if ( cpu_self->dispatch_necessary ) {
607     *         heir = _Thread_Get_heir_and_make_it_executing( cpu_self );
608     *       }
609     *     } while ( test_and_set( &heir->is_executing ) );
610     *   }
611     *
612     *   restore( heir );
613     * }
614     * @endcode
615     */
616    volatile bool is_executing;
617#endif
618} Context_Control;
619
620/**
621 * @ingroup Management
622 *
623 * This macro returns the stack pointer associated with @a _context.
624 *
625 * @param[in] _context is the thread context area to access
626 *
627 * @return This method returns the stack pointer.
628 */
629#define _CPU_Context_Get_SP( _context ) \
630  (_context)->stack_pointer
631
632/**
633 * @ingroup Management
634 *
635 * This defines the complete set of floating point registers that must
636 * be saved during any context switch from one thread to another.
637 */
638typedef struct {
639    /** FPU registers are listed here */
640    double      some_float_register;
641} Context_Control_fp;
642
643/**
644 * @ingroup Management
645 *
646 * This defines the set of integer and processor state registers that must
647 * be saved during an interrupt.  This set does not include any which are
648 * in @ref Context_Control.
649 */
650typedef struct {
651    /**
652     * This field is a hint that a port will have a number of integer
653     * registers that need to be saved when an interrupt occurs or
654     * when a context switch occurs at the end of an ISR.
655     */
656    uint32_t   special_interrupt_register;
657} CPU_Interrupt_frame;
658
659/**
660 * This variable is optional.  It is used on CPUs on which it is difficult
661 * to generate an "uninitialized" FP context.  It is filled in by
662 * @ref _CPU_Initialize and copied into the task's FP context area during
663 * @ref _CPU_Context_Initialize.
664 *
665 * Port Specific Information:
666 *
667 * XXX document implementation including references if appropriate
668 */
669SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
670
671/** @} */
672
673/**
674 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
675 *
676 * On some CPUs, RTEMS supports a software managed interrupt stack.
677 * This stack is allocated by the Interrupt Manager and the switch
678 * is performed in @ref _ISR_Handler.  These variables contain pointers
679 * to the lowest and highest addresses in the chunk of memory allocated
680 * for the interrupt stack.  Since it is unknown whether the stack
681 * grows up or down (in general), this give the CPU dependent
682 * code the option of picking the version it wants to use.
683 *
684 * NOTE: These two variables are required if the macro
685 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
686 *
687 * Port Specific Information:
688 *
689 * XXX document implementation including references if appropriate
690 */
691
692/*
693 *  Nothing prevents the porter from declaring more CPU specific variables.
694 *
695 *  Port Specific Information:
696 *
697 *  XXX document implementation including references if appropriate
698 */
699
700/* XXX: if needed, put more variables here */
701
702/**
703 * @ingroup CPUContext
704 *
705 * The size of the floating point context area.  On some CPUs this
706 * will not be a "sizeof" because the format of the floating point
707 * area is not defined -- only the size is.  This is usually on
708 * CPUs with a "floating point save context" instruction.
709 *
710 * Port Specific Information:
711 *
712 * XXX document implementation including references if appropriate
713 */
714#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
715
716/**
717 * Amount of extra stack (above minimum stack size) required by
718 * MPCI receive server thread.  Remember that in a multiprocessor
719 * system this thread must exist and be able to process all directives.
720 *
721 * Port Specific Information:
722 *
723 * XXX document implementation including references if appropriate
724 */
725#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
726
727/**
728 * @ingroup CPUInterrupt
729 *
730 * This defines the number of entries in the _ISR_Vector_table managed by RTEMS
731 * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be a
732 * compile-time constant.
733 *
734 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
735 * FALSE.
736 */
737#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
738
739/**
740 * @ingroup CPUInterrupt
741 *
742 * This defines the highest interrupt vector number for this port in case
743 * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be less than
744 * CPU_INTERRUPT_NUMBER_OF_VECTORS.  It may be not a compile-time constant.
745 *
746 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
747 * FALSE.
748 */
749#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
750
751/**
752 * @ingroup CPUInterrupt
753 *
754 * This is defined if the port has a special way to report the ISR nesting
755 * level.  Most ports maintain the variable @a _ISR_Nest_level.
756 */
757#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
758
759/**
760 * @ingroup CPUContext
761 *
762 * Should be large enough to run all RTEMS tests.  This ensures
763 * that a "reasonable" small application should not have any problems.
764 *
765 * Port Specific Information:
766 *
767 * XXX document implementation including references if appropriate
768 */
769#define CPU_STACK_MINIMUM_SIZE          (1024*4)
770
771/**
772 * Size of a pointer.
773 *
774 * This must be an integer literal that can be used by the assembler.  This
775 * value will be used to calculate offsets of structure members.  These
776 * offsets will be used in assembler code.
777 */
778#define CPU_SIZEOF_POINTER         4
779
780/**
781 * CPU's worst alignment requirement for data types on a byte boundary.  This
782 * alignment does not take into account the requirements for the stack.  It
783 * must be a power of two greater than or equal to two.  The power of two
784 * requirement makes it possible to align values easily using simple bit
785 * operations.
786 *
787 * Port Specific Information:
788 *
789 * XXX document implementation including references if appropriate
790 */
791#define CPU_ALIGNMENT              8
792
793/**
794 * This number corresponds to the byte alignment requirement for the
795 * heap handler.  This alignment requirement may be stricter than that
796 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
797 * common for the heap to follow the same alignment requirement as
798 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
799 * the heap, then this should be set to @ref CPU_ALIGNMENT.
800 *
801 * NOTE:  It must be a power of two greater than or equal to two.  The
802 *        requirement to be a multiple of two is because the heap uses the
803 *        least significant field of the front and back flags to indicate that
804 *        a block is in use or free.  So you do not want any odd length blocks
805 *        really putting length data in that bit.
806 *
807 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
808 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
809 *        elements allocated from the heap meet all restrictions.
810 *
811 * Port Specific Information:
812 *
813 * XXX document implementation including references if appropriate
814 */
815#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
816
817/**
818 * This number corresponds to the byte alignment requirement for memory
819 * buffers allocated by the partition manager.  This alignment requirement
820 * may be stricter than that for the data types alignment specified by
821 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
822 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
823 * strict enough for the partition, then this should be set to
824 * @ref CPU_ALIGNMENT.
825 *
826 * NOTE:  This does not have to be a power of 2.  It does have to
827 *        be greater or equal to than @ref CPU_ALIGNMENT.
828 *
829 * Port Specific Information:
830 *
831 * XXX document implementation including references if appropriate
832 */
833#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
834
835/**
836 * This number corresponds to the byte alignment requirement for the
837 * stack.  This alignment requirement may be stricter than that for the
838 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
839 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
840 * set to 0.
841 *
842 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
843 *
844 * Port Specific Information:
845 *
846 * XXX document implementation including references if appropriate
847 */
848#define CPU_STACK_ALIGNMENT        0
849
850/*
851 *  ISR handler macros
852 */
853
854/**
855 * @ingroup CPUInterrupt
856 *
857 * Support routine to initialize the RTEMS vector table after it is allocated.
858 *
859 * Port Specific Information:
860 *
861 * XXX document implementation including references if appropriate
862 */
863#define _CPU_Initialize_vectors()
864
865/**
866 * @ingroup CPUInterrupt
867 *
868 * Disable all interrupts for an RTEMS critical section.  The previous
869 * level is returned in @a _isr_cookie.
870 *
871 * @param[out] _isr_cookie will contain the previous level cookie
872 *
873 * Port Specific Information:
874 *
875 * XXX document implementation including references if appropriate
876 */
877#define _CPU_ISR_Disable( _isr_cookie ) \
878  { \
879    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
880  }
881
882/**
883 * @ingroup CPUInterrupt
884 *
885 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
886 * This indicates the end of an RTEMS critical section.  The parameter
887 * @a _isr_cookie is not modified.
888 *
889 * @param[in] _isr_cookie contain the previous level cookie
890 *
891 * Port Specific Information:
892 *
893 * XXX document implementation including references if appropriate
894 */
895#define _CPU_ISR_Enable( _isr_cookie )  \
896  { \
897  }
898
899/**
900 * @ingroup CPUInterrupt
901 *
902 * This temporarily restores the interrupt to @a _isr_cookie before immediately
903 * disabling them again.  This is used to divide long RTEMS critical
904 * sections into two or more parts.  The parameter @a _isr_cookie is not
905 * modified.
906 *
907 * @param[in] _isr_cookie contain the previous level cookie
908 *
909 * Port Specific Information:
910 *
911 * XXX document implementation including references if appropriate
912 */
913#define _CPU_ISR_Flash( _isr_cookie ) \
914  { \
915  }
916
917/**
918 * @ingroup CPUInterrupt
919 *
920 * This routine and @ref _CPU_ISR_Get_level
921 * Map the interrupt level in task mode onto the hardware that the CPU
922 * actually provides.  Currently, interrupt levels which do not
923 * map onto the CPU in a generic fashion are undefined.  Someday,
924 * it would be nice if these were "mapped" by the application
925 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
926 * 8 - 255 would be available for bsp/application specific meaning.
927 * This could be used to manage a programmable interrupt controller
928 * via the rtems_task_mode directive.
929 *
930 * Port Specific Information:
931 *
932 * XXX document implementation including references if appropriate
933 */
934#define _CPU_ISR_Set_level( new_level ) \
935  { \
936  }
937
938/**
939 * @ingroup CPUInterrupt
940 *
941 * Return the current interrupt disable level for this task in
942 * the format used by the interrupt level portion of the task mode.
943 *
944 * NOTE: This routine usually must be implemented as a subroutine.
945 *
946 * Port Specific Information:
947 *
948 * XXX document implementation including references if appropriate
949 */
950uint32_t   _CPU_ISR_Get_level( void );
951
952/* end of ISR handler macros */
953
954/* Context handler macros */
955
956/**
957 *  @ingroup CPUContext
958 *
959 * Initialize the context to a state suitable for starting a
960 * task after a context restore operation.  Generally, this
961 * involves:
962 *
963 *    - setting a starting address
964 *    - preparing the stack
965 *    - preparing the stack and frame pointers
966 *    - setting the proper interrupt level in the context
967 *    - initializing the floating point context
968 *
969 * This routine generally does not set any unnecessary register
970 * in the context.  The state of the "general data" registers is
971 * undefined at task start time.
972 *
973 * @param[in] _the_context is the context structure to be initialized
974 * @param[in] _stack_base is the lowest physical address of this task's stack
975 * @param[in] _size is the size of this task's stack
976 * @param[in] _isr is the interrupt disable level
977 * @param[in] _entry_point is the thread's entry point.  This is
978 *        always @a _Thread_Handler
979 * @param[in] _is_fp is TRUE if the thread is to be a floating
980 *       point thread.  This is typically only used on CPUs where the
981 *       FPU may be easily disabled by software such as on the SPARC
982 *       where the PSR contains an enable FPU bit.
983 * @param[in] _tls_area The thread-local storage (TLS) area.
984 *
985 * Port Specific Information:
986 *
987 * XXX document implementation including references if appropriate
988 */
989#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
990                                 _isr, _entry_point, _is_fp, _tls_area ) \
991  { \
992  }
993
994/**
995 * This routine is responsible for somehow restarting the currently
996 * executing task.  If you are lucky, then all that is necessary
997 * is restoring the context.  Otherwise, there will need to be
998 * a special assembly routine which does something special in this
999 * case.  For many ports, simply adding a label to the restore path
1000 * of @ref _CPU_Context_switch will work.  On other ports, it may be
1001 * possibly to load a few arguments and jump to the restore path. It will
1002 * not work if restarting self conflicts with the stack frame
1003 * assumptions of restoring a context.
1004 *
1005 * Port Specific Information:
1006 *
1007 * XXX document implementation including references if appropriate
1008 */
1009#define _CPU_Context_Restart_self( _the_context ) \
1010   _CPU_Context_restore( (_the_context) );
1011
1012/**
1013 * @ingroup CPUContext
1014 *
1015 * The purpose of this macro is to allow the initial pointer into
1016 * a floating point context area (used to save the floating point
1017 * context) to be at an arbitrary place in the floating point
1018 *context area.
1019 *
1020 * This is necessary because some FP units are designed to have
1021 * their context saved as a stack which grows into lower addresses.
1022 * Other FP units can be saved by simply moving registers into offsets
1023 * from the base of the context area.  Finally some FP units provide
1024 * a "dump context" instruction which could fill in from high to low
1025 * or low to high based on the whim of the CPU designers.
1026 *
1027 * @param[in] _base is the lowest physical address of the floating point
1028 *        context area
1029 * @param[in] _offset is the offset into the floating point area
1030 *
1031 * Port Specific Information:
1032 *
1033 * XXX document implementation including references if appropriate
1034 */
1035#define _CPU_Context_Fp_start( _base, _offset ) \
1036   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
1037
1038/**
1039 * This routine initializes the FP context area passed to it to.
1040 * There are a few standard ways in which to initialize the
1041 * floating point context.  The code included for this macro assumes
1042 * that this is a CPU in which a "initial" FP context was saved into
1043 * @a _CPU_Null_fp_context and it simply copies it to the destination
1044 * context passed to it.
1045 *
1046 * Other floating point context save/restore models include:
1047 *   -# not doing anything, and
1048 *   -# putting a "null FP status word" in the correct place in the FP context.
1049 *
1050 * @param[in] _destination is the floating point context area
1051 *
1052 * Port Specific Information:
1053 *
1054 * XXX document implementation including references if appropriate
1055 */
1056#define _CPU_Context_Initialize_fp( _destination ) \
1057  { \
1058   *(*(_destination)) = _CPU_Null_fp_context; \
1059  }
1060
1061/* end of Context handler macros */
1062
1063/* Fatal Error manager macros */
1064
1065/**
1066 * This routine copies _error into a known place -- typically a stack
1067 * location or a register, optionally disables interrupts, and
1068 * halts/stops the CPU.
1069 *
1070 * Port Specific Information:
1071 *
1072 * XXX document implementation including references if appropriate
1073 */
1074#define _CPU_Fatal_halt( _source, _error ) \
1075  { \
1076  }
1077
1078/* end of Fatal Error manager macros */
1079
1080/* Bitfield handler macros */
1081
1082/**
1083 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1084 *
1085 * This set of routines are used to implement fast searches for
1086 * the most important ready task.
1087 *
1088 */
1089/**@{**/
1090
1091/**
1092 * This definition is set to TRUE if the port uses the generic bitfield
1093 * manipulation implementation.
1094 */
1095#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1096
1097/**
1098 * This definition is set to TRUE if the port uses the data tables provided
1099 * by the generic bitfield manipulation implementation.
1100 * This can occur when actually using the generic bitfield manipulation
1101 * implementation or when implementing the same algorithm in assembly
1102 * language for improved performance.  It is unlikely that a port will use
1103 * the data if it has a bitfield scan instruction.
1104 */
1105#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1106
1107/**
1108 * This routine sets @a _output to the bit number of the first bit
1109 * set in @a _value.  @a _value is of CPU dependent type
1110 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
1111 * wide although only the 16 least significant bits will be used.
1112 *
1113 * There are a number of variables in using a "find first bit" type
1114 * instruction.
1115 *
1116 *   -# What happens when run on a value of zero?
1117 *   -# Bits may be numbered from MSB to LSB or vice-versa.
1118 *   -# The numbering may be zero or one based.
1119 *   -# The "find first bit" instruction may search from MSB or LSB.
1120 *
1121 * RTEMS guarantees that (1) will never happen so it is not a concern.
1122 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1123 * @ref _CPU_Priority_bits_index.  These three form a set of routines
1124 * which must logically operate together.  Bits in the _value are
1125 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
1126 * The basic major and minor values calculated by @ref _Priority_Major
1127 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1128 * to properly range between the values returned by the "find first bit"
1129 * instruction.  This makes it possible for @ref _Priority_Get_highest to
1130 * calculate the major and directly index into the minor table.
1131 * This mapping is necessary to ensure that 0 (a high priority major/minor)
1132 * is the first bit found.
1133 *
1134 * This entire "find first bit" and mapping process depends heavily
1135 * on the manner in which a priority is broken into a major and minor
1136 * components with the major being the 4 MSB of a priority and minor
1137 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1138 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1139 * to the lowest priority.
1140 *
1141 * If your CPU does not have a "find first bit" instruction, then
1142 * there are ways to make do without it.  Here are a handful of ways
1143 * to implement this in software:
1144 *
1145@verbatim
1146      - a series of 16 bit test instructions
1147      - a "binary search using if's"
1148      - _number = 0
1149        if _value > 0x00ff
1150          _value >>=8
1151          _number = 8;
1152
1153        if _value > 0x0000f
1154          _value >=8
1155          _number += 4
1156
1157        _number += bit_set_table[ _value ]
1158@endverbatim
1159
1160 *   where bit_set_table[ 16 ] has values which indicate the first
1161 *     bit set
1162 *
1163 * @param[in] _value is the value to be scanned
1164 * @param[in] _output is the first bit set
1165 *
1166 * Port Specific Information:
1167 *
1168 * XXX document implementation including references if appropriate
1169 */
1170
1171#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1172#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1173  { \
1174    (_output) = 0;   /* do something to prevent warnings */ \
1175  }
1176#endif
1177
1178/** @} */
1179
1180/* end of Bitfield handler macros */
1181
1182/**
1183 * This routine builds the mask which corresponds to the bit fields
1184 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1185 * for that routine.
1186 *
1187 * Port Specific Information:
1188 *
1189 * XXX document implementation including references if appropriate
1190 */
1191#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1192
1193#define _CPU_Priority_Mask( _bit_number ) \
1194  ( 1 << (_bit_number) )
1195
1196#endif
1197
1198/**
1199 * @ingroup CPUBitfield
1200 *
1201 * This routine translates the bit numbers returned by
1202 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1203 * a major or minor component of a priority.  See the discussion
1204 * for that routine.
1205 *
1206 * @param[in] _priority is the major or minor number to translate
1207 *
1208 * Port Specific Information:
1209 *
1210 * XXX document implementation including references if appropriate
1211 */
1212#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1213
1214#define _CPU_Priority_bits_index( _priority ) \
1215  (_priority)
1216
1217#endif
1218
1219/* end of Priority handler macros */
1220
1221/* functions */
1222
1223/**
1224 * This routine performs CPU dependent initialization.
1225 *
1226 * Port Specific Information:
1227 *
1228 * XXX document implementation including references if appropriate
1229 */
1230void _CPU_Initialize(void);
1231
1232/**
1233 * @ingroup CPUInterrupt
1234 *
1235 * This routine installs a "raw" interrupt handler directly into the
1236 * processor's vector table.
1237 *
1238 * @param[in] vector is the vector number
1239 * @param[in] new_handler is the raw ISR handler to install
1240 * @param[in] old_handler is the previously installed ISR Handler
1241 *
1242 * Port Specific Information:
1243 *
1244 * XXX document implementation including references if appropriate
1245 */
1246void _CPU_ISR_install_raw_handler(
1247  uint32_t    vector,
1248  proc_ptr    new_handler,
1249  proc_ptr   *old_handler
1250);
1251
1252/**
1253 * @ingroup CPUInterrupt
1254 *
1255 * This routine installs an interrupt vector.
1256 *
1257 * @param[in] vector is the vector number
1258 * @param[in] new_handler is the RTEMS ISR handler to install
1259 * @param[in] old_handler is the previously installed ISR Handler
1260 *
1261 * Port Specific Information:
1262 *
1263 * XXX document implementation including references if appropriate
1264 */
1265void _CPU_ISR_install_vector(
1266  uint32_t    vector,
1267  proc_ptr    new_handler,
1268  proc_ptr   *old_handler
1269);
1270
1271/**
1272 * @ingroup CPUInterrupt
1273 * This routine installs the hardware interrupt stack pointer.
1274 *
1275 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1276 *        is TRUE.
1277 *
1278 * Port Specific Information:
1279 *
1280 * XXX document implementation including references if appropriate
1281 */
1282void _CPU_Install_interrupt_stack( void );
1283
1284/**
1285 * This routine is the CPU dependent IDLE thread body.
1286 *
1287 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1288 *         is TRUE.
1289 *
1290 * Port Specific Information:
1291 *
1292 * XXX document implementation including references if appropriate
1293 */
1294void *_CPU_Thread_Idle_body( uintptr_t ignored );
1295
1296/**
1297 * @ingroup CPUContext
1298 *
1299 * This routine switches from the run context to the heir context.
1300 *
1301 * @param[in] run points to the context of the currently executing task
1302 * @param[in] heir points to the context of the heir task
1303 *
1304 * Port Specific Information:
1305 *
1306 * XXX document implementation including references if appropriate
1307 */
1308void _CPU_Context_switch(
1309  Context_Control  *run,
1310  Context_Control  *heir
1311);
1312
1313/**
1314 * @ingroup CPUContext
1315 *
1316 * This routine is generally used only to restart self in an
1317 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1318 *
1319 * @param[in] new_context points to the context to be restored.
1320 *
1321 * NOTE: May be unnecessary to reload some registers.
1322 *
1323 * Port Specific Information:
1324 *
1325 * XXX document implementation including references if appropriate
1326 */
1327void _CPU_Context_restore(
1328  Context_Control *new_context
1329) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1330
1331/**
1332 * @ingroup CPUContext
1333 *
1334 * This routine saves the floating point context passed to it.
1335 *
1336 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1337 * point context area
1338 *
1339 * @return on output @a *fp_context_ptr will contain the address that
1340 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1341 *
1342 * Port Specific Information:
1343 *
1344 * XXX document implementation including references if appropriate
1345 */
1346void _CPU_Context_save_fp(
1347  Context_Control_fp **fp_context_ptr
1348);
1349
1350/**
1351 * @ingroup CPUContext
1352 *
1353 * This routine restores the floating point context passed to it.
1354 *
1355 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1356 * point context area to restore
1357 *
1358 * @return on output @a *fp_context_ptr will contain the address that
1359 * should be used with @ref _CPU_Context_save_fp to save this context.
1360 *
1361 * Port Specific Information:
1362 *
1363 * XXX document implementation including references if appropriate
1364 */
1365void _CPU_Context_restore_fp(
1366  Context_Control_fp **fp_context_ptr
1367);
1368
1369/**
1370 * @ingroup CPUContext
1371 *
1372 * @brief Clobbers all volatile registers with values derived from the pattern
1373 * parameter.
1374 *
1375 * This function is used only in test sptests/spcontext01.
1376 *
1377 * @param[in] pattern Pattern used to generate distinct register values.
1378 *
1379 * @see _CPU_Context_validate().
1380 */
1381void _CPU_Context_volatile_clobber( uintptr_t pattern );
1382
1383/**
1384 * @ingroup CPUContext
1385 *
1386 * @brief Initializes and validates the CPU context with values derived from
1387 * the pattern parameter.
1388 *
1389 * This function will not return if the CPU context remains consistent.  In
1390 * case this function returns the CPU port is broken.
1391 *
1392 * This function is used only in test sptests/spcontext01.
1393 *
1394 * @param[in] pattern Pattern used to generate distinct register values.
1395 *
1396 * @see _CPU_Context_volatile_clobber().
1397 */
1398void _CPU_Context_validate( uintptr_t pattern );
1399
1400/**
1401 * @brief The set of registers that specifies the complete processor state.
1402 *
1403 * The CPU exception frame may be available in fatal error conditions like for
1404 * example illegal opcodes, instruction fetch errors, or data access errors.
1405 *
1406 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1407 * rtems_exception_frame_print().
1408 */
1409typedef struct {
1410  uint32_t processor_state_register;
1411  uint32_t integer_registers [1];
1412  double float_registers [1];
1413} CPU_Exception_frame;
1414
1415/**
1416 * @brief Prints the exception frame via printk().
1417 *
1418 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1419 */
1420void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1421
1422/**
1423 * @ingroup CPUEndian
1424 *
1425 * The following routine swaps the endian format of an unsigned int.
1426 * It must be static because it is referenced indirectly.
1427 *
1428 * This version will work on any processor, but if there is a better
1429 * way for your CPU PLEASE use it.  The most common way to do this is to:
1430 *
1431 *    swap least significant two bytes with 16-bit rotate
1432 *    swap upper and lower 16-bits
1433 *    swap most significant two bytes with 16-bit rotate
1434 *
1435 * Some CPUs have special instructions which swap a 32-bit quantity in
1436 * a single instruction (e.g. i486).  It is probably best to avoid
1437 * an "endian swapping control bit" in the CPU.  One good reason is
1438 * that interrupts would probably have to be disabled to ensure that
1439 * an interrupt does not try to access the same "chunk" with the wrong
1440 * endian.  Another good reason is that on some CPUs, the endian bit
1441 * endianness for ALL fetches -- both code and data -- so the code
1442 * will be fetched incorrectly.
1443 *
1444 * @param[in] value is the value to be swapped
1445 * @return the value after being endian swapped
1446 *
1447 * Port Specific Information:
1448 *
1449 * XXX document implementation including references if appropriate
1450 */
1451static inline uint32_t CPU_swap_u32(
1452  uint32_t value
1453)
1454{
1455  uint32_t byte1, byte2, byte3, byte4, swapped;
1456
1457  byte4 = (value >> 24) & 0xff;
1458  byte3 = (value >> 16) & 0xff;
1459  byte2 = (value >> 8)  & 0xff;
1460  byte1 =  value        & 0xff;
1461
1462  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1463  return swapped;
1464}
1465
1466/**
1467 * @ingroup CPUEndian
1468 *
1469 * This routine swaps a 16 bir quantity.
1470 *
1471 * @param[in] value is the value to be swapped
1472 * @return the value after being endian swapped
1473 */
1474#define CPU_swap_u16( value ) \
1475  (((value&0xff) << 8) | ((value >> 8)&0xff))
1476
1477/**
1478 * @brief Unsigned integer type for CPU counter values.
1479 */
1480typedef uint32_t CPU_Counter_ticks;
1481
1482/**
1483 * @brief Returns the current CPU counter value.
1484 *
1485 * A CPU counter is some free-running counter.  It ticks usually with a
1486 * frequency close to the CPU or system bus clock.  The board support package
1487 * must ensure that this function works before the RTEMS initialization.
1488 * Otherwise invalid profiling statistics will be gathered.
1489 *
1490 * @return The current CPU counter value.
1491 */
1492CPU_Counter_ticks _CPU_Counter_read( void );
1493
1494/**
1495 * @brief Returns the difference between the second and first CPU counter
1496 * value.
1497 *
1498 * This operation may be carried out as a modulo operation depending on the
1499 * range of the CPU counter device.
1500 *
1501 * @param[in] second The second CPU counter value.
1502 * @param[in] first The first CPU counter value.
1503 *
1504 * @return Returns second minus first modulo counter period.
1505 */
1506CPU_Counter_ticks _CPU_Counter_difference(
1507  CPU_Counter_ticks second,
1508  CPU_Counter_ticks first
1509);
1510
1511/**
1512 * @brief Special register pointing to the per-CPU control of the current
1513 * processor.
1514 *
1515 * This is optional.  Not every CPU port needs this.  It is only an optional
1516 * optimization variant.
1517 */
1518register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" );
1519
1520/**
1521 * @brief Optional method to obtain the per-CPU control of the current processor.
1522 *
1523 * This is optional.  Not every CPU port needs this.  It is only an optional
1524 * optimization variant.  In case this macro is undefined, the default
1525 * implementation using the current processor index will be used.
1526 */
1527#define _CPU_Get_current_per_CPU_control() ( _CPU_Per_CPU_current )
1528
1529#ifdef RTEMS_SMP
1530  /**
1531   * @brief Performs CPU specific SMP initialization in the context of the boot
1532   * processor.
1533   *
1534   * This function is invoked on the boot processor during system
1535   * initialization.  All interrupt stacks are allocated at this point in case
1536   * the CPU port allocates the interrupt stacks.  This function is called
1537   * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
1538   * used.
1539   *
1540   * @return The count of physically or virtually available processors.
1541   * Depending on the configuration the application may use not all processors.
1542   */
1543  uint32_t _CPU_SMP_Initialize( void );
1544
1545  /**
1546   * @brief Starts a processor specified by its index.
1547   *
1548   * This function is invoked on the boot processor during system
1549   * initialization.
1550   *
1551   * This function will be called after _CPU_SMP_Initialize().
1552   *
1553   * @param[in] cpu_index The processor index.
1554   *
1555   * @retval true Successful operation.
1556   * @retval false Unable to start this processor.
1557   */
1558  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1559
1560  /**
1561   * @brief Performs final steps of CPU specific SMP initialization in the
1562   * context of the boot processor.
1563   *
1564   * This function is invoked on the boot processor during system
1565   * initialization.
1566   *
1567   * This function will be called after all processors requested by the
1568   * application have been started.
1569   *
1570   * @param[in] cpu_count The minimum value of the count of processors
1571   * requested by the application configuration and the count of physically or
1572   * virtually available processors.
1573   */
1574  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1575
1576  /**
1577   * @brief Returns the index of the current processor.
1578   *
1579   * An architecture specific method must be used to obtain the index of the
1580   * current processor in the system.  The set of processor indices is the
1581   * range of integers starting with zero up to the processor count minus one.
1582   */
1583  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1584  {
1585    return 123;
1586  }
1587
1588  /**
1589   * @brief Sends an inter-processor interrupt to the specified target
1590   * processor.
1591   *
1592   * This operation is undefined for target processor indices out of range.
1593   *
1594   * @param[in] target_processor_index The target processor index.
1595   */
1596  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1597
1598  /**
1599   * @brief Broadcasts a processor event.
1600   *
1601   * Some architectures provide a low-level synchronization primitive for
1602   * processors in a multi-processor environment.  Processors waiting for this
1603   * event may go into a low-power state and stop generating system bus
1604   * transactions.  This function must ensure that preceding store operations
1605   * can be observed by other processors.
1606   *
1607   * @see _CPU_SMP_Processor_event_receive().
1608   */
1609  static inline void _CPU_SMP_Processor_event_broadcast( void )
1610  {
1611    __asm__ volatile ( "" : : : "memory" );
1612  }
1613
1614  /**
1615   * @brief Receives a processor event.
1616   *
1617   * This function will wait for the processor event and may wait forever if no
1618   * such event arrives.
1619   *
1620   * @see _CPU_SMP_Processor_event_broadcast().
1621   */
1622  static inline void _CPU_SMP_Processor_event_receive( void )
1623  {
1624    __asm__ volatile ( "" : : : "memory" );
1625  }
1626
1627  /**
1628   * @brief Gets the is executing indicator of the thread context.
1629   *
1630   * @param[in] context The context.
1631   */
1632  static inline bool _CPU_Context_Get_is_executing(
1633    const Context_Control *context
1634  )
1635  {
1636    return context->is_executing;
1637  }
1638
1639  /**
1640   * @brief Sets the is executing indicator of the thread context.
1641   *
1642   * @param[in] context The context.
1643   * @param[in] is_executing The new value for the is executing indicator.
1644   */
1645  static inline void _CPU_Context_Set_is_executing(
1646    Context_Control *context,
1647    bool is_executing
1648  )
1649  {
1650    context->is_executing = is_executing;
1651  }
1652#endif
1653
1654#ifdef __cplusplus
1655}
1656#endif
1657
1658#endif
Note: See TracBrowser for help on using the repository browser.