source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 7f70d1b7

4.104.114.84.95
Last change on this file since 7f70d1b7 was 7f70d1b7, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jan 28, 2005 at 3:56:09 PM

New header guard.

  • Property mode set to 100644
File size: 43.7 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 * 
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*  COPYRIGHT (c) 1989-2004.
23 *  On-Line Applications Research Corporation (OAR).
24 *
25 *  The license and distribution terms for this file may be
26 *  found in the file LICENSE in this distribution or at
27 *  http://www.rtems.com/license/LICENSE.
28 *
29 *  $Id$
30 */
31
32#ifndef _RTEMS_SCORE_CPU_H
33#define _RTEMS_SCORE_CPU_H
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
40#ifndef ASM
41#include <rtems/score/types.h>
42#endif
43
44/* conditional compilation parameters */
45
46/**
47 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
48 *
49 *  If TRUE, then they are inlined.
50 *  If FALSE, then a subroutine call is made.
51 *
52 *  This conditional is an example of the classic trade-off of size
53 *  versus speed.  Inlining the call (TRUE) typically increases the
54 *  size of RTEMS while speeding up the enabling of dispatching.
55 *
56 *  @note In general, the @ref _Thread_Dispatch_disable_level will
57 *  only be 0 or 1 unless you are in an interrupt handler and that
58 *  interrupt handler invokes the executive.]  When not inlined
59 *  something calls @ref _Thread_Enable_dispatch which in turns calls
60 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
61 *  one subroutine call is avoided entirely.
62 *
63 *  Port Specific Information:
64 *
65 *  XXX document implementation including references if appropriate
66 */
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/**
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 *
86 *  Port Specific Information:
87 *
88 *  XXX document implementation including references if appropriate
89 */
90#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
91
92/**
93 *  Does RTEMS manage a dedicated interrupt stack in software?
94 *
95 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
96 *  If FALSE, nothing is done.
97 *
98 *  If the CPU supports a dedicated interrupt stack in hardware,
99 *  then it is generally the responsibility of the BSP to allocate it
100 *  and set it up.
101 *
102 *  If the CPU does not support a dedicated interrupt stack, then
103 *  the porter has two options: (1) execute interrupts on the
104 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
105 *  interrupt stack.
106 *
107 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 *
115 *  Port Specific Information:
116 *
117 *  XXX document implementation including references if appropriate
118 */
119#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
120
121/**
122 *  Does this CPU have hardware support for a dedicated interrupt stack?
123 *
124 *  If TRUE, then it must be installed during initialization.
125 *  If FALSE, then no installation is performed.
126 *
127 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
128 *
129 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
130 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
131 *  possible that both are FALSE for a particular CPU.  Although it
132 *  is unclear what that would imply about the interrupt processing
133 *  procedure on that CPU.
134 *
135 *  Port Specific Information:
136 *
137 *  XXX document implementation including references if appropriate
138 */
139#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
140
141/**
142 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
143 *
144 *  If TRUE, then the memory is allocated during initialization.
145 *  If FALSE, then the memory is allocated during initialization.
146 *
147 *  This should be TRUE is @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
148 *  or @ref CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
149 *
150 *  Port Specific Information:
151 *
152 *  XXX document implementation including references if appropriate
153 */
154#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
155
156/**
157 *  Does the RTEMS invoke the user's ISR with the vector number and
158 *  a pointer to the saved interrupt frame (1) or just the vector
159 *  number (0)?
160 *
161 *  Port Specific Information:
162 *
163 *  XXX document implementation including references if appropriate
164 */
165#define CPU_ISR_PASSES_FRAME_POINTER 0
166
167/**
168 *  @def CPU_HARDWARE_FP
169 *
170 *  Does the CPU have hardware floating point?
171 *
172 *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is supported.
173 *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is ignored.
174 *
175 *  If there is a FP coprocessor such as the i387 or mc68881, then
176 *  the answer is TRUE.
177 *
178 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
179 *  It indicates whether or not this CPU model has FP support.  For
180 *  example, it would be possible to have an i386_nofp CPU model
181 *  which set this to false to indicate that you have an i386 without
182 *  an i387 and wish to leave floating point support out of RTEMS.
183 */
184
185/**
186 *  @def CPU_SOFTWARE_FP
187 *
188 *  Does the CPU have no hardware floating point and GCC provides a
189 *  software floating point implementation which must be context
190 *  switched?
191 *
192 *  This feature conditional is used to indicate whether or not there
193 *  is software implemented floating point that must be context
194 *  switched.  The determination of whether or not this applies
195 *  is very tool specific and the state saved/restored is also
196 *  compiler specific.
197 *
198 *  Port Specific Information:
199 *
200 *  XXX document implementation including references if appropriate
201 */
202#if ( NO_CPU_HAS_FPU == 1 )
203#define CPU_HARDWARE_FP     TRUE
204#else
205#define CPU_HARDWARE_FP     FALSE
206#endif
207#define CPU_SOFTWARE_FP     FALSE
208
209/**
210 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
211 *
212 *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is assumed.
213 *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is followed.
214 *
215 *  So far, the only CPUs in which this option has been used are the
216 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
217 *  gcc both implicitly used the floating point registers to perform
218 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
219 *  seen to allocate floating point local variables and touch the FPU
220 *  even when the flow through a subroutine (like vfprintf()) might
221 *  not use floating point formats.
222 *
223 *  If a function which you would not think utilize the FP unit DOES,
224 *  then one can not easily predict which tasks will use the FP hardware.
225 *  In this case, this option should be TRUE.
226 *
227 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
228 *
229 *  Port Specific Information:
230 *
231 *  XXX document implementation including references if appropriate
232 */
233#define CPU_ALL_TASKS_ARE_FP     TRUE
234
235/**
236 *  Should the IDLE task have a floating point context?
237 *
238 *  If TRUE, then the IDLE task is created as a @ref RTEMS_FLOATING_POINT task
239 *  and it has a floating point context which is switched in and out.
240 *  If FALSE, then the IDLE task does not have a floating point context.
241 *
242 *  Setting this to TRUE negatively impacts the time required to preempt
243 *  the IDLE task from an interrupt because the floating point context
244 *  must be saved as part of the preemption.
245 *
246 *  Port Specific Information:
247 *
248 *  XXX document implementation including references if appropriate
249 */
250#define CPU_IDLE_TASK_IS_FP      FALSE
251
252/**
253 *  Should the saving of the floating point registers be deferred
254 *  until a context switch is made to another different floating point
255 *  task?
256 *
257 *  If TRUE, then the floating point context will not be stored until
258 *  necessary.  It will remain in the floating point registers and not
259 *  disturned until another floating point task is switched to.
260 *
261 *  If FALSE, then the floating point context is saved when a floating
262 *  point task is switched out and restored when the next floating point
263 *  task is restored.  The state of the floating point registers between
264 *  those two operations is not specified.
265 *
266 *  If the floating point context does NOT have to be saved as part of
267 *  interrupt dispatching, then it should be safe to set this to TRUE.
268 *
269 *  Setting this flag to TRUE results in using a different algorithm
270 *  for deciding when to save and restore the floating point context.
271 *  The deferred FP switch algorithm minimizes the number of times
272 *  the FP context is saved and restored.  The FP context is not saved
273 *  until a context switch is made to another, different FP task.
274 *  Thus in a system with only one FP task, the FP context will never
275 *  be saved or restored.
276 *
277 *  Port Specific Information:
278 *
279 *  XXX document implementation including references if appropriate
280 */
281#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
282
283/**
284 *  Does this port provide a CPU dependent IDLE task implementation?
285 *
286 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
287 *  must be provided and is the default IDLE thread body instead of
288 *  @ref _CPU_Thread_Idle_body.
289 *
290 *  If FALSE, then use the generic IDLE thread body if the BSP does
291 *  not provide one.
292 *
293 *  This is intended to allow for supporting processors which have
294 *  a low power or idle mode.  When the IDLE thread is executed, then
295 *  the CPU can be powered down.
296 *
297 *  The order of precedence for selecting the IDLE thread body is:
298 *
299 *    -#  BSP provided
300 *    -#  CPU dependent (if provided)
301 *    -#  generic (if no BSP and no CPU dependent)
302 *
303 *  Port Specific Information:
304 *
305 *  XXX document implementation including references if appropriate
306 */
307#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
308
309/**
310 *  Does the stack grow up (toward higher addresses) or down
311 *  (toward lower addresses)?
312 *
313 *  If TRUE, then the grows upward.
314 *  If FALSE, then the grows toward smaller addresses.
315 *
316 *  Port Specific Information:
317 *
318 *  XXX document implementation including references if appropriate
319 */
320#define CPU_STACK_GROWS_UP               TRUE
321
322/**
323 *  The following is the variable attribute used to force alignment
324 *  of critical RTEMS structures.  On some processors it may make
325 *  sense to have these aligned on tighter boundaries than
326 *  the minimum requirements of the compiler in order to have as
327 *  much of the critical data area as possible in a cache line.
328 *
329 *  The placement of this macro in the declaration of the variables
330 *  is based on the syntactically requirements of the GNU C
331 *  "__attribute__" extension.  For example with GNU C, use
332 *  the following to force a structures to a 32 byte boundary.
333 *
334 *      __attribute__ ((aligned (32)))
335 *
336 *  @note Currently only the Priority Bit Map table uses this feature.
337 *        To benefit from using this, the data must be heavily
338 *        used so it will stay in the cache and used frequently enough
339 *        in the executive to justify turning this on.
340 *
341 *  Port Specific Information:
342 *
343 *  XXX document implementation including references if appropriate
344 */
345#define CPU_STRUCTURE_ALIGNMENT
346
347/**
348 *  @defgroup CPUEndian Processor Dependent Endianness Support
349 *
350 *  This group assists in issues related to processor endianness.
351 */
352
353/**
354 *  @ingroup CPUEndian
355 *  Define what is required to specify how the network to host conversion
356 *  routines are handled.
357 *
358 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
359 *  same values.
360 *
361 *  @see CPU_LITTLE_ENDIAN
362 *
363 *  Port Specific Information:
364 *
365 *  XXX document implementation including references if appropriate
366 */
367#define CPU_BIG_ENDIAN                           TRUE
368
369/**
370 *  @ingroup CPUEndian
371 *  Define what is required to specify how the network to host conversion
372 *  routines are handled.
373 *
374 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
375 *  same values.
376 *
377 *  @see CPU_BIG_ENDIAN
378 *
379 *  Port Specific Information:
380 *
381 *  XXX document implementation including references if appropriate
382 */
383#define CPU_LITTLE_ENDIAN                        FALSE
384
385/**
386 *  @ingroup CPUInterrupt
387 *  The following defines the number of bits actually used in the
388 *  interrupt field of the task mode.  How those bits map to the
389 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
390 *
391 *  Port Specific Information:
392 *
393 *  XXX document implementation including references if appropriate
394 */
395#define CPU_MODES_INTERRUPT_MASK   0x00000001
396
397/*
398 *  Processor defined structures required for cpukit/score.
399 *
400 *  Port Specific Information:
401 *
402 *  XXX document implementation including references if appropriate
403 */
404
405/* may need to put some structures here.  */
406
407/**
408 * @defgroup CPUContext Processor Dependent Context Management
409 *
410 *  From the highest level viewpoint, there are 2 types of context to save.
411 *
412 *     -# Interrupt registers to save
413 *     -# Task level registers to save
414 *
415 *  Since RTEMS handles integer and floating point contexts separately, this
416 *  means we have the following 3 context items:
417 *
418 *     -# task level context stuff::  Context_Control
419 *     -# floating point task stuff:: Context_Control_fp
420 *     -# special interrupt level context :: CPU_Interrupt_frame
421 *
422 *  On some processors, it is cost-effective to save only the callee
423 *  preserved registers during a task context switch.  This means
424 *  that the ISR code needs to save those registers which do not
425 *  persist across function calls.  It is not mandatory to make this
426 *  distinctions between the caller/callee saves registers for the
427 *  purpose of minimizing context saved during task switch and on interrupts.
428 *  If the cost of saving extra registers is minimal, simplicity is the
429 *  choice.  Save the same context on interrupt entry as for tasks in
430 *  this case.
431 *
432 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
433 *  care should be used in designing the context area.
434 *
435 *  On some CPUs with hardware floating point support, the Context_Control_fp
436 *  structure will not be used or it simply consist of an array of a
437 *  fixed number of bytes.   This is done when the floating point context
438 *  is dumped by a "FP save context" type instruction and the format
439 *  is not really defined by the CPU.  In this case, there is no need
440 *  to figure out the exact format -- only the size.  Of course, although
441 *  this is enough information for RTEMS, it is probably not enough for
442 *  a debugger such as gdb.  But that is another problem.
443 *
444 *  Port Specific Information:
445 *
446 *  XXX document implementation including references if appropriate
447 */
448
449/**
450 *  @ingroup CPUContext Management
451 *  This defines the minimal set of integer and processor state registers
452 *  that must be saved during a voluntary context switch from one thread
453 *  to another.
454 */
455typedef struct {
456    /** This field is a hint that a port will have a number of integer
457     *  registers that need to be saved at a context switch.
458     */
459    uint32_t   some_integer_register;
460    /** This field is a hint that a port will have a number of system
461     *  registers that need to be saved at a context switch.
462     */
463    uint32_t   some_system_register;
464} Context_Control;
465
466/**
467 *  @ingroup CPUContext Management
468 *  This defines the complete set of floating point registers that must
469 *  be saved during any context switch from one thread to another.
470 */
471typedef struct {
472    double      some_float_register;
473} Context_Control_fp;
474
475/**
476 *  @ingroup CPUContext Management
477 *  This defines the set of integer and processor state registers that must
478 *  be saved during an interrupt.  This set does not include any which are
479 *  in @ref Context_Control.
480 */
481typedef struct {
482    /** This field is a hint that a port will have a number of integer
483     *  registers that need to be saved when an interrupt occurs or
484     *  when a context switch occurs at the end of an ISR.
485     */
486    uint32_t   special_interrupt_register;
487} CPU_Interrupt_frame;
488
489
490/**
491 *  The following table contains the information required to configure
492 *  the XXX processor specific parameters.
493 *
494 *  Port Specific Information:
495 *
496 *  XXX document implementation including references if appropriate
497 */
498
499typedef struct {
500  /** This element points to the BSP's pretasking hook. */
501  void       (*pretasking_hook)( void );
502  /** This element points to the BSP's predriver hook. */
503  void       (*predriver_hook)( void );
504  /** This element points to the BSP's postdriver hook. */
505  void       (*postdriver_hook)( void );
506  /** This element points to the BSP's optional idle task which may override
507   *  the default one provided with RTEMS.
508   */
509  void       (*idle_task)( void );
510  /** If this element is TRUE, then RTEMS will zero the Executive Workspace.
511   *  When this element is FALSE, it is assumed that the BSP or invoking
512   *  environment has ensured that memory was cleared before RTEMS was
513   *  invoked.
514   */
515  boolean      do_zero_of_workspace;
516  /** This field specifies the size of the IDLE task's stack.  If less than or
517   *  equal to the minimum stack size, then the IDLE task will have the minimum
518   *  stack size.
519   */
520  uint32_t     idle_task_stack_size;
521  /** This field specifies the size of the interrupt stack.  If less than or
522   *  equal to the minimum stack size, then the interrupt stack will be of
523   *  minimum stack size.
524   */
525  uint32_t     interrupt_stack_size;
526  /** The MPCI Receive server is assumed to have a stack of at least
527   *  minimum stack size.  This field specifies the amount of extra
528   *  stack this task will be given in bytes.
529   */
530  uint32_t     extra_mpci_receive_server_stack;
531  /** The BSP may want to provide it's own stack allocation routines.
532   *  In this case, the BSP will provide this stack allocation hook.
533   */
534  void *     (*stack_allocate_hook)( uint32_t   );
535  /** The BSP may want to provide it's own stack free routines.
536   *  In this case, the BSP will provide this stack free hook.
537   */
538  void       (*stack_free_hook)( void *);
539  /* end of fields required on all CPUs */
540}   rtems_cpu_table;
541
542/*
543 *  Macros to access required entires in the CPU Table are in
544 *  the file rtems/system.h.
545 *
546 *  Port Specific Information:
547 *
548 *  XXX document implementation including references if appropriate
549 */
550
551/*
552 *  Macros to access NO_CPU specific additions to the CPU Table
553 *
554 *  Port Specific Information:
555 *
556 *  XXX document implementation including references if appropriate
557 */
558
559/* There are no CPU specific additions to the CPU Table for this port. */
560
561/**
562 *  This variable is optional.  It is used on CPUs on which it is difficult
563 *  to generate an "uninitialized" FP context.  It is filled in by
564 *  @ref _CPU_Initialize and copied into the task's FP context area during
565 *  @ref _CPU_Context_Initialize.
566 *
567 *  Port Specific Information:
568 *
569 *  XXX document implementation including references if appropriate
570 */
571SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
572
573/**
574 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
575 *
576 *  On some CPUs, RTEMS supports a software managed interrupt stack.
577 *  This stack is allocated by the Interrupt Manager and the switch
578 *  is performed in @ref _ISR_Handler.  These variables contain pointers
579 *  to the lowest and highest addresses in the chunk of memory allocated
580 *  for the interrupt stack.  Since it is unknown whether the stack
581 *  grows up or down (in general), this give the CPU dependent
582 *  code the option of picking the version it wants to use.
583 *
584 *  @note These two variables are required if the macro
585 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
586 *
587 *  Port Specific Information:
588 *
589 *  XXX document implementation including references if appropriate
590 */
591
592/**
593 *  @ingroup CPUInterrupt
594 *  This variable points to the lowest physical address of the interrupt
595 *  stack.
596 */
597SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
598
599/**
600 *  @ingroup CPUInterrupt
601 *  This variable points to the lowest physical address of the interrupt
602 *  stack.
603 */
604SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
605
606/**
607 *  @ingroup CPUInterrupt
608 *  With some compilation systems, it is difficult if not impossible to
609 *  call a high-level language routine from assembly language.  This
610 *  is especially true of commercial Ada compilers and name mangling
611 *  C++ ones.  This variable can be optionally defined by the CPU porter
612 *  and contains the address of the routine @ref _Thread_Dispatch.  This
613 *  can make it easier to invoke that routine at the end of the interrupt
614 *  sequence (if a dispatch is necessary).
615 *
616 *  Port Specific Information:
617 *
618 *  XXX document implementation including references if appropriate
619 */
620SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
621
622/*
623 *  Nothing prevents the porter from declaring more CPU specific variables.
624 *
625 *  Port Specific Information:
626 *
627 *  XXX document implementation including references if appropriate
628 */
629
630/* XXX: if needed, put more variables here */
631
632/**
633 *  @ingroup CPUContext
634 *  The size of the floating point context area.  On some CPUs this
635 *  will not be a "sizeof" because the format of the floating point
636 *  area is not defined -- only the size is.  This is usually on
637 *  CPUs with a "floating point save context" instruction.
638 *
639 *  Port Specific Information:
640 *
641 *  XXX document implementation including references if appropriate
642 */
643#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
644
645/**
646 *  Amount of extra stack (above minimum stack size) required by
647 *  MPCI receive server thread.  Remember that in a multiprocessor
648 *  system this thread must exist and be able to process all directives.
649 *
650 *  Port Specific Information:
651 *
652 *  XXX document implementation including references if appropriate
653 */
654#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
655
656/**
657 *  @ingroup CPUInterrupt
658 *  This defines the number of entries in the @ref _ISR_Vector_table managed
659 *  by RTEMS.
660 *
661 *  Port Specific Information:
662 *
663 *  XXX document implementation including references if appropriate
664 */
665#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
666
667/**
668 *  @ingroup CPUInterrupt
669 *  This defines the highest interrupt vector number for this port.
670 */
671#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
672
673/**
674 *  @ingroup CPUInterrupt
675 *  This is defined if the port has a special way to report the ISR nesting
676 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
677 */
678#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
679
680/**
681 *  @ingroup CPUContext
682 *  Should be large enough to run all RTEMS tests.  This ensures
683 *  that a "reasonable" small application should not have any problems.
684 *
685 *  Port Specific Information:
686 *
687 *  XXX document implementation including references if appropriate
688 */
689#define CPU_STACK_MINIMUM_SIZE          (1024*4)
690
691/**
692 *  CPU's worst alignment requirement for data types on a byte boundary.  This
693 *  alignment does not take into account the requirements for the stack.
694 *
695 *  Port Specific Information:
696 *
697 *  XXX document implementation including references if appropriate
698 */
699#define CPU_ALIGNMENT              8
700
701/**
702 *  This number corresponds to the byte alignment requirement for the
703 *  heap handler.  This alignment requirement may be stricter than that
704 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
705 *  common for the heap to follow the same alignment requirement as
706 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
707 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
708 *
709 *  @note  This does not have to be a power of 2 although it should be
710 *         a multiple of 2 greater than or equal to 2.  The requirement
711 *         to be a multiple of 2 is because the heap uses the least
712 *         significant field of the front and back flags to indicate
713 *         that a block is in use or free.  So you do not want any odd
714 *         length blocks really putting length data in that bit.
715 *
716 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
717 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
718 *         elements allocated from the heap meet all restrictions.
719 *
720 *  Port Specific Information:
721 *
722 *  XXX document implementation including references if appropriate
723 */
724#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
725
726/**
727 *  This number corresponds to the byte alignment requirement for memory
728 *  buffers allocated by the partition manager.  This alignment requirement
729 *  may be stricter than that for the data types alignment specified by
730 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
731 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
732 *  strict enough for the partition, then this should be set to
733 *  @ref CPU_ALIGNMENT.
734 *
735 *  @note  This does not have to be a power of 2.  It does have to
736 *         be greater or equal to than @ref CPU_ALIGNMENT.
737 *
738 *  Port Specific Information:
739 *
740 *  XXX document implementation including references if appropriate
741 */
742#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
743
744/**
745 *  This number corresponds to the byte alignment requirement for the
746 *  stack.  This alignment requirement may be stricter than that for the
747 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
748 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
749 *  set to 0.
750 *
751 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
752 *
753 *  Port Specific Information:
754 *
755 *  XXX document implementation including references if appropriate
756 */
757#define CPU_STACK_ALIGNMENT        0
758
759/*
760 *  ISR handler macros
761 */
762
763/**
764 *  @ingroup CPUInterrupt
765 *  Support routine to initialize the RTEMS vector table after it is allocated.
766 *
767 *  Port Specific Information:
768 *
769 *  XXX document implementation including references if appropriate
770 */
771#define _CPU_Initialize_vectors()
772
773/**
774 *  @ingroup CPUInterrupt
775 *  Disable all interrupts for an RTEMS critical section.  The previous
776 *  level is returned in @a _isr_cookie.
777 *
778 *  @param _isr_cookie (out) will contain the previous level cookie
779 *
780 *  Port Specific Information:
781 *
782 *  XXX document implementation including references if appropriate
783 */
784#define _CPU_ISR_Disable( _isr_cookie ) \
785  { \
786    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
787  }
788
789/**
790 *  @ingroup CPUInterrupt
791 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
792 *  This indicates the end of an RTEMS critical section.  The parameter
793 *  @a _isr_cookie is not modified.
794 *
795 *  @param _isr_cookie (in) contain the previous level cookie
796 *
797 *  Port Specific Information:
798 *
799 *  XXX document implementation including references if appropriate
800 */
801#define _CPU_ISR_Enable( _isr_cookie )  \
802  { \
803  }
804
805/**
806 *  @ingroup CPUInterrupt
807 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
808 *  disabling them again.  This is used to divide long RTEMS critical
809 *  sections into two or more parts.  The parameter @a _isr_cookie is not
810 *  modified.
811 *
812 *  @param _isr_cookie (in) contain the previous level cookie
813 *
814 *  Port Specific Information:
815 *
816 *  XXX document implementation including references if appropriate
817 */
818#define _CPU_ISR_Flash( _isr_cookie ) \
819  { \
820  }
821
822/**
823 *  @ingroup CPUInterrupt
824 *
825 *  This routine and @ref _CPU_ISR_Get_level
826 *  Map the interrupt level in task mode onto the hardware that the CPU
827 *  actually provides.  Currently, interrupt levels which do not
828 *  map onto the CPU in a generic fashion are undefined.  Someday,
829 *  it would be nice if these were "mapped" by the application
830 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
831 *  8 - 255 would be available for bsp/application specific meaning.
832 *  This could be used to manage a programmable interrupt controller
833 *  via the rtems_task_mode directive.
834 *
835 *  Port Specific Information:
836 *
837 *  XXX document implementation including references if appropriate
838 */
839#define _CPU_ISR_Set_level( new_level ) \
840  { \
841  }
842
843/**
844 *  @ingroup CPUInterrupt
845 *  Return the current interrupt disable level for this task in
846 *  the format used by the interrupt level portion of the task mode.
847 *
848 *  @note This routine usually must be implemented as a subroutine.
849 *
850 *  Port Specific Information:
851 *
852 *  XXX document implementation including references if appropriate
853 */
854uint32_t   _CPU_ISR_Get_level( void );
855
856/* end of ISR handler macros */
857
858/* Context handler macros */
859
860/**
861 *  @ingroup CPUContext
862 *  Initialize the context to a state suitable for starting a
863 *  task after a context restore operation.  Generally, this
864 *  involves:
865 *
866 *     - setting a starting address
867 *     - preparing the stack
868 *     - preparing the stack and frame pointers
869 *     - setting the proper interrupt level in the context
870 *     - initializing the floating point context
871 *
872 *  This routine generally does not set any unnecessary register
873 *  in the context.  The state of the "general data" registers is
874 *  undefined at task start time.
875 *
876 *  @param _the_context (in) is the context structure to be initialized
877 *  @param _stack_base (in) is the lowest physical address of this task's stack
878 *  @param _size (in) is the size of this task's stack
879 *  @param _isr (in) is the interrupt disable level
880 *  @param _entry_point (in) is the thread's entry point.  This is
881 *         always @a _Thread_Handler
882 *  @param _is_fp (in) is TRUE if the thread is to be a floating
883 *        point thread.  This is typically only used on CPUs where the
884 *        FPU may be easily disabled by software such as on the SPARC
885 *        where the PSR contains an enable FPU bit.
886 *
887 *  Port Specific Information:
888 *
889 *  XXX document implementation including references if appropriate
890 */
891#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
892                                 _isr, _entry_point, _is_fp ) \
893  { \
894  }
895
896/*
897 *  This routine is responsible for somehow restarting the currently
898 *  executing task.  If you are lucky, then all that is necessary
899 *  is restoring the context.  Otherwise, there will need to be
900 *  a special assembly routine which does something special in this
901 *  case.  @ref _CPU_Context_Restore should work most of the time.  It will
902 *  not work if restarting self conflicts with the stack frame
903 *  assumptions of restoring a context.
904 *
905 *  Port Specific Information:
906 *
907 *  XXX document implementation including references if appropriate
908 */
909#define _CPU_Context_Restart_self( _the_context ) \
910   _CPU_Context_restore( (_the_context) );
911
912/**
913 *  @ingroup CPUContext
914 *  The purpose of this macro is to allow the initial pointer into
915 *  a floating point context area (used to save the floating point
916 *  context) to be at an arbitrary place in the floating point
917 *  context area.
918 *
919 *  This is necessary because some FP units are designed to have
920 *  their context saved as a stack which grows into lower addresses.
921 *  Other FP units can be saved by simply moving registers into offsets
922 *  from the base of the context area.  Finally some FP units provide
923 *  a "dump context" instruction which could fill in from high to low
924 *  or low to high based on the whim of the CPU designers.
925 *
926 *  @param _base (in) is the lowest physical address of the floating point
927 *         context area
928 *  @param _offset (in) is the offset into the floating point area
929 *
930 *  Port Specific Information:
931 *
932 *  XXX document implementation including references if appropriate
933 */
934#define _CPU_Context_Fp_start( _base, _offset ) \
935   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
936
937/**
938 *  This routine initializes the FP context area passed to it to.
939 *  There are a few standard ways in which to initialize the
940 *  floating point context.  The code included for this macro assumes
941 *  that this is a CPU in which a "initial" FP context was saved into
942 *  @a _CPU_Null_fp_context and it simply copies it to the destination
943 *  context passed to it.
944 *
945 *  Other floating point context save/restore models include:
946 *    -# not doing anything, and
947 *    -# putting a "null FP status word" in the correct place in the FP context.
948 *
949 *  @param _destination (in) is the floating point context area
950 *
951 *  Port Specific Information:
952 *
953 *  XXX document implementation including references if appropriate
954 */
955#define _CPU_Context_Initialize_fp( _destination ) \
956  { \
957   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
958  }
959
960/* end of Context handler macros */
961
962/* Fatal Error manager macros */
963
964/**
965 *  This routine copies _error into a known place -- typically a stack
966 *  location or a register, optionally disables interrupts, and
967 *  halts/stops the CPU.
968 *
969 *  Port Specific Information:
970 *
971 *  XXX document implementation including references if appropriate
972 */
973#define _CPU_Fatal_halt( _error ) \
974  { \
975  }
976
977/* end of Fatal Error manager macros */
978
979/* Bitfield handler macros */
980
981/**
982 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
983 *
984 *  This set of routines are used to implement fast searches for
985 *  the most important ready task.
986 */
987
988/**
989 *  @ingroup CPUBitfield
990 *  This definition is set to TRUE if the port uses the generic bitfield
991 *  manipulation implementation.
992 */
993#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
994
995/**
996 *  @ingroup CPUBitfield
997 *  This definition is set to TRUE if the port uses the data tables provided
998 *  by the generic bitfield manipulation implementation.
999 *  This can occur when actually using the generic bitfield manipulation
1000 *  implementation or when implementing the same algorithm in assembly
1001 *  language for improved performance.  It is unlikely that a port will use
1002 *  the data if it has a bitfield scan instruction.
1003 */
1004#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1005
1006/**
1007 *  @ingroup CPUBitfield
1008 *  This routine sets @a _output to the bit number of the first bit
1009 *  set in @a _value.  @a _value is of CPU dependent type
1010 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
1011 *  wide although only the 16 least significant bits will be used.
1012 *
1013 *  There are a number of variables in using a "find first bit" type
1014 *  instruction.
1015 *
1016 *    -# What happens when run on a value of zero?
1017 *    -# Bits may be numbered from MSB to LSB or vice-versa.
1018 *    -# The numbering may be zero or one based.
1019 *    -# The "find first bit" instruction may search from MSB or LSB.
1020 *
1021 *  RTEMS guarantees that (1) will never happen so it is not a concern.
1022 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1023 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
1024 *  which must logically operate together.  Bits in the _value are
1025 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
1026 *  The basic major and minor values calculated by @ref _Priority_Major
1027 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1028 *  to properly range between the values returned by the "find first bit"
1029 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
1030 *  calculate the major and directly index into the minor table.
1031 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
1032 *  is the first bit found.
1033 *
1034 *  This entire "find first bit" and mapping process depends heavily
1035 *  on the manner in which a priority is broken into a major and minor
1036 *  components with the major being the 4 MSB of a priority and minor
1037 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1038 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1039 *  to the lowest priority.
1040 *
1041 *  If your CPU does not have a "find first bit" instruction, then
1042 *  there are ways to make do without it.  Here are a handful of ways
1043 *  to implement this in software:
1044 *
1045@verbatim
1046      - a series of 16 bit test instructions
1047      - a "binary search using if's"
1048      - _number = 0
1049        if _value > 0x00ff
1050          _value >>=8
1051          _number = 8;
1052 
1053        if _value > 0x0000f
1054          _value >=8
1055          _number += 4
1056 
1057        _number += bit_set_table[ _value ]
1058@endverbatim
1059 
1060 *    where bit_set_table[ 16 ] has values which indicate the first
1061 *      bit set
1062 *
1063 *  @param _value (in) is the value to be scanned
1064 *  @param _output (in) is the first bit set
1065 *
1066 *  Port Specific Information:
1067 *
1068 *  XXX document implementation including references if appropriate
1069 */
1070
1071#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1072#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1073  { \
1074    (_output) = 0;   /* do something to prevent warnings */ \
1075  }
1076#endif
1077
1078/* end of Bitfield handler macros */
1079
1080/**
1081 *  This routine builds the mask which corresponds to the bit fields
1082 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1083 *  for that routine.
1084 *
1085 *  Port Specific Information:
1086 *
1087 *  XXX document implementation including references if appropriate
1088 */
1089#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1090
1091#define _CPU_Priority_Mask( _bit_number ) \
1092  ( 1 << (_bit_number) )
1093
1094#endif
1095
1096/**
1097 *  @ingroup CPUBitfield
1098 *  This routine translates the bit numbers returned by
1099 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1100 *  a major or minor component of a priority.  See the discussion
1101 *  for that routine.
1102 *
1103 *  @param _priority (in) is the major or minor number to translate
1104 *
1105 *  Port Specific Information:
1106 *
1107 *  XXX document implementation including references if appropriate
1108 */
1109#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1110
1111#define _CPU_Priority_bits_index( _priority ) \
1112  (_priority)
1113
1114#endif
1115
1116/* end of Priority handler macros */
1117
1118/* functions */
1119
1120/**
1121 *  This routine performs CPU dependent initialization.
1122 *
1123 *  @param cpu_table (in) is the CPU Dependent Configuration Table
1124 *  @param thread_dispatch (in) is the address of @ref _Thread_Dispatch
1125 *
1126 *  Port Specific Information:
1127 *
1128 *  XXX document implementation including references if appropriate
1129 */
1130void _CPU_Initialize(
1131  rtems_cpu_table  *cpu_table,
1132  void      (*thread_dispatch)
1133);
1134
1135/**
1136 *  @ingroup CPUInterrupt
1137 *  This routine installs a "raw" interrupt handler directly into the
1138 *  processor's vector table.
1139 *
1140 *  @param vector (in) is the vector number
1141 *  @param new_handler (in) is the raw ISR handler to install
1142 *  @param old_handler (in) is the previously installed ISR Handler
1143 *
1144 *  Port Specific Information:
1145 *
1146 *  XXX document implementation including references if appropriate
1147 */
1148void _CPU_ISR_install_raw_handler(
1149  uint32_t    vector,
1150  proc_ptr    new_handler,
1151  proc_ptr   *old_handler
1152);
1153
1154/**
1155 *  @ingroup CPUInterrupt
1156 *  This routine installs an interrupt vector.
1157 *
1158 *  @param vector (in) is the vector number
1159 *  @param new_handler (in) is the RTEMS ISR handler to install
1160 *  @param old_handler (in) is the previously installed ISR Handler
1161 *
1162 *  Port Specific Information:
1163 *
1164 *  XXX document implementation including references if appropriate
1165 */
1166void _CPU_ISR_install_vector(
1167  uint32_t    vector,
1168  proc_ptr    new_handler,
1169  proc_ptr   *old_handler
1170);
1171
1172/**
1173 *  @ingroup CPUInterrupt
1174 *  This routine installs the hardware interrupt stack pointer.
1175 *
1176 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1177 *         is TRUE.
1178 *
1179 *  Port Specific Information:
1180 *
1181 *  XXX document implementation including references if appropriate
1182 */
1183void _CPU_Install_interrupt_stack( void );
1184
1185/**
1186 *  This routine is the CPU dependent IDLE thread body.
1187 *
1188 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1189 *         is TRUE.
1190 *
1191 *  Port Specific Information:
1192 *
1193 *  XXX document implementation including references if appropriate
1194 */
1195void _CPU_Thread_Idle_body( void );
1196
1197/**
1198 *  @ingroup CPUContext
1199 *  This routine switches from the run context to the heir context.
1200 *
1201 *  @param run (in) points to the context of the currently executing task
1202 *  @param heir (in) points to the context of the heir task
1203 *
1204 *  Port Specific Information:
1205 *
1206 *  XXX document implementation including references if appropriate
1207 */
1208void _CPU_Context_switch(
1209  Context_Control  *run,
1210  Context_Control  *heir
1211);
1212
1213/**
1214 *  @ingroup CPUContext
1215 *  This routine is generally used only to restart self in an
1216 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1217 *
1218 *  @param new_context (in) points to the context to be restored.
1219 *
1220 *  @note May be unnecessary to reload some registers.
1221 *
1222 *  Port Specific Information:
1223 *
1224 *  XXX document implementation including references if appropriate
1225 */
1226void _CPU_Context_restore(
1227  Context_Control *new_context
1228);
1229
1230/**
1231 *  @ingroup CPUContext
1232 *  This routine saves the floating point context passed to it.
1233 *
1234 *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
1235 *  point context area
1236 *
1237 *  @return on output @a *fp_context_ptr will contain the address that
1238 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1239 *
1240 *  Port Specific Information:
1241 *
1242 *  XXX document implementation including references if appropriate
1243 */
1244void _CPU_Context_save_fp(
1245  void **fp_context_ptr
1246);
1247
1248/**
1249 *  @ingroup CPUContext
1250 *  This routine restores the floating point context passed to it.
1251 *
1252 *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
1253 *  point context area to restore
1254 *
1255 *  @return on output @a *fp_context_ptr will contain the address that
1256 *  should be used with @ref _CPU_Context_save_fp to save this context.
1257 *
1258 *  Port Specific Information:
1259 *
1260 *  XXX document implementation including references if appropriate
1261 */
1262void _CPU_Context_restore_fp(
1263  void **fp_context_ptr
1264);
1265
1266/**
1267 *  @ingroup CPUEndian
1268 *  The following routine swaps the endian format of an unsigned int.
1269 *  It must be static because it is referenced indirectly.
1270 *
1271 *  This version will work on any processor, but if there is a better
1272 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1273 *
1274 *     swap least significant two bytes with 16-bit rotate
1275 *     swap upper and lower 16-bits
1276 *     swap most significant two bytes with 16-bit rotate
1277 *
1278 *  Some CPUs have special instructions which swap a 32-bit quantity in
1279 *  a single instruction (e.g. i486).  It is probably best to avoid
1280 *  an "endian swapping control bit" in the CPU.  One good reason is
1281 *  that interrupts would probably have to be disabled to insure that
1282 *  an interrupt does not try to access the same "chunk" with the wrong
1283 *  endian.  Another good reason is that on some CPUs, the endian bit
1284 *  endianness for ALL fetches -- both code and data -- so the code
1285 *  will be fetched incorrectly.
1286 *
1287 *  @param value (in) is the value to be swapped
1288 *  @return the value after being endian swapped
1289 *
1290 *  Port Specific Information:
1291 *
1292 *  XXX document implementation including references if appropriate
1293 */
1294static inline uint32_t CPU_swap_u32(
1295  uint32_t value
1296)
1297{
1298  uint32_t   byte1, byte2, byte3, byte4, swapped;
1299 
1300  byte4 = (value >> 24) & 0xff;
1301  byte3 = (value >> 16) & 0xff;
1302  byte2 = (value >> 8)  & 0xff;
1303  byte1 =  value        & 0xff;
1304 
1305  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1306  return( swapped );
1307}
1308
1309/**
1310 *  @ingroup CPUEndian
1311 *  This routine swaps a 16 bir quantity.
1312 *
1313 *  @param value (in) is the value to be swapped
1314 *  @return the value after being endian swapped
1315 */
1316#define CPU_swap_u16( value ) \
1317  (((value&0xff) << 8) | ((value >> 8)&0xff))
1318
1319#ifdef __cplusplus
1320}
1321#endif
1322
1323#endif
Note: See TracBrowser for help on using the repository browser.