source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 5c5d438

4.104.114.95
Last change on this file since 5c5d438 was 5c5d438, checked in by Joel Sherrill <joel.sherrill@…>, on Dec 11, 2007 at 11:42:15 PM

2007-12-11 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Style.
  • Property mode set to 100644
File size: 41.2 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 * 
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*  COPYRIGHT (c) 1989-2006.
23 *  On-Line Applications Research Corporation (OAR).
24 *
25 *  The license and distribution terms for this file may be
26 *  found in the file LICENSE in this distribution or at
27 *  http://www.rtems.com/license/LICENSE.
28 *
29 *  $Id$
30 */
31
32#ifndef _RTEMS_SCORE_CPU_H
33#define _RTEMS_SCORE_CPU_H
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
40#ifndef ASM
41#include <rtems/score/types.h>
42#endif
43
44/* conditional compilation parameters */
45
46/**
47 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
48 *
49 *  If TRUE, then they are inlined.
50 *  If FALSE, then a subroutine call is made.
51 *
52 *  This conditional is an example of the classic trade-off of size
53 *  versus speed.  Inlining the call (TRUE) typically increases the
54 *  size of RTEMS while speeding up the enabling of dispatching.
55 *
56 *  @note In general, the @ref _Thread_Dispatch_disable_level will
57 *  only be 0 or 1 unless you are in an interrupt handler and that
58 *  interrupt handler invokes the executive.]  When not inlined
59 *  something calls @ref _Thread_Enable_dispatch which in turns calls
60 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
61 *  one subroutine call is avoided entirely.
62 *
63 *  Port Specific Information:
64 *
65 *  XXX document implementation including references if appropriate
66 */
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/**
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 *
86 *  Port Specific Information:
87 *
88 *  XXX document implementation including references if appropriate
89 */
90#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
91
92/**
93 *  Does RTEMS manage a dedicated interrupt stack in software?
94 *
95 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
96 *  If FALSE, nothing is done.
97 *
98 *  If the CPU supports a dedicated interrupt stack in hardware,
99 *  then it is generally the responsibility of the BSP to allocate it
100 *  and set it up.
101 *
102 *  If the CPU does not support a dedicated interrupt stack, then
103 *  the porter has two options: (1) execute interrupts on the
104 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
105 *  interrupt stack.
106 *
107 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 *
115 *  Port Specific Information:
116 *
117 *  XXX document implementation including references if appropriate
118 */
119#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
120
121/**
122 *  Does this CPU have hardware support for a dedicated interrupt stack?
123 *
124 *  If TRUE, then it must be installed during initialization.
125 *  If FALSE, then no installation is performed.
126 *
127 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
128 *
129 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
130 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
131 *  possible that both are FALSE for a particular CPU.  Although it
132 *  is unclear what that would imply about the interrupt processing
133 *  procedure on that CPU.
134 *
135 *  Port Specific Information:
136 *
137 *  XXX document implementation including references if appropriate
138 */
139#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
140
141/**
142 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
143 *
144 *  If TRUE, then the memory is allocated during initialization.
145 *  If FALSE, then the memory is allocated during initialization.
146 *
147 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
148 *
149 *  Port Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
154
155/**
156 *  Does the RTEMS invoke the user's ISR with the vector number and
157 *  a pointer to the saved interrupt frame (1) or just the vector
158 *  number (0)?
159 *
160 *  Port Specific Information:
161 *
162 *  XXX document implementation including references if appropriate
163 */
164#define CPU_ISR_PASSES_FRAME_POINTER 0
165
166/**
167 *  @def CPU_HARDWARE_FP
168 *
169 *  Does the CPU have hardware floating point?
170 *
171 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
172 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
173 *
174 *  If there is a FP coprocessor such as the i387 or mc68881, then
175 *  the answer is TRUE.
176 *
177 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
178 *  It indicates whether or not this CPU model has FP support.  For
179 *  example, it would be possible to have an i386_nofp CPU model
180 *  which set this to false to indicate that you have an i386 without
181 *  an i387 and wish to leave floating point support out of RTEMS.
182 */
183
184/**
185 *  @def CPU_SOFTWARE_FP
186 *
187 *  Does the CPU have no hardware floating point and GCC provides a
188 *  software floating point implementation which must be context
189 *  switched?
190 *
191 *  This feature conditional is used to indicate whether or not there
192 *  is software implemented floating point that must be context
193 *  switched.  The determination of whether or not this applies
194 *  is very tool specific and the state saved/restored is also
195 *  compiler specific.
196 *
197 *  Port Specific Information:
198 *
199 *  XXX document implementation including references if appropriate
200 */
201#if ( NO_CPU_HAS_FPU == 1 )
202#define CPU_HARDWARE_FP     TRUE
203#else
204#define CPU_HARDWARE_FP     FALSE
205#endif
206#define CPU_SOFTWARE_FP     FALSE
207
208/**
209 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
210 *
211 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
212 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
213 *
214 *  So far, the only CPUs in which this option has been used are the
215 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
216 *  gcc both implicitly used the floating point registers to perform
217 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
218 *  seen to allocate floating point local variables and touch the FPU
219 *  even when the flow through a subroutine (like vfprintf()) might
220 *  not use floating point formats.
221 *
222 *  If a function which you would not think utilize the FP unit DOES,
223 *  then one can not easily predict which tasks will use the FP hardware.
224 *  In this case, this option should be TRUE.
225 *
226 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
227 *
228 *  Port Specific Information:
229 *
230 *  XXX document implementation including references if appropriate
231 */
232#define CPU_ALL_TASKS_ARE_FP     TRUE
233
234/**
235 *  Should the IDLE task have a floating point context?
236 *
237 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
238 *  and it has a floating point context which is switched in and out.
239 *  If FALSE, then the IDLE task does not have a floating point context.
240 *
241 *  Setting this to TRUE negatively impacts the time required to preempt
242 *  the IDLE task from an interrupt because the floating point context
243 *  must be saved as part of the preemption.
244 *
245 *  Port Specific Information:
246 *
247 *  XXX document implementation including references if appropriate
248 */
249#define CPU_IDLE_TASK_IS_FP      FALSE
250
251/**
252 *  Should the saving of the floating point registers be deferred
253 *  until a context switch is made to another different floating point
254 *  task?
255 *
256 *  If TRUE, then the floating point context will not be stored until
257 *  necessary.  It will remain in the floating point registers and not
258 *  disturned until another floating point task is switched to.
259 *
260 *  If FALSE, then the floating point context is saved when a floating
261 *  point task is switched out and restored when the next floating point
262 *  task is restored.  The state of the floating point registers between
263 *  those two operations is not specified.
264 *
265 *  If the floating point context does NOT have to be saved as part of
266 *  interrupt dispatching, then it should be safe to set this to TRUE.
267 *
268 *  Setting this flag to TRUE results in using a different algorithm
269 *  for deciding when to save and restore the floating point context.
270 *  The deferred FP switch algorithm minimizes the number of times
271 *  the FP context is saved and restored.  The FP context is not saved
272 *  until a context switch is made to another, different FP task.
273 *  Thus in a system with only one FP task, the FP context will never
274 *  be saved or restored.
275 *
276 *  Port Specific Information:
277 *
278 *  XXX document implementation including references if appropriate
279 */
280#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
281
282/**
283 *  Does this port provide a CPU dependent IDLE task implementation?
284 *
285 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
286 *  must be provided and is the default IDLE thread body instead of
287 *  @ref _CPU_Thread_Idle_body.
288 *
289 *  If FALSE, then use the generic IDLE thread body if the BSP does
290 *  not provide one.
291 *
292 *  This is intended to allow for supporting processors which have
293 *  a low power or idle mode.  When the IDLE thread is executed, then
294 *  the CPU can be powered down.
295 *
296 *  The order of precedence for selecting the IDLE thread body is:
297 *
298 *    -#  BSP provided
299 *    -#  CPU dependent (if provided)
300 *    -#  generic (if no BSP and no CPU dependent)
301 *
302 *  Port Specific Information:
303 *
304 *  XXX document implementation including references if appropriate
305 */
306#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
307
308/**
309 *  Does the stack grow up (toward higher addresses) or down
310 *  (toward lower addresses)?
311 *
312 *  If TRUE, then the grows upward.
313 *  If FALSE, then the grows toward smaller addresses.
314 *
315 *  Port Specific Information:
316 *
317 *  XXX document implementation including references if appropriate
318 */
319#define CPU_STACK_GROWS_UP               TRUE
320
321/**
322 *  The following is the variable attribute used to force alignment
323 *  of critical RTEMS structures.  On some processors it may make
324 *  sense to have these aligned on tighter boundaries than
325 *  the minimum requirements of the compiler in order to have as
326 *  much of the critical data area as possible in a cache line.
327 *
328 *  The placement of this macro in the declaration of the variables
329 *  is based on the syntactically requirements of the GNU C
330 *  "__attribute__" extension.  For example with GNU C, use
331 *  the following to force a structures to a 32 byte boundary.
332 *
333 *      __attribute__ ((aligned (32)))
334 *
335 *  @note Currently only the Priority Bit Map table uses this feature.
336 *        To benefit from using this, the data must be heavily
337 *        used so it will stay in the cache and used frequently enough
338 *        in the executive to justify turning this on.
339 *
340 *  Port Specific Information:
341 *
342 *  XXX document implementation including references if appropriate
343 */
344#define CPU_STRUCTURE_ALIGNMENT
345
346/**
347 *  @defgroup CPUEndian Processor Dependent Endianness Support
348 *
349 *  This group assists in issues related to processor endianness.
350 */
351
352/**
353 *  @ingroup CPUEndian
354 *  Define what is required to specify how the network to host conversion
355 *  routines are handled.
356 *
357 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
358 *  same values.
359 *
360 *  @see CPU_LITTLE_ENDIAN
361 *
362 *  Port Specific Information:
363 *
364 *  XXX document implementation including references if appropriate
365 */
366#define CPU_BIG_ENDIAN                           TRUE
367
368/**
369 *  @ingroup CPUEndian
370 *  Define what is required to specify how the network to host conversion
371 *  routines are handled.
372 *
373 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
374 *  same values.
375 *
376 *  @see CPU_BIG_ENDIAN
377 *
378 *  Port Specific Information:
379 *
380 *  XXX document implementation including references if appropriate
381 */
382#define CPU_LITTLE_ENDIAN                        FALSE
383
384/**
385 *  @ingroup CPUInterrupt
386 *  The following defines the number of bits actually used in the
387 *  interrupt field of the task mode.  How those bits map to the
388 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
389 *
390 *  Port Specific Information:
391 *
392 *  XXX document implementation including references if appropriate
393 */
394#define CPU_MODES_INTERRUPT_MASK   0x00000001
395
396/*
397 *  Processor defined structures required for cpukit/score.
398 *
399 *  Port Specific Information:
400 *
401 *  XXX document implementation including references if appropriate
402 */
403
404/* may need to put some structures here.  */
405
406/**
407 * @defgroup CPUContext Processor Dependent Context Management
408 *
409 *  From the highest level viewpoint, there are 2 types of context to save.
410 *
411 *     -# Interrupt registers to save
412 *     -# Task level registers to save
413 *
414 *  Since RTEMS handles integer and floating point contexts separately, this
415 *  means we have the following 3 context items:
416 *
417 *     -# task level context stuff::  Context_Control
418 *     -# floating point task stuff:: Context_Control_fp
419 *     -# special interrupt level context :: CPU_Interrupt_frame
420 *
421 *  On some processors, it is cost-effective to save only the callee
422 *  preserved registers during a task context switch.  This means
423 *  that the ISR code needs to save those registers which do not
424 *  persist across function calls.  It is not mandatory to make this
425 *  distinctions between the caller/callee saves registers for the
426 *  purpose of minimizing context saved during task switch and on interrupts.
427 *  If the cost of saving extra registers is minimal, simplicity is the
428 *  choice.  Save the same context on interrupt entry as for tasks in
429 *  this case.
430 *
431 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
432 *  care should be used in designing the context area.
433 *
434 *  On some CPUs with hardware floating point support, the Context_Control_fp
435 *  structure will not be used or it simply consist of an array of a
436 *  fixed number of bytes.   This is done when the floating point context
437 *  is dumped by a "FP save context" type instruction and the format
438 *  is not really defined by the CPU.  In this case, there is no need
439 *  to figure out the exact format -- only the size.  Of course, although
440 *  this is enough information for RTEMS, it is probably not enough for
441 *  a debugger such as gdb.  But that is another problem.
442 *
443 *  Port Specific Information:
444 *
445 *  XXX document implementation including references if appropriate
446 */
447
448/**
449 *  @ingroup CPUContext Management
450 *  This defines the minimal set of integer and processor state registers
451 *  that must be saved during a voluntary context switch from one thread
452 *  to another.
453 */
454typedef struct {
455    /** This field is a hint that a port will have a number of integer
456     *  registers that need to be saved at a context switch.
457     */
458    uint32_t   some_integer_register;
459    /** This field is a hint that a port will have a number of system
460     *  registers that need to be saved at a context switch.
461     */
462    uint32_t   some_system_register;
463} Context_Control;
464
465/**
466 *  @ingroup CPUContext Management
467 *  This defines the complete set of floating point registers that must
468 *  be saved during any context switch from one thread to another.
469 */
470typedef struct {
471    /** FPU registers are listed here */
472    double      some_float_register;
473} Context_Control_fp;
474
475/**
476 *  @ingroup CPUContext Management
477 *  This defines the set of integer and processor state registers that must
478 *  be saved during an interrupt.  This set does not include any which are
479 *  in @ref Context_Control.
480 */
481typedef struct {
482    /** This field is a hint that a port will have a number of integer
483     *  registers that need to be saved when an interrupt occurs or
484     *  when a context switch occurs at the end of an ISR.
485     */
486    uint32_t   special_interrupt_register;
487} CPU_Interrupt_frame;
488
489/**
490 *  This variable is optional.  It is used on CPUs on which it is difficult
491 *  to generate an "uninitialized" FP context.  It is filled in by
492 *  @ref _CPU_Initialize and copied into the task's FP context area during
493 *  @ref _CPU_Context_Initialize.
494 *
495 *  Port Specific Information:
496 *
497 *  XXX document implementation including references if appropriate
498 */
499SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
500
501/**
502 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
503 *
504 *  On some CPUs, RTEMS supports a software managed interrupt stack.
505 *  This stack is allocated by the Interrupt Manager and the switch
506 *  is performed in @ref _ISR_Handler.  These variables contain pointers
507 *  to the lowest and highest addresses in the chunk of memory allocated
508 *  for the interrupt stack.  Since it is unknown whether the stack
509 *  grows up or down (in general), this give the CPU dependent
510 *  code the option of picking the version it wants to use.
511 *
512 *  @note These two variables are required if the macro
513 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
514 *
515 *  Port Specific Information:
516 *
517 *  XXX document implementation including references if appropriate
518 */
519
520/**
521 *  @ingroup CPUInterrupt
522 *  This variable points to the lowest physical address of the interrupt
523 *  stack.
524 */
525SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
526
527/**
528 *  @ingroup CPUInterrupt
529 *  This variable points to the lowest physical address of the interrupt
530 *  stack.
531 */
532SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
533
534/**
535 *  @ingroup CPUInterrupt
536 *  With some compilation systems, it is difficult if not impossible to
537 *  call a high-level language routine from assembly language.  This
538 *  is especially true of commercial Ada compilers and name mangling
539 *  C++ ones.  This variable can be optionally defined by the CPU porter
540 *  and contains the address of the routine @ref _Thread_Dispatch.  This
541 *  can make it easier to invoke that routine at the end of the interrupt
542 *  sequence (if a dispatch is necessary).
543 *
544 *  Port Specific Information:
545 *
546 *  XXX document implementation including references if appropriate
547 */
548SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
549
550/*
551 *  Nothing prevents the porter from declaring more CPU specific variables.
552 *
553 *  Port Specific Information:
554 *
555 *  XXX document implementation including references if appropriate
556 */
557
558/* XXX: if needed, put more variables here */
559
560/**
561 *  @ingroup CPUContext
562 *  The size of the floating point context area.  On some CPUs this
563 *  will not be a "sizeof" because the format of the floating point
564 *  area is not defined -- only the size is.  This is usually on
565 *  CPUs with a "floating point save context" instruction.
566 *
567 *  Port Specific Information:
568 *
569 *  XXX document implementation including references if appropriate
570 */
571#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
572
573/**
574 *  Amount of extra stack (above minimum stack size) required by
575 *  MPCI receive server thread.  Remember that in a multiprocessor
576 *  system this thread must exist and be able to process all directives.
577 *
578 *  Port Specific Information:
579 *
580 *  XXX document implementation including references if appropriate
581 */
582#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
583
584/**
585 *  @ingroup CPUInterrupt
586 *  This defines the number of entries in the @ref _ISR_Vector_table managed
587 *  by RTEMS.
588 *
589 *  Port Specific Information:
590 *
591 *  XXX document implementation including references if appropriate
592 */
593#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
594
595/**
596 *  @ingroup CPUInterrupt
597 *  This defines the highest interrupt vector number for this port.
598 */
599#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
600
601/**
602 *  @ingroup CPUInterrupt
603 *  This is defined if the port has a special way to report the ISR nesting
604 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
605 */
606#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
607
608/**
609 *  @ingroup CPUContext
610 *  Should be large enough to run all RTEMS tests.  This ensures
611 *  that a "reasonable" small application should not have any problems.
612 *
613 *  Port Specific Information:
614 *
615 *  XXX document implementation including references if appropriate
616 */
617#define CPU_STACK_MINIMUM_SIZE          (1024*4)
618
619/**
620 *  CPU's worst alignment requirement for data types on a byte boundary.  This
621 *  alignment does not take into account the requirements for the stack.
622 *
623 *  Port Specific Information:
624 *
625 *  XXX document implementation including references if appropriate
626 */
627#define CPU_ALIGNMENT              8
628
629/**
630 *  This number corresponds to the byte alignment requirement for the
631 *  heap handler.  This alignment requirement may be stricter than that
632 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
633 *  common for the heap to follow the same alignment requirement as
634 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
635 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
636 *
637 *  @note  This does not have to be a power of 2 although it should be
638 *         a multiple of 2 greater than or equal to 2.  The requirement
639 *         to be a multiple of 2 is because the heap uses the least
640 *         significant field of the front and back flags to indicate
641 *         that a block is in use or free.  So you do not want any odd
642 *         length blocks really putting length data in that bit.
643 *
644 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
645 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
646 *         elements allocated from the heap meet all restrictions.
647 *
648 *  Port Specific Information:
649 *
650 *  XXX document implementation including references if appropriate
651 */
652#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
653
654/**
655 *  This number corresponds to the byte alignment requirement for memory
656 *  buffers allocated by the partition manager.  This alignment requirement
657 *  may be stricter than that for the data types alignment specified by
658 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
659 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
660 *  strict enough for the partition, then this should be set to
661 *  @ref CPU_ALIGNMENT.
662 *
663 *  @note  This does not have to be a power of 2.  It does have to
664 *         be greater or equal to than @ref CPU_ALIGNMENT.
665 *
666 *  Port Specific Information:
667 *
668 *  XXX document implementation including references if appropriate
669 */
670#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
671
672/**
673 *  This number corresponds to the byte alignment requirement for the
674 *  stack.  This alignment requirement may be stricter than that for the
675 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
676 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
677 *  set to 0.
678 *
679 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
680 *
681 *  Port Specific Information:
682 *
683 *  XXX document implementation including references if appropriate
684 */
685#define CPU_STACK_ALIGNMENT        0
686
687/*
688 *  ISR handler macros
689 */
690
691/**
692 *  @ingroup CPUInterrupt
693 *  Support routine to initialize the RTEMS vector table after it is allocated.
694 *
695 *  Port Specific Information:
696 *
697 *  XXX document implementation including references if appropriate
698 */
699#define _CPU_Initialize_vectors()
700
701/**
702 *  @ingroup CPUInterrupt
703 *  Disable all interrupts for an RTEMS critical section.  The previous
704 *  level is returned in @a _isr_cookie.
705 *
706 *  @param[out] _isr_cookie will contain the previous level cookie
707 *
708 *  Port Specific Information:
709 *
710 *  XXX document implementation including references if appropriate
711 */
712#define _CPU_ISR_Disable( _isr_cookie ) \
713  { \
714    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
715  }
716
717/**
718 *  @ingroup CPUInterrupt
719 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
720 *  This indicates the end of an RTEMS critical section.  The parameter
721 *  @a _isr_cookie is not modified.
722 *
723 *  @param[in] _isr_cookie contain the previous level cookie
724 *
725 *  Port Specific Information:
726 *
727 *  XXX document implementation including references if appropriate
728 */
729#define _CPU_ISR_Enable( _isr_cookie )  \
730  { \
731  }
732
733/**
734 *  @ingroup CPUInterrupt
735 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
736 *  disabling them again.  This is used to divide long RTEMS critical
737 *  sections into two or more parts.  The parameter @a _isr_cookie is not
738 *  modified.
739 *
740 *  @param[in] _isr_cookie contain the previous level cookie
741 *
742 *  Port Specific Information:
743 *
744 *  XXX document implementation including references if appropriate
745 */
746#define _CPU_ISR_Flash( _isr_cookie ) \
747  { \
748  }
749
750/**
751 *  @ingroup CPUInterrupt
752 *
753 *  This routine and @ref _CPU_ISR_Get_level
754 *  Map the interrupt level in task mode onto the hardware that the CPU
755 *  actually provides.  Currently, interrupt levels which do not
756 *  map onto the CPU in a generic fashion are undefined.  Someday,
757 *  it would be nice if these were "mapped" by the application
758 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
759 *  8 - 255 would be available for bsp/application specific meaning.
760 *  This could be used to manage a programmable interrupt controller
761 *  via the rtems_task_mode directive.
762 *
763 *  Port Specific Information:
764 *
765 *  XXX document implementation including references if appropriate
766 */
767#define _CPU_ISR_Set_level( new_level ) \
768  { \
769  }
770
771/**
772 *  @ingroup CPUInterrupt
773 *  Return the current interrupt disable level for this task in
774 *  the format used by the interrupt level portion of the task mode.
775 *
776 *  @note This routine usually must be implemented as a subroutine.
777 *
778 *  Port Specific Information:
779 *
780 *  XXX document implementation including references if appropriate
781 */
782uint32_t   _CPU_ISR_Get_level( void );
783
784/* end of ISR handler macros */
785
786/* Context handler macros */
787
788/**
789 *  @ingroup CPUContext
790 *  Initialize the context to a state suitable for starting a
791 *  task after a context restore operation.  Generally, this
792 *  involves:
793 *
794 *     - setting a starting address
795 *     - preparing the stack
796 *     - preparing the stack and frame pointers
797 *     - setting the proper interrupt level in the context
798 *     - initializing the floating point context
799 *
800 *  This routine generally does not set any unnecessary register
801 *  in the context.  The state of the "general data" registers is
802 *  undefined at task start time.
803 *
804 *  @param[in] _the_context is the context structure to be initialized
805 *  @param[in] _stack_base is the lowest physical address of this task's stack
806 *  @param[in] _size is the size of this task's stack
807 *  @param[in] _isr is the interrupt disable level
808 *  @param[in] _entry_point is the thread's entry point.  This is
809 *         always @a _Thread_Handler
810 *  @param[in] _is_fp is TRUE if the thread is to be a floating
811 *        point thread.  This is typically only used on CPUs where the
812 *        FPU may be easily disabled by software such as on the SPARC
813 *        where the PSR contains an enable FPU bit.
814 *
815 *  Port Specific Information:
816 *
817 *  XXX document implementation including references if appropriate
818 */
819#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
820                                 _isr, _entry_point, _is_fp ) \
821  { \
822  }
823
824/**
825 *  This routine is responsible for somehow restarting the currently
826 *  executing task.  If you are lucky, then all that is necessary
827 *  is restoring the context.  Otherwise, there will need to be
828 *  a special assembly routine which does something special in this
829 *  case.  For many ports, simply adding a label to the restore path
830 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
831 *  possibly to load a few arguments and jump to the restore path. It will
832 *  not work if restarting self conflicts with the stack frame
833 *  assumptions of restoring a context.
834 *
835 *  Port Specific Information:
836 *
837 *  XXX document implementation including references if appropriate
838 */
839#define _CPU_Context_Restart_self( _the_context ) \
840   _CPU_Context_restore( (_the_context) );
841
842/**
843 *  @ingroup CPUContext
844 *  The purpose of this macro is to allow the initial pointer into
845 *  a floating point context area (used to save the floating point
846 *  context) to be at an arbitrary place in the floating point
847 *  context area.
848 *
849 *  This is necessary because some FP units are designed to have
850 *  their context saved as a stack which grows into lower addresses.
851 *  Other FP units can be saved by simply moving registers into offsets
852 *  from the base of the context area.  Finally some FP units provide
853 *  a "dump context" instruction which could fill in from high to low
854 *  or low to high based on the whim of the CPU designers.
855 *
856 *  @param[in] _base is the lowest physical address of the floating point
857 *         context area
858 *  @param[in] _offset is the offset into the floating point area
859 *
860 *  Port Specific Information:
861 *
862 *  XXX document implementation including references if appropriate
863 */
864#define _CPU_Context_Fp_start( _base, _offset ) \
865   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
866
867/**
868 *  This routine initializes the FP context area passed to it to.
869 *  There are a few standard ways in which to initialize the
870 *  floating point context.  The code included for this macro assumes
871 *  that this is a CPU in which a "initial" FP context was saved into
872 *  @a _CPU_Null_fp_context and it simply copies it to the destination
873 *  context passed to it.
874 *
875 *  Other floating point context save/restore models include:
876 *    -# not doing anything, and
877 *    -# putting a "null FP status word" in the correct place in the FP context.
878 *
879 *  @param[in] _destination is the floating point context area
880 *
881 *  Port Specific Information:
882 *
883 *  XXX document implementation including references if appropriate
884 */
885#define _CPU_Context_Initialize_fp( _destination ) \
886  { \
887   *(*(_destination)) = _CPU_Null_fp_context; \
888  }
889
890/* end of Context handler macros */
891
892/* Fatal Error manager macros */
893
894/**
895 *  This routine copies _error into a known place -- typically a stack
896 *  location or a register, optionally disables interrupts, and
897 *  halts/stops the CPU.
898 *
899 *  Port Specific Information:
900 *
901 *  XXX document implementation including references if appropriate
902 */
903#define _CPU_Fatal_halt( _error ) \
904  { \
905  }
906
907/* end of Fatal Error manager macros */
908
909/* Bitfield handler macros */
910
911/**
912 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
913 *
914 *  This set of routines are used to implement fast searches for
915 *  the most important ready task.
916 */
917
918/**
919 *  @ingroup CPUBitfield
920 *  This definition is set to TRUE if the port uses the generic bitfield
921 *  manipulation implementation.
922 */
923#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
924
925/**
926 *  @ingroup CPUBitfield
927 *  This definition is set to TRUE if the port uses the data tables provided
928 *  by the generic bitfield manipulation implementation.
929 *  This can occur when actually using the generic bitfield manipulation
930 *  implementation or when implementing the same algorithm in assembly
931 *  language for improved performance.  It is unlikely that a port will use
932 *  the data if it has a bitfield scan instruction.
933 */
934#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
935
936/**
937 *  @ingroup CPUBitfield
938 *  This routine sets @a _output to the bit number of the first bit
939 *  set in @a _value.  @a _value is of CPU dependent type
940 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
941 *  wide although only the 16 least significant bits will be used.
942 *
943 *  There are a number of variables in using a "find first bit" type
944 *  instruction.
945 *
946 *    -# What happens when run on a value of zero?
947 *    -# Bits may be numbered from MSB to LSB or vice-versa.
948 *    -# The numbering may be zero or one based.
949 *    -# The "find first bit" instruction may search from MSB or LSB.
950 *
951 *  RTEMS guarantees that (1) will never happen so it is not a concern.
952 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
953 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
954 *  which must logically operate together.  Bits in the _value are
955 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
956 *  The basic major and minor values calculated by @ref _Priority_Major
957 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
958 *  to properly range between the values returned by the "find first bit"
959 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
960 *  calculate the major and directly index into the minor table.
961 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
962 *  is the first bit found.
963 *
964 *  This entire "find first bit" and mapping process depends heavily
965 *  on the manner in which a priority is broken into a major and minor
966 *  components with the major being the 4 MSB of a priority and minor
967 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
968 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
969 *  to the lowest priority.
970 *
971 *  If your CPU does not have a "find first bit" instruction, then
972 *  there are ways to make do without it.  Here are a handful of ways
973 *  to implement this in software:
974 *
975@verbatim
976      - a series of 16 bit test instructions
977      - a "binary search using if's"
978      - _number = 0
979        if _value > 0x00ff
980          _value >>=8
981          _number = 8;
982 
983        if _value > 0x0000f
984          _value >=8
985          _number += 4
986 
987        _number += bit_set_table[ _value ]
988@endverbatim
989 
990 *    where bit_set_table[ 16 ] has values which indicate the first
991 *      bit set
992 *
993 *  @param[in] _value is the value to be scanned
994 *  @param[in] _output is the first bit set
995 *
996 *  Port Specific Information:
997 *
998 *  XXX document implementation including references if appropriate
999 */
1000
1001#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1002#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1003  { \
1004    (_output) = 0;   /* do something to prevent warnings */ \
1005  }
1006#endif
1007
1008/* end of Bitfield handler macros */
1009
1010/**
1011 *  This routine builds the mask which corresponds to the bit fields
1012 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1013 *  for that routine.
1014 *
1015 *  Port Specific Information:
1016 *
1017 *  XXX document implementation including references if appropriate
1018 */
1019#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1020
1021#define _CPU_Priority_Mask( _bit_number ) \
1022  ( 1 << (_bit_number) )
1023
1024#endif
1025
1026/**
1027 *  @ingroup CPUBitfield
1028 *  This routine translates the bit numbers returned by
1029 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1030 *  a major or minor component of a priority.  See the discussion
1031 *  for that routine.
1032 *
1033 *  @param[in] _priority is the major or minor number to translate
1034 *
1035 *  Port Specific Information:
1036 *
1037 *  XXX document implementation including references if appropriate
1038 */
1039#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1040
1041#define _CPU_Priority_bits_index( _priority ) \
1042  (_priority)
1043
1044#endif
1045
1046/* end of Priority handler macros */
1047
1048/* functions */
1049
1050/**
1051 *  This routine performs CPU dependent initialization.
1052 *
1053 *  @param[in] thread_dispatch is the address of @ref _Thread_Dispatch
1054 *
1055 *  Port Specific Information:
1056 *
1057 *  XXX document implementation including references if appropriate
1058 */
1059void _CPU_Initialize(
1060  void      (*thread_dispatch)
1061);
1062
1063/**
1064 *  @ingroup CPUInterrupt
1065 *  This routine installs a "raw" interrupt handler directly into the
1066 *  processor's vector table.
1067 *
1068 *  @param[in] vector is the vector number
1069 *  @param[in] new_handler is the raw ISR handler to install
1070 *  @param[in] old_handler is the previously installed ISR Handler
1071 *
1072 *  Port Specific Information:
1073 *
1074 *  XXX document implementation including references if appropriate
1075 */
1076void _CPU_ISR_install_raw_handler(
1077  uint32_t    vector,
1078  proc_ptr    new_handler,
1079  proc_ptr   *old_handler
1080);
1081
1082/**
1083 *  @ingroup CPUInterrupt
1084 *  This routine installs an interrupt vector.
1085 *
1086 *  @param[in] vector is the vector number
1087 *  @param[in] new_handler is the RTEMS ISR handler to install
1088 *  @param[in] old_handler is the previously installed ISR Handler
1089 *
1090 *  Port Specific Information:
1091 *
1092 *  XXX document implementation including references if appropriate
1093 */
1094void _CPU_ISR_install_vector(
1095  uint32_t    vector,
1096  proc_ptr    new_handler,
1097  proc_ptr   *old_handler
1098);
1099
1100/**
1101 *  @ingroup CPUInterrupt
1102 *  This routine installs the hardware interrupt stack pointer.
1103 *
1104 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1105 *         is TRUE.
1106 *
1107 *  Port Specific Information:
1108 *
1109 *  XXX document implementation including references if appropriate
1110 */
1111void _CPU_Install_interrupt_stack( void );
1112
1113/**
1114 *  This routine is the CPU dependent IDLE thread body.
1115 *
1116 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1117 *         is TRUE.
1118 *
1119 *  Port Specific Information:
1120 *
1121 *  XXX document implementation including references if appropriate
1122 */
1123void _CPU_Thread_Idle_body( void );
1124
1125/**
1126 *  @ingroup CPUContext
1127 *  This routine switches from the run context to the heir context.
1128 *
1129 *  @param[in] run points to the context of the currently executing task
1130 *  @param[in] heir points to the context of the heir task
1131 *
1132 *  Port Specific Information:
1133 *
1134 *  XXX document implementation including references if appropriate
1135 */
1136void _CPU_Context_switch(
1137  Context_Control  *run,
1138  Context_Control  *heir
1139);
1140
1141/**
1142 *  @ingroup CPUContext
1143 *  This routine is generally used only to restart self in an
1144 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1145 *
1146 *  @param[in] new_context points to the context to be restored.
1147 *
1148 *  @note May be unnecessary to reload some registers.
1149 *
1150 *  Port Specific Information:
1151 *
1152 *  XXX document implementation including references if appropriate
1153 */
1154void _CPU_Context_restore(
1155  Context_Control *new_context
1156);
1157
1158/**
1159 *  @ingroup CPUContext
1160 *  This routine saves the floating point context passed to it.
1161 *
1162 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1163 *  point context area
1164 *
1165 *  @return on output @a *fp_context_ptr will contain the address that
1166 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1167 *
1168 *  Port Specific Information:
1169 *
1170 *  XXX document implementation including references if appropriate
1171 */
1172void _CPU_Context_save_fp(
1173  Context_Control_fp **fp_context_ptr
1174);
1175
1176/**
1177 *  @ingroup CPUContext
1178 *  This routine restores the floating point context passed to it.
1179 *
1180 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1181 *  point context area to restore
1182 *
1183 *  @return on output @a *fp_context_ptr will contain the address that
1184 *  should be used with @ref _CPU_Context_save_fp to save this context.
1185 *
1186 *  Port Specific Information:
1187 *
1188 *  XXX document implementation including references if appropriate
1189 */
1190void _CPU_Context_restore_fp(
1191  Context_Control_fp **fp_context_ptr
1192);
1193
1194/**
1195 *  @ingroup CPUEndian
1196 *  The following routine swaps the endian format of an unsigned int.
1197 *  It must be static because it is referenced indirectly.
1198 *
1199 *  This version will work on any processor, but if there is a better
1200 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1201 *
1202 *     swap least significant two bytes with 16-bit rotate
1203 *     swap upper and lower 16-bits
1204 *     swap most significant two bytes with 16-bit rotate
1205 *
1206 *  Some CPUs have special instructions which swap a 32-bit quantity in
1207 *  a single instruction (e.g. i486).  It is probably best to avoid
1208 *  an "endian swapping control bit" in the CPU.  One good reason is
1209 *  that interrupts would probably have to be disabled to ensure that
1210 *  an interrupt does not try to access the same "chunk" with the wrong
1211 *  endian.  Another good reason is that on some CPUs, the endian bit
1212 *  endianness for ALL fetches -- both code and data -- so the code
1213 *  will be fetched incorrectly.
1214 *
1215 *  @param[in] value is the value to be swapped
1216 *  @return the value after being endian swapped
1217 *
1218 *  Port Specific Information:
1219 *
1220 *  XXX document implementation including references if appropriate
1221 */
1222static inline uint32_t CPU_swap_u32(
1223  uint32_t value
1224)
1225{
1226  uint32_t byte1, byte2, byte3, byte4, swapped;
1227 
1228  byte4 = (value >> 24) & 0xff;
1229  byte3 = (value >> 16) & 0xff;
1230  byte2 = (value >> 8)  & 0xff;
1231  byte1 =  value        & 0xff;
1232 
1233  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1234  return swapped;
1235}
1236
1237/**
1238 *  @ingroup CPUEndian
1239 *  This routine swaps a 16 bir quantity.
1240 *
1241 *  @param[in] value is the value to be swapped
1242 *  @return the value after being endian swapped
1243 */
1244#define CPU_swap_u16( value ) \
1245  (((value&0xff) << 8) | ((value >> 8)&0xff))
1246
1247#ifdef __cplusplus
1248}
1249#endif
1250
1251#endif
Note: See TracBrowser for help on using the repository browser.