source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 4ef13360

4.11
Last change on this file since 4ef13360 was 4ef13360, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 29, 2010 at 5:51:56 PM

2010-07-29 Gedare Bloom <giddyup44@…>

PR 1635/cpukit

  • rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority handling, to isolate the bitmap implementation of priorities in the supercore so that priority management is a little more modular. This change is in anticipation of scheduler implementations that can select how they manage tracking priority levels / finding the highest priority ready task. Note that most of the changes here are simple renaming, to clarify the use of the bitmap-based priority management.
  • Property mode set to 100644
File size: 40.8 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 *
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/types.h>
41#include <rtems/score/no_cpu.h>
42
43/* conditional compilation parameters */
44
45/**
46 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
47 *
48 *  If TRUE, then they are inlined.
49 *  If FALSE, then a subroutine call is made.
50 *
51 *  This conditional is an example of the classic trade-off of size
52 *  versus speed.  Inlining the call (TRUE) typically increases the
53 *  size of RTEMS while speeding up the enabling of dispatching.
54 *
55 *  @note In general, the @ref _Thread_Dispatch_disable_level will
56 *  only be 0 or 1 unless you are in an interrupt handler and that
57 *  interrupt handler invokes the executive.]  When not inlined
58 *  something calls @ref _Thread_Enable_dispatch which in turns calls
59 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
60 *  one subroutine call is avoided entirely.
61 *
62 *  Port Specific Information:
63 *
64 *  XXX document implementation including references if appropriate
65 */
66#define CPU_INLINE_ENABLE_DISPATCH       FALSE
67
68/**
69 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
70 *  be unrolled one time?  In unrolled each iteration of the loop examines
71 *  two "nodes" on the chain being searched.  Otherwise, only one node
72 *  is examined per iteration.
73 *
74 *  If TRUE, then the loops are unrolled.
75 *  If FALSE, then the loops are not unrolled.
76 *
77 *  The primary factor in making this decision is the cost of disabling
78 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
79 *  body of the loop.  On some CPUs, the flash is more expensive than
80 *  one iteration of the loop body.  In this case, it might be desirable
81 *  to unroll the loop.  It is important to note that on some CPUs, this
82 *  code is the longest interrupt disable period in RTEMS.  So it is
83 *  necessary to strike a balance when setting this parameter.
84 *
85 *  Port Specific Information:
86 *
87 *  XXX document implementation including references if appropriate
88 */
89#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
90
91/**
92 *  Does RTEMS manage a dedicated interrupt stack in software?
93 *
94 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
95 *  If FALSE, nothing is done.
96 *
97 *  If the CPU supports a dedicated interrupt stack in hardware,
98 *  then it is generally the responsibility of the BSP to allocate it
99 *  and set it up.
100 *
101 *  If the CPU does not support a dedicated interrupt stack, then
102 *  the porter has two options: (1) execute interrupts on the
103 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
104 *  interrupt stack.
105 *
106 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
107 *
108 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
109 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
110 *  possible that both are FALSE for a particular CPU.  Although it
111 *  is unclear what that would imply about the interrupt processing
112 *  procedure on that CPU.
113 *
114 *  Port Specific Information:
115 *
116 *  XXX document implementation including references if appropriate
117 */
118#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
119
120/**
121 *  Does the CPU follow the simple vectored interrupt model?
122 *
123 *  If TRUE, then RTEMS allocates the vector table it internally manages.
124 *  If FALSE, then the BSP is assumed to allocate and manage the vector
125 *  table
126 *
127 *  Port Specific Information:
128 *
129 *  XXX document implementation including references if appropriate
130 */
131#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
132
133/**
134 *  Does this CPU have hardware support for a dedicated interrupt stack?
135 *
136 *  If TRUE, then it must be installed during initialization.
137 *  If FALSE, then no installation is performed.
138 *
139 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
140 *
141 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
142 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
143 *  possible that both are FALSE for a particular CPU.  Although it
144 *  is unclear what that would imply about the interrupt processing
145 *  procedure on that CPU.
146 *
147 *  Port Specific Information:
148 *
149 *  XXX document implementation including references if appropriate
150 */
151#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
152
153/**
154 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
155 *
156 *  If TRUE, then the memory is allocated during initialization.
157 *  If FALSE, then the memory is allocated during initialization.
158 *
159 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
160 *
161 *  Port Specific Information:
162 *
163 *  XXX document implementation including references if appropriate
164 */
165#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
166
167/**
168 *  Does the RTEMS invoke the user's ISR with the vector number and
169 *  a pointer to the saved interrupt frame (1) or just the vector
170 *  number (0)?
171 *
172 *  Port Specific Information:
173 *
174 *  XXX document implementation including references if appropriate
175 */
176#define CPU_ISR_PASSES_FRAME_POINTER 0
177
178/**
179 *  @def CPU_HARDWARE_FP
180 *
181 *  Does the CPU have hardware floating point?
182 *
183 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
184 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
185 *
186 *  If there is a FP coprocessor such as the i387 or mc68881, then
187 *  the answer is TRUE.
188 *
189 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
190 *  It indicates whether or not this CPU model has FP support.  For
191 *  example, it would be possible to have an i386_nofp CPU model
192 *  which set this to false to indicate that you have an i386 without
193 *  an i387 and wish to leave floating point support out of RTEMS.
194 */
195
196/**
197 *  @def CPU_SOFTWARE_FP
198 *
199 *  Does the CPU have no hardware floating point and GCC provides a
200 *  software floating point implementation which must be context
201 *  switched?
202 *
203 *  This feature conditional is used to indicate whether or not there
204 *  is software implemented floating point that must be context
205 *  switched.  The determination of whether or not this applies
206 *  is very tool specific and the state saved/restored is also
207 *  compiler specific.
208 *
209 *  Port Specific Information:
210 *
211 *  XXX document implementation including references if appropriate
212 */
213#if ( NO_CPU_HAS_FPU == 1 )
214#define CPU_HARDWARE_FP     TRUE
215#else
216#define CPU_HARDWARE_FP     FALSE
217#endif
218#define CPU_SOFTWARE_FP     FALSE
219
220/**
221 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
222 *
223 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
224 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
225 *
226 *  So far, the only CPUs in which this option has been used are the
227 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
228 *  gcc both implicitly used the floating point registers to perform
229 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
230 *  seen to allocate floating point local variables and touch the FPU
231 *  even when the flow through a subroutine (like vfprintf()) might
232 *  not use floating point formats.
233 *
234 *  If a function which you would not think utilize the FP unit DOES,
235 *  then one can not easily predict which tasks will use the FP hardware.
236 *  In this case, this option should be TRUE.
237 *
238 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
239 *
240 *  Port Specific Information:
241 *
242 *  XXX document implementation including references if appropriate
243 */
244#define CPU_ALL_TASKS_ARE_FP     TRUE
245
246/**
247 *  Should the IDLE task have a floating point context?
248 *
249 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
250 *  and it has a floating point context which is switched in and out.
251 *  If FALSE, then the IDLE task does not have a floating point context.
252 *
253 *  Setting this to TRUE negatively impacts the time required to preempt
254 *  the IDLE task from an interrupt because the floating point context
255 *  must be saved as part of the preemption.
256 *
257 *  Port Specific Information:
258 *
259 *  XXX document implementation including references if appropriate
260 */
261#define CPU_IDLE_TASK_IS_FP      FALSE
262
263/**
264 *  Should the saving of the floating point registers be deferred
265 *  until a context switch is made to another different floating point
266 *  task?
267 *
268 *  If TRUE, then the floating point context will not be stored until
269 *  necessary.  It will remain in the floating point registers and not
270 *  disturned until another floating point task is switched to.
271 *
272 *  If FALSE, then the floating point context is saved when a floating
273 *  point task is switched out and restored when the next floating point
274 *  task is restored.  The state of the floating point registers between
275 *  those two operations is not specified.
276 *
277 *  If the floating point context does NOT have to be saved as part of
278 *  interrupt dispatching, then it should be safe to set this to TRUE.
279 *
280 *  Setting this flag to TRUE results in using a different algorithm
281 *  for deciding when to save and restore the floating point context.
282 *  The deferred FP switch algorithm minimizes the number of times
283 *  the FP context is saved and restored.  The FP context is not saved
284 *  until a context switch is made to another, different FP task.
285 *  Thus in a system with only one FP task, the FP context will never
286 *  be saved or restored.
287 *
288 *  Port Specific Information:
289 *
290 *  XXX document implementation including references if appropriate
291 */
292#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
293
294/**
295 *  Does this port provide a CPU dependent IDLE task implementation?
296 *
297 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
298 *  must be provided and is the default IDLE thread body instead of
299 *  @ref _CPU_Thread_Idle_body.
300 *
301 *  If FALSE, then use the generic IDLE thread body if the BSP does
302 *  not provide one.
303 *
304 *  This is intended to allow for supporting processors which have
305 *  a low power or idle mode.  When the IDLE thread is executed, then
306 *  the CPU can be powered down.
307 *
308 *  The order of precedence for selecting the IDLE thread body is:
309 *
310 *    -#  BSP provided
311 *    -#  CPU dependent (if provided)
312 *    -#  generic (if no BSP and no CPU dependent)
313 *
314 *  Port Specific Information:
315 *
316 *  XXX document implementation including references if appropriate
317 */
318#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
319
320/**
321 *  Does the stack grow up (toward higher addresses) or down
322 *  (toward lower addresses)?
323 *
324 *  If TRUE, then the grows upward.
325 *  If FALSE, then the grows toward smaller addresses.
326 *
327 *  Port Specific Information:
328 *
329 *  XXX document implementation including references if appropriate
330 */
331#define CPU_STACK_GROWS_UP               TRUE
332
333/**
334 *  The following is the variable attribute used to force alignment
335 *  of critical RTEMS structures.  On some processors it may make
336 *  sense to have these aligned on tighter boundaries than
337 *  the minimum requirements of the compiler in order to have as
338 *  much of the critical data area as possible in a cache line.
339 *
340 *  The placement of this macro in the declaration of the variables
341 *  is based on the syntactically requirements of the GNU C
342 *  "__attribute__" extension.  For example with GNU C, use
343 *  the following to force a structures to a 32 byte boundary.
344 *
345 *      __attribute__ ((aligned (32)))
346 *
347 *  @note Currently only the Priority Bit Map table uses this feature.
348 *        To benefit from using this, the data must be heavily
349 *        used so it will stay in the cache and used frequently enough
350 *        in the executive to justify turning this on.
351 *
352 *  Port Specific Information:
353 *
354 *  XXX document implementation including references if appropriate
355 */
356#define CPU_STRUCTURE_ALIGNMENT
357
358/**
359 *  @defgroup CPUEndian Processor Dependent Endianness Support
360 *
361 *  This group assists in issues related to processor endianness.
362 */
363
364/**
365 *  @ingroup CPUEndian
366 *  Define what is required to specify how the network to host conversion
367 *  routines are handled.
368 *
369 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
370 *  same values.
371 *
372 *  @see CPU_LITTLE_ENDIAN
373 *
374 *  Port Specific Information:
375 *
376 *  XXX document implementation including references if appropriate
377 */
378#define CPU_BIG_ENDIAN                           TRUE
379
380/**
381 *  @ingroup CPUEndian
382 *  Define what is required to specify how the network to host conversion
383 *  routines are handled.
384 *
385 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
386 *  same values.
387 *
388 *  @see CPU_BIG_ENDIAN
389 *
390 *  Port Specific Information:
391 *
392 *  XXX document implementation including references if appropriate
393 */
394#define CPU_LITTLE_ENDIAN                        FALSE
395
396/**
397 *  @ingroup CPUInterrupt
398 *  The following defines the number of bits actually used in the
399 *  interrupt field of the task mode.  How those bits map to the
400 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
401 *
402 *  Port Specific Information:
403 *
404 *  XXX document implementation including references if appropriate
405 */
406#define CPU_MODES_INTERRUPT_MASK   0x00000001
407
408/*
409 *  Processor defined structures required for cpukit/score.
410 *
411 *  Port Specific Information:
412 *
413 *  XXX document implementation including references if appropriate
414 */
415
416/* may need to put some structures here.  */
417
418/**
419 * @defgroup CPUContext Processor Dependent Context Management
420 *
421 *  From the highest level viewpoint, there are 2 types of context to save.
422 *
423 *     -# Interrupt registers to save
424 *     -# Task level registers to save
425 *
426 *  Since RTEMS handles integer and floating point contexts separately, this
427 *  means we have the following 3 context items:
428 *
429 *     -# task level context stuff::  Context_Control
430 *     -# floating point task stuff:: Context_Control_fp
431 *     -# special interrupt level context :: CPU_Interrupt_frame
432 *
433 *  On some processors, it is cost-effective to save only the callee
434 *  preserved registers during a task context switch.  This means
435 *  that the ISR code needs to save those registers which do not
436 *  persist across function calls.  It is not mandatory to make this
437 *  distinctions between the caller/callee saves registers for the
438 *  purpose of minimizing context saved during task switch and on interrupts.
439 *  If the cost of saving extra registers is minimal, simplicity is the
440 *  choice.  Save the same context on interrupt entry as for tasks in
441 *  this case.
442 *
443 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
444 *  care should be used in designing the context area.
445 *
446 *  On some CPUs with hardware floating point support, the Context_Control_fp
447 *  structure will not be used or it simply consist of an array of a
448 *  fixed number of bytes.   This is done when the floating point context
449 *  is dumped by a "FP save context" type instruction and the format
450 *  is not really defined by the CPU.  In this case, there is no need
451 *  to figure out the exact format -- only the size.  Of course, although
452 *  this is enough information for RTEMS, it is probably not enough for
453 *  a debugger such as gdb.  But that is another problem.
454 *
455 *  Port Specific Information:
456 *
457 *  XXX document implementation including references if appropriate
458 */
459
460/**
461 *  @ingroup CPUContext Management
462 *  This defines the minimal set of integer and processor state registers
463 *  that must be saved during a voluntary context switch from one thread
464 *  to another.
465 */
466typedef struct {
467    /** This field is a hint that a port will have a number of integer
468     *  registers that need to be saved at a context switch.
469     */
470    uint32_t   some_integer_register;
471    /** This field is a hint that a port will have a number of system
472     *  registers that need to be saved at a context switch.
473     */
474    uint32_t   some_system_register;
475
476    /** This field is a hint that a port will have a register that
477     *  is the stack pointer.
478     */
479    uint32_t   stack_pointer;
480} Context_Control;
481
482/**
483 *  @ingroup CPUContext Management
484 *
485 *  This macro returns the stack pointer associated with @a _context.
486 *
487 *  @param[in] _context is the thread context area to access
488 *
489 *  @return This method returns the stack pointer.
490 */
491#define _CPU_Context_Get_SP( _context ) \
492  (_context)->stack_pointer
493
494/**
495 *  @ingroup CPUContext Management
496 *  This defines the complete set of floating point registers that must
497 *  be saved during any context switch from one thread to another.
498 */
499typedef struct {
500    /** FPU registers are listed here */
501    double      some_float_register;
502} Context_Control_fp;
503
504/**
505 *  @ingroup CPUContext Management
506 *  This defines the set of integer and processor state registers that must
507 *  be saved during an interrupt.  This set does not include any which are
508 *  in @ref Context_Control.
509 */
510typedef struct {
511    /** This field is a hint that a port will have a number of integer
512     *  registers that need to be saved when an interrupt occurs or
513     *  when a context switch occurs at the end of an ISR.
514     */
515    uint32_t   special_interrupt_register;
516} CPU_Interrupt_frame;
517
518/**
519 *  This variable is optional.  It is used on CPUs on which it is difficult
520 *  to generate an "uninitialized" FP context.  It is filled in by
521 *  @ref _CPU_Initialize and copied into the task's FP context area during
522 *  @ref _CPU_Context_Initialize.
523 *
524 *  Port Specific Information:
525 *
526 *  XXX document implementation including references if appropriate
527 */
528SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
529
530/**
531 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
532 *
533 *  On some CPUs, RTEMS supports a software managed interrupt stack.
534 *  This stack is allocated by the Interrupt Manager and the switch
535 *  is performed in @ref _ISR_Handler.  These variables contain pointers
536 *  to the lowest and highest addresses in the chunk of memory allocated
537 *  for the interrupt stack.  Since it is unknown whether the stack
538 *  grows up or down (in general), this give the CPU dependent
539 *  code the option of picking the version it wants to use.
540 *
541 *  @note These two variables are required if the macro
542 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
543 *
544 *  Port Specific Information:
545 *
546 *  XXX document implementation including references if appropriate
547 */
548
549/*
550 *  Nothing prevents the porter from declaring more CPU specific variables.
551 *
552 *  Port Specific Information:
553 *
554 *  XXX document implementation including references if appropriate
555 */
556
557/* XXX: if needed, put more variables here */
558
559/**
560 *  @ingroup CPUContext
561 *  The size of the floating point context area.  On some CPUs this
562 *  will not be a "sizeof" because the format of the floating point
563 *  area is not defined -- only the size is.  This is usually on
564 *  CPUs with a "floating point save context" instruction.
565 *
566 *  Port Specific Information:
567 *
568 *  XXX document implementation including references if appropriate
569 */
570#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
571
572/**
573 *  Amount of extra stack (above minimum stack size) required by
574 *  MPCI receive server thread.  Remember that in a multiprocessor
575 *  system this thread must exist and be able to process all directives.
576 *
577 *  Port Specific Information:
578 *
579 *  XXX document implementation including references if appropriate
580 */
581#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
582
583/**
584 *  @ingroup CPUInterrupt
585 *  This defines the number of entries in the @ref _ISR_Vector_table managed
586 *  by RTEMS.
587 *
588 *  Port Specific Information:
589 *
590 *  XXX document implementation including references if appropriate
591 */
592#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
593
594/**
595 *  @ingroup CPUInterrupt
596 *  This defines the highest interrupt vector number for this port.
597 */
598#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
599
600/**
601 *  @ingroup CPUInterrupt
602 *  This is defined if the port has a special way to report the ISR nesting
603 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
604 */
605#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
606
607/**
608 *  @ingroup CPUContext
609 *  Should be large enough to run all RTEMS tests.  This ensures
610 *  that a "reasonable" small application should not have any problems.
611 *
612 *  Port Specific Information:
613 *
614 *  XXX document implementation including references if appropriate
615 */
616#define CPU_STACK_MINIMUM_SIZE          (1024*4)
617
618/**
619 *  CPU's worst alignment requirement for data types on a byte boundary.  This
620 *  alignment does not take into account the requirements for the stack.
621 *
622 *  Port Specific Information:
623 *
624 *  XXX document implementation including references if appropriate
625 */
626#define CPU_ALIGNMENT              8
627
628/**
629 *  This number corresponds to the byte alignment requirement for the
630 *  heap handler.  This alignment requirement may be stricter than that
631 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
632 *  common for the heap to follow the same alignment requirement as
633 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
634 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
635 *
636 *  @note  This does not have to be a power of 2 although it should be
637 *         a multiple of 2 greater than or equal to 2.  The requirement
638 *         to be a multiple of 2 is because the heap uses the least
639 *         significant field of the front and back flags to indicate
640 *         that a block is in use or free.  So you do not want any odd
641 *         length blocks really putting length data in that bit.
642 *
643 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
644 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
645 *         elements allocated from the heap meet all restrictions.
646 *
647 *  Port Specific Information:
648 *
649 *  XXX document implementation including references if appropriate
650 */
651#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
652
653/**
654 *  This number corresponds to the byte alignment requirement for memory
655 *  buffers allocated by the partition manager.  This alignment requirement
656 *  may be stricter than that for the data types alignment specified by
657 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
658 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
659 *  strict enough for the partition, then this should be set to
660 *  @ref CPU_ALIGNMENT.
661 *
662 *  @note  This does not have to be a power of 2.  It does have to
663 *         be greater or equal to than @ref CPU_ALIGNMENT.
664 *
665 *  Port Specific Information:
666 *
667 *  XXX document implementation including references if appropriate
668 */
669#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
670
671/**
672 *  This number corresponds to the byte alignment requirement for the
673 *  stack.  This alignment requirement may be stricter than that for the
674 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
675 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
676 *  set to 0.
677 *
678 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
679 *
680 *  Port Specific Information:
681 *
682 *  XXX document implementation including references if appropriate
683 */
684#define CPU_STACK_ALIGNMENT        0
685
686/*
687 *  ISR handler macros
688 */
689
690/**
691 *  @ingroup CPUInterrupt
692 *  Support routine to initialize the RTEMS vector table after it is allocated.
693 *
694 *  Port Specific Information:
695 *
696 *  XXX document implementation including references if appropriate
697 */
698#define _CPU_Initialize_vectors()
699
700/**
701 *  @ingroup CPUInterrupt
702 *  Disable all interrupts for an RTEMS critical section.  The previous
703 *  level is returned in @a _isr_cookie.
704 *
705 *  @param[out] _isr_cookie will contain the previous level cookie
706 *
707 *  Port Specific Information:
708 *
709 *  XXX document implementation including references if appropriate
710 */
711#define _CPU_ISR_Disable( _isr_cookie ) \
712  { \
713    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
714  }
715
716/**
717 *  @ingroup CPUInterrupt
718 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
719 *  This indicates the end of an RTEMS critical section.  The parameter
720 *  @a _isr_cookie is not modified.
721 *
722 *  @param[in] _isr_cookie contain the previous level cookie
723 *
724 *  Port Specific Information:
725 *
726 *  XXX document implementation including references if appropriate
727 */
728#define _CPU_ISR_Enable( _isr_cookie )  \
729  { \
730  }
731
732/**
733 *  @ingroup CPUInterrupt
734 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
735 *  disabling them again.  This is used to divide long RTEMS critical
736 *  sections into two or more parts.  The parameter @a _isr_cookie is not
737 *  modified.
738 *
739 *  @param[in] _isr_cookie contain the previous level cookie
740 *
741 *  Port Specific Information:
742 *
743 *  XXX document implementation including references if appropriate
744 */
745#define _CPU_ISR_Flash( _isr_cookie ) \
746  { \
747  }
748
749/**
750 *  @ingroup CPUInterrupt
751 *
752 *  This routine and @ref _CPU_ISR_Get_level
753 *  Map the interrupt level in task mode onto the hardware that the CPU
754 *  actually provides.  Currently, interrupt levels which do not
755 *  map onto the CPU in a generic fashion are undefined.  Someday,
756 *  it would be nice if these were "mapped" by the application
757 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
758 *  8 - 255 would be available for bsp/application specific meaning.
759 *  This could be used to manage a programmable interrupt controller
760 *  via the rtems_task_mode directive.
761 *
762 *  Port Specific Information:
763 *
764 *  XXX document implementation including references if appropriate
765 */
766#define _CPU_ISR_Set_level( new_level ) \
767  { \
768  }
769
770/**
771 *  @ingroup CPUInterrupt
772 *  Return the current interrupt disable level for this task in
773 *  the format used by the interrupt level portion of the task mode.
774 *
775 *  @note This routine usually must be implemented as a subroutine.
776 *
777 *  Port Specific Information:
778 *
779 *  XXX document implementation including references if appropriate
780 */
781uint32_t   _CPU_ISR_Get_level( void );
782
783/* end of ISR handler macros */
784
785/* Context handler macros */
786
787/**
788 *  @ingroup CPUContext
789 *  Initialize the context to a state suitable for starting a
790 *  task after a context restore operation.  Generally, this
791 *  involves:
792 *
793 *     - setting a starting address
794 *     - preparing the stack
795 *     - preparing the stack and frame pointers
796 *     - setting the proper interrupt level in the context
797 *     - initializing the floating point context
798 *
799 *  This routine generally does not set any unnecessary register
800 *  in the context.  The state of the "general data" registers is
801 *  undefined at task start time.
802 *
803 *  @param[in] _the_context is the context structure to be initialized
804 *  @param[in] _stack_base is the lowest physical address of this task's stack
805 *  @param[in] _size is the size of this task's stack
806 *  @param[in] _isr is the interrupt disable level
807 *  @param[in] _entry_point is the thread's entry point.  This is
808 *         always @a _Thread_Handler
809 *  @param[in] _is_fp is TRUE if the thread is to be a floating
810 *        point thread.  This is typically only used on CPUs where the
811 *        FPU may be easily disabled by software such as on the SPARC
812 *        where the PSR contains an enable FPU bit.
813 *
814 *  Port Specific Information:
815 *
816 *  XXX document implementation including references if appropriate
817 */
818#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
819                                 _isr, _entry_point, _is_fp ) \
820  { \
821  }
822
823/**
824 *  This routine is responsible for somehow restarting the currently
825 *  executing task.  If you are lucky, then all that is necessary
826 *  is restoring the context.  Otherwise, there will need to be
827 *  a special assembly routine which does something special in this
828 *  case.  For many ports, simply adding a label to the restore path
829 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
830 *  possibly to load a few arguments and jump to the restore path. It will
831 *  not work if restarting self conflicts with the stack frame
832 *  assumptions of restoring a context.
833 *
834 *  Port Specific Information:
835 *
836 *  XXX document implementation including references if appropriate
837 */
838#define _CPU_Context_Restart_self( _the_context ) \
839   _CPU_Context_restore( (_the_context) );
840
841/**
842 *  @ingroup CPUContext
843 *  The purpose of this macro is to allow the initial pointer into
844 *  a floating point context area (used to save the floating point
845 *  context) to be at an arbitrary place in the floating point
846 *  context area.
847 *
848 *  This is necessary because some FP units are designed to have
849 *  their context saved as a stack which grows into lower addresses.
850 *  Other FP units can be saved by simply moving registers into offsets
851 *  from the base of the context area.  Finally some FP units provide
852 *  a "dump context" instruction which could fill in from high to low
853 *  or low to high based on the whim of the CPU designers.
854 *
855 *  @param[in] _base is the lowest physical address of the floating point
856 *         context area
857 *  @param[in] _offset is the offset into the floating point area
858 *
859 *  Port Specific Information:
860 *
861 *  XXX document implementation including references if appropriate
862 */
863#define _CPU_Context_Fp_start( _base, _offset ) \
864   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
865
866/**
867 *  This routine initializes the FP context area passed to it to.
868 *  There are a few standard ways in which to initialize the
869 *  floating point context.  The code included for this macro assumes
870 *  that this is a CPU in which a "initial" FP context was saved into
871 *  @a _CPU_Null_fp_context and it simply copies it to the destination
872 *  context passed to it.
873 *
874 *  Other floating point context save/restore models include:
875 *    -# not doing anything, and
876 *    -# putting a "null FP status word" in the correct place in the FP context.
877 *
878 *  @param[in] _destination is the floating point context area
879 *
880 *  Port Specific Information:
881 *
882 *  XXX document implementation including references if appropriate
883 */
884#define _CPU_Context_Initialize_fp( _destination ) \
885  { \
886   *(*(_destination)) = _CPU_Null_fp_context; \
887  }
888
889/* end of Context handler macros */
890
891/* Fatal Error manager macros */
892
893/**
894 *  This routine copies _error into a known place -- typically a stack
895 *  location or a register, optionally disables interrupts, and
896 *  halts/stops the CPU.
897 *
898 *  Port Specific Information:
899 *
900 *  XXX document implementation including references if appropriate
901 */
902#define _CPU_Fatal_halt( _error ) \
903  { \
904  }
905
906/* end of Fatal Error manager macros */
907
908/* Bitfield handler macros */
909
910/**
911 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
912 *
913 *  This set of routines are used to implement fast searches for
914 *  the most important ready task.
915 */
916
917/**
918 *  @ingroup CPUBitfield
919 *  This definition is set to TRUE if the port uses the generic bitfield
920 *  manipulation implementation.
921 */
922#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
923
924/**
925 *  @ingroup CPUBitfield
926 *  This definition is set to TRUE if the port uses the data tables provided
927 *  by the generic bitfield manipulation implementation.
928 *  This can occur when actually using the generic bitfield manipulation
929 *  implementation or when implementing the same algorithm in assembly
930 *  language for improved performance.  It is unlikely that a port will use
931 *  the data if it has a bitfield scan instruction.
932 */
933#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
934
935/**
936 *  @ingroup CPUBitfield
937 *  This routine sets @a _output to the bit number of the first bit
938 *  set in @a _value.  @a _value is of CPU dependent type
939 *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
940 *  wide although only the 16 least significant bits will be used.
941 *
942 *  There are a number of variables in using a "find first bit" type
943 *  instruction.
944 *
945 *    -# What happens when run on a value of zero?
946 *    -# Bits may be numbered from MSB to LSB or vice-versa.
947 *    -# The numbering may be zero or one based.
948 *    -# The "find first bit" instruction may search from MSB or LSB.
949 *
950 *  RTEMS guarantees that (1) will never happen so it is not a concern.
951 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
952 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
953 *  which must logically operate together.  Bits in the _value are
954 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
955 *  The basic major and minor values calculated by @ref _Priority_Major
956 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
957 *  to properly range between the values returned by the "find first bit"
958 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
959 *  calculate the major and directly index into the minor table.
960 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
961 *  is the first bit found.
962 *
963 *  This entire "find first bit" and mapping process depends heavily
964 *  on the manner in which a priority is broken into a major and minor
965 *  components with the major being the 4 MSB of a priority and minor
966 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
967 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
968 *  to the lowest priority.
969 *
970 *  If your CPU does not have a "find first bit" instruction, then
971 *  there are ways to make do without it.  Here are a handful of ways
972 *  to implement this in software:
973 *
974@verbatim
975      - a series of 16 bit test instructions
976      - a "binary search using if's"
977      - _number = 0
978        if _value > 0x00ff
979          _value >>=8
980          _number = 8;
981
982        if _value > 0x0000f
983          _value >=8
984          _number += 4
985
986        _number += bit_set_table[ _value ]
987@endverbatim
988
989 *    where bit_set_table[ 16 ] has values which indicate the first
990 *      bit set
991 *
992 *  @param[in] _value is the value to be scanned
993 *  @param[in] _output is the first bit set
994 *
995 *  Port Specific Information:
996 *
997 *  XXX document implementation including references if appropriate
998 */
999
1000#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1001#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1002  { \
1003    (_output) = 0;   /* do something to prevent warnings */ \
1004  }
1005#endif
1006
1007/* end of Bitfield handler macros */
1008
1009/**
1010 *  This routine builds the mask which corresponds to the bit fields
1011 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1012 *  for that routine.
1013 *
1014 *  Port Specific Information:
1015 *
1016 *  XXX document implementation including references if appropriate
1017 */
1018#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1019
1020#define _CPU_Priority_Mask( _bit_number ) \
1021  ( 1 << (_bit_number) )
1022
1023#endif
1024
1025/**
1026 *  @ingroup CPUBitfield
1027 *  This routine translates the bit numbers returned by
1028 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1029 *  a major or minor component of a priority.  See the discussion
1030 *  for that routine.
1031 *
1032 *  @param[in] _priority is the major or minor number to translate
1033 *
1034 *  Port Specific Information:
1035 *
1036 *  XXX document implementation including references if appropriate
1037 */
1038#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1039
1040#define _CPU_Priority_bits_index( _priority ) \
1041  (_priority)
1042
1043#endif
1044
1045/* end of Priority handler macros */
1046
1047/* functions */
1048
1049/**
1050 *  This routine performs CPU dependent initialization.
1051 *
1052 *  Port Specific Information:
1053 *
1054 *  XXX document implementation including references if appropriate
1055 */
1056void _CPU_Initialize(void);
1057
1058/**
1059 *  @ingroup CPUInterrupt
1060 *  This routine installs a "raw" interrupt handler directly into the
1061 *  processor's vector table.
1062 *
1063 *  @param[in] vector is the vector number
1064 *  @param[in] new_handler is the raw ISR handler to install
1065 *  @param[in] old_handler is the previously installed ISR Handler
1066 *
1067 *  Port Specific Information:
1068 *
1069 *  XXX document implementation including references if appropriate
1070 */
1071void _CPU_ISR_install_raw_handler(
1072  uint32_t    vector,
1073  proc_ptr    new_handler,
1074  proc_ptr   *old_handler
1075);
1076
1077/**
1078 *  @ingroup CPUInterrupt
1079 *  This routine installs an interrupt vector.
1080 *
1081 *  @param[in] vector is the vector number
1082 *  @param[in] new_handler is the RTEMS ISR handler to install
1083 *  @param[in] old_handler is the previously installed ISR Handler
1084 *
1085 *  Port Specific Information:
1086 *
1087 *  XXX document implementation including references if appropriate
1088 */
1089void _CPU_ISR_install_vector(
1090  uint32_t    vector,
1091  proc_ptr    new_handler,
1092  proc_ptr   *old_handler
1093);
1094
1095/**
1096 *  @ingroup CPUInterrupt
1097 *  This routine installs the hardware interrupt stack pointer.
1098 *
1099 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1100 *         is TRUE.
1101 *
1102 *  Port Specific Information:
1103 *
1104 *  XXX document implementation including references if appropriate
1105 */
1106void _CPU_Install_interrupt_stack( void );
1107
1108/**
1109 *  This routine is the CPU dependent IDLE thread body.
1110 *
1111 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1112 *         is TRUE.
1113 *
1114 *  Port Specific Information:
1115 *
1116 *  XXX document implementation including references if appropriate
1117 */
1118void *_CPU_Thread_Idle_body( uintptr_t ignored );
1119
1120/**
1121 *  @ingroup CPUContext
1122 *  This routine switches from the run context to the heir context.
1123 *
1124 *  @param[in] run points to the context of the currently executing task
1125 *  @param[in] heir points to the context of the heir task
1126 *
1127 *  Port Specific Information:
1128 *
1129 *  XXX document implementation including references if appropriate
1130 */
1131void _CPU_Context_switch(
1132  Context_Control  *run,
1133  Context_Control  *heir
1134);
1135
1136/**
1137 *  @ingroup CPUContext
1138 *  This routine is generally used only to restart self in an
1139 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1140 *
1141 *  @param[in] new_context points to the context to be restored.
1142 *
1143 *  @note May be unnecessary to reload some registers.
1144 *
1145 *  Port Specific Information:
1146 *
1147 *  XXX document implementation including references if appropriate
1148 */
1149void _CPU_Context_restore(
1150  Context_Control *new_context
1151);
1152
1153/**
1154 *  @ingroup CPUContext
1155 *  This routine saves the floating point context passed to it.
1156 *
1157 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1158 *  point context area
1159 *
1160 *  @return on output @a *fp_context_ptr will contain the address that
1161 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1162 *
1163 *  Port Specific Information:
1164 *
1165 *  XXX document implementation including references if appropriate
1166 */
1167void _CPU_Context_save_fp(
1168  Context_Control_fp **fp_context_ptr
1169);
1170
1171/**
1172 *  @ingroup CPUContext
1173 *  This routine restores the floating point context passed to it.
1174 *
1175 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1176 *  point context area to restore
1177 *
1178 *  @return on output @a *fp_context_ptr will contain the address that
1179 *  should be used with @ref _CPU_Context_save_fp to save this context.
1180 *
1181 *  Port Specific Information:
1182 *
1183 *  XXX document implementation including references if appropriate
1184 */
1185void _CPU_Context_restore_fp(
1186  Context_Control_fp **fp_context_ptr
1187);
1188
1189/**
1190 *  @ingroup CPUEndian
1191 *  The following routine swaps the endian format of an unsigned int.
1192 *  It must be static because it is referenced indirectly.
1193 *
1194 *  This version will work on any processor, but if there is a better
1195 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1196 *
1197 *     swap least significant two bytes with 16-bit rotate
1198 *     swap upper and lower 16-bits
1199 *     swap most significant two bytes with 16-bit rotate
1200 *
1201 *  Some CPUs have special instructions which swap a 32-bit quantity in
1202 *  a single instruction (e.g. i486).  It is probably best to avoid
1203 *  an "endian swapping control bit" in the CPU.  One good reason is
1204 *  that interrupts would probably have to be disabled to ensure that
1205 *  an interrupt does not try to access the same "chunk" with the wrong
1206 *  endian.  Another good reason is that on some CPUs, the endian bit
1207 *  endianness for ALL fetches -- both code and data -- so the code
1208 *  will be fetched incorrectly.
1209 *
1210 *  @param[in] value is the value to be swapped
1211 *  @return the value after being endian swapped
1212 *
1213 *  Port Specific Information:
1214 *
1215 *  XXX document implementation including references if appropriate
1216 */
1217static inline uint32_t CPU_swap_u32(
1218  uint32_t value
1219)
1220{
1221  uint32_t byte1, byte2, byte3, byte4, swapped;
1222
1223  byte4 = (value >> 24) & 0xff;
1224  byte3 = (value >> 16) & 0xff;
1225  byte2 = (value >> 8)  & 0xff;
1226  byte1 =  value        & 0xff;
1227
1228  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1229  return swapped;
1230}
1231
1232/**
1233 *  @ingroup CPUEndian
1234 *  This routine swaps a 16 bir quantity.
1235 *
1236 *  @param[in] value is the value to be swapped
1237 *  @return the value after being endian swapped
1238 */
1239#define CPU_swap_u16( value ) \
1240  (((value&0xff) << 8) | ((value >> 8)&0xff))
1241
1242#ifdef __cplusplus
1243}
1244#endif
1245
1246#endif
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