source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 3d0e458

4.104.11
Last change on this file since 3d0e458 was 3d0e458, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 2, 2008 at 8:20:17 PM

2008-10-02 Joel Sherrill <joel.sherrill@…>

  • cpu_asm.c, rtems/score/cpu.h, rtems/score/types.h: Corrections and updates.
  • Property mode set to 100644
File size: 42.0 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 * 
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 *
30 *  $Id$
31 */
32
33#ifndef _RTEMS_SCORE_CPU_H
34#define _RTEMS_SCORE_CPU_H
35
36#ifdef __cplusplus
37extern "C" {
38#endif
39
40#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
41#ifndef ASM
42#include <rtems/score/types.h>
43#endif
44
45/* conditional compilation parameters */
46
47/**
48 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
49 *
50 *  If TRUE, then they are inlined.
51 *  If FALSE, then a subroutine call is made.
52 *
53 *  This conditional is an example of the classic trade-off of size
54 *  versus speed.  Inlining the call (TRUE) typically increases the
55 *  size of RTEMS while speeding up the enabling of dispatching.
56 *
57 *  @note In general, the @ref _Thread_Dispatch_disable_level will
58 *  only be 0 or 1 unless you are in an interrupt handler and that
59 *  interrupt handler invokes the executive.]  When not inlined
60 *  something calls @ref _Thread_Enable_dispatch which in turns calls
61 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
62 *  one subroutine call is avoided entirely.
63 *
64 *  Port Specific Information:
65 *
66 *  XXX document implementation including references if appropriate
67 */
68#define CPU_INLINE_ENABLE_DISPATCH       FALSE
69
70/**
71 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
72 *  be unrolled one time?  In unrolled each iteration of the loop examines
73 *  two "nodes" on the chain being searched.  Otherwise, only one node
74 *  is examined per iteration.
75 *
76 *  If TRUE, then the loops are unrolled.
77 *  If FALSE, then the loops are not unrolled.
78 *
79 *  The primary factor in making this decision is the cost of disabling
80 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
81 *  body of the loop.  On some CPUs, the flash is more expensive than
82 *  one iteration of the loop body.  In this case, it might be desirable
83 *  to unroll the loop.  It is important to note that on some CPUs, this
84 *  code is the longest interrupt disable period in RTEMS.  So it is
85 *  necessary to strike a balance when setting this parameter.
86 *
87 *  Port Specific Information:
88 *
89 *  XXX document implementation including references if appropriate
90 */
91#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
92
93/**
94 *  Does RTEMS manage a dedicated interrupt stack in software?
95 *
96 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
97 *  If FALSE, nothing is done.
98 *
99 *  If the CPU supports a dedicated interrupt stack in hardware,
100 *  then it is generally the responsibility of the BSP to allocate it
101 *  and set it up.
102 *
103 *  If the CPU does not support a dedicated interrupt stack, then
104 *  the porter has two options: (1) execute interrupts on the
105 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
106 *  interrupt stack.
107 *
108 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
109 *
110 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
111 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
112 *  possible that both are FALSE for a particular CPU.  Although it
113 *  is unclear what that would imply about the interrupt processing
114 *  procedure on that CPU.
115 *
116 *  Port Specific Information:
117 *
118 *  XXX document implementation including references if appropriate
119 */
120#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
121
122/**
123 *  Does the CPU follow the simple vectored interrupt model?
124 *
125 *  If TRUE, then RTEMS allocates the vector table it internally manages.
126 *  If FALSE, then the BSP is assumed to allocate and manage the vector
127 *  table
128 *
129 *  Port Specific Information:
130 *
131 *  XXX document implementation including references if appropriate
132 */
133#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
134
135/**
136 *  Does this CPU have hardware support for a dedicated interrupt stack?
137 *
138 *  If TRUE, then it must be installed during initialization.
139 *  If FALSE, then no installation is performed.
140 *
141 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
142 *
143 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
144 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
145 *  possible that both are FALSE for a particular CPU.  Although it
146 *  is unclear what that would imply about the interrupt processing
147 *  procedure on that CPU.
148 *
149 *  Port Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
154
155/**
156 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
157 *
158 *  If TRUE, then the memory is allocated during initialization.
159 *  If FALSE, then the memory is allocated during initialization.
160 *
161 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
162 *
163 *  Port Specific Information:
164 *
165 *  XXX document implementation including references if appropriate
166 */
167#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
168
169/**
170 *  Does the RTEMS invoke the user's ISR with the vector number and
171 *  a pointer to the saved interrupt frame (1) or just the vector
172 *  number (0)?
173 *
174 *  Port Specific Information:
175 *
176 *  XXX document implementation including references if appropriate
177 */
178#define CPU_ISR_PASSES_FRAME_POINTER 0
179
180/**
181 *  @def CPU_HARDWARE_FP
182 *
183 *  Does the CPU have hardware floating point?
184 *
185 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
186 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
187 *
188 *  If there is a FP coprocessor such as the i387 or mc68881, then
189 *  the answer is TRUE.
190 *
191 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
192 *  It indicates whether or not this CPU model has FP support.  For
193 *  example, it would be possible to have an i386_nofp CPU model
194 *  which set this to false to indicate that you have an i386 without
195 *  an i387 and wish to leave floating point support out of RTEMS.
196 */
197
198/**
199 *  @def CPU_SOFTWARE_FP
200 *
201 *  Does the CPU have no hardware floating point and GCC provides a
202 *  software floating point implementation which must be context
203 *  switched?
204 *
205 *  This feature conditional is used to indicate whether or not there
206 *  is software implemented floating point that must be context
207 *  switched.  The determination of whether or not this applies
208 *  is very tool specific and the state saved/restored is also
209 *  compiler specific.
210 *
211 *  Port Specific Information:
212 *
213 *  XXX document implementation including references if appropriate
214 */
215#if ( NO_CPU_HAS_FPU == 1 )
216#define CPU_HARDWARE_FP     TRUE
217#else
218#define CPU_HARDWARE_FP     FALSE
219#endif
220#define CPU_SOFTWARE_FP     FALSE
221
222/**
223 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
224 *
225 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
226 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
227 *
228 *  So far, the only CPUs in which this option has been used are the
229 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
230 *  gcc both implicitly used the floating point registers to perform
231 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
232 *  seen to allocate floating point local variables and touch the FPU
233 *  even when the flow through a subroutine (like vfprintf()) might
234 *  not use floating point formats.
235 *
236 *  If a function which you would not think utilize the FP unit DOES,
237 *  then one can not easily predict which tasks will use the FP hardware.
238 *  In this case, this option should be TRUE.
239 *
240 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
241 *
242 *  Port Specific Information:
243 *
244 *  XXX document implementation including references if appropriate
245 */
246#define CPU_ALL_TASKS_ARE_FP     TRUE
247
248/**
249 *  Should the IDLE task have a floating point context?
250 *
251 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
252 *  and it has a floating point context which is switched in and out.
253 *  If FALSE, then the IDLE task does not have a floating point context.
254 *
255 *  Setting this to TRUE negatively impacts the time required to preempt
256 *  the IDLE task from an interrupt because the floating point context
257 *  must be saved as part of the preemption.
258 *
259 *  Port Specific Information:
260 *
261 *  XXX document implementation including references if appropriate
262 */
263#define CPU_IDLE_TASK_IS_FP      FALSE
264
265/**
266 *  Should the saving of the floating point registers be deferred
267 *  until a context switch is made to another different floating point
268 *  task?
269 *
270 *  If TRUE, then the floating point context will not be stored until
271 *  necessary.  It will remain in the floating point registers and not
272 *  disturned until another floating point task is switched to.
273 *
274 *  If FALSE, then the floating point context is saved when a floating
275 *  point task is switched out and restored when the next floating point
276 *  task is restored.  The state of the floating point registers between
277 *  those two operations is not specified.
278 *
279 *  If the floating point context does NOT have to be saved as part of
280 *  interrupt dispatching, then it should be safe to set this to TRUE.
281 *
282 *  Setting this flag to TRUE results in using a different algorithm
283 *  for deciding when to save and restore the floating point context.
284 *  The deferred FP switch algorithm minimizes the number of times
285 *  the FP context is saved and restored.  The FP context is not saved
286 *  until a context switch is made to another, different FP task.
287 *  Thus in a system with only one FP task, the FP context will never
288 *  be saved or restored.
289 *
290 *  Port Specific Information:
291 *
292 *  XXX document implementation including references if appropriate
293 */
294#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
295
296/**
297 *  Does this port provide a CPU dependent IDLE task implementation?
298 *
299 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
300 *  must be provided and is the default IDLE thread body instead of
301 *  @ref _CPU_Thread_Idle_body.
302 *
303 *  If FALSE, then use the generic IDLE thread body if the BSP does
304 *  not provide one.
305 *
306 *  This is intended to allow for supporting processors which have
307 *  a low power or idle mode.  When the IDLE thread is executed, then
308 *  the CPU can be powered down.
309 *
310 *  The order of precedence for selecting the IDLE thread body is:
311 *
312 *    -#  BSP provided
313 *    -#  CPU dependent (if provided)
314 *    -#  generic (if no BSP and no CPU dependent)
315 *
316 *  Port Specific Information:
317 *
318 *  XXX document implementation including references if appropriate
319 */
320#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
321
322/**
323 *  Does the stack grow up (toward higher addresses) or down
324 *  (toward lower addresses)?
325 *
326 *  If TRUE, then the grows upward.
327 *  If FALSE, then the grows toward smaller addresses.
328 *
329 *  Port Specific Information:
330 *
331 *  XXX document implementation including references if appropriate
332 */
333#define CPU_STACK_GROWS_UP               TRUE
334
335/**
336 *  The following is the variable attribute used to force alignment
337 *  of critical RTEMS structures.  On some processors it may make
338 *  sense to have these aligned on tighter boundaries than
339 *  the minimum requirements of the compiler in order to have as
340 *  much of the critical data area as possible in a cache line.
341 *
342 *  The placement of this macro in the declaration of the variables
343 *  is based on the syntactically requirements of the GNU C
344 *  "__attribute__" extension.  For example with GNU C, use
345 *  the following to force a structures to a 32 byte boundary.
346 *
347 *      __attribute__ ((aligned (32)))
348 *
349 *  @note Currently only the Priority Bit Map table uses this feature.
350 *        To benefit from using this, the data must be heavily
351 *        used so it will stay in the cache and used frequently enough
352 *        in the executive to justify turning this on.
353 *
354 *  Port Specific Information:
355 *
356 *  XXX document implementation including references if appropriate
357 */
358#define CPU_STRUCTURE_ALIGNMENT
359
360/**
361 *  @defgroup CPUEndian Processor Dependent Endianness Support
362 *
363 *  This group assists in issues related to processor endianness.
364 */
365
366/**
367 *  @ingroup CPUEndian
368 *  Define what is required to specify how the network to host conversion
369 *  routines are handled.
370 *
371 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
372 *  same values.
373 *
374 *  @see CPU_LITTLE_ENDIAN
375 *
376 *  Port Specific Information:
377 *
378 *  XXX document implementation including references if appropriate
379 */
380#define CPU_BIG_ENDIAN                           TRUE
381
382/**
383 *  @ingroup CPUEndian
384 *  Define what is required to specify how the network to host conversion
385 *  routines are handled.
386 *
387 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
388 *  same values.
389 *
390 *  @see CPU_BIG_ENDIAN
391 *
392 *  Port Specific Information:
393 *
394 *  XXX document implementation including references if appropriate
395 */
396#define CPU_LITTLE_ENDIAN                        FALSE
397
398/**
399 *  @ingroup CPUInterrupt
400 *  The following defines the number of bits actually used in the
401 *  interrupt field of the task mode.  How those bits map to the
402 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
403 *
404 *  Port Specific Information:
405 *
406 *  XXX document implementation including references if appropriate
407 */
408#define CPU_MODES_INTERRUPT_MASK   0x00000001
409
410/*
411 *  Processor defined structures required for cpukit/score.
412 *
413 *  Port Specific Information:
414 *
415 *  XXX document implementation including references if appropriate
416 */
417
418/* may need to put some structures here.  */
419
420/**
421 * @defgroup CPUContext Processor Dependent Context Management
422 *
423 *  From the highest level viewpoint, there are 2 types of context to save.
424 *
425 *     -# Interrupt registers to save
426 *     -# Task level registers to save
427 *
428 *  Since RTEMS handles integer and floating point contexts separately, this
429 *  means we have the following 3 context items:
430 *
431 *     -# task level context stuff::  Context_Control
432 *     -# floating point task stuff:: Context_Control_fp
433 *     -# special interrupt level context :: CPU_Interrupt_frame
434 *
435 *  On some processors, it is cost-effective to save only the callee
436 *  preserved registers during a task context switch.  This means
437 *  that the ISR code needs to save those registers which do not
438 *  persist across function calls.  It is not mandatory to make this
439 *  distinctions between the caller/callee saves registers for the
440 *  purpose of minimizing context saved during task switch and on interrupts.
441 *  If the cost of saving extra registers is minimal, simplicity is the
442 *  choice.  Save the same context on interrupt entry as for tasks in
443 *  this case.
444 *
445 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
446 *  care should be used in designing the context area.
447 *
448 *  On some CPUs with hardware floating point support, the Context_Control_fp
449 *  structure will not be used or it simply consist of an array of a
450 *  fixed number of bytes.   This is done when the floating point context
451 *  is dumped by a "FP save context" type instruction and the format
452 *  is not really defined by the CPU.  In this case, there is no need
453 *  to figure out the exact format -- only the size.  Of course, although
454 *  this is enough information for RTEMS, it is probably not enough for
455 *  a debugger such as gdb.  But that is another problem.
456 *
457 *  Port Specific Information:
458 *
459 *  XXX document implementation including references if appropriate
460 */
461
462/**
463 *  @ingroup CPUContext Management
464 *  This defines the minimal set of integer and processor state registers
465 *  that must be saved during a voluntary context switch from one thread
466 *  to another.
467 */
468typedef struct {
469    /** This field is a hint that a port will have a number of integer
470     *  registers that need to be saved at a context switch.
471     */
472    uint32_t   some_integer_register;
473    /** This field is a hint that a port will have a number of system
474     *  registers that need to be saved at a context switch.
475     */
476    uint32_t   some_system_register;
477
478    /** This field is a hint that a port will have a register that
479     *  is the stack pointer.
480     */
481    uint32_t   stack_pointer;
482} Context_Control;
483
484/**
485 *  @ingroup CPUContext Management
486 *
487 *  This macro returns the stack pointer associated with @a _context.
488 *
489 *  @param[in] _context is the thread context area to access
490 * 
491 *  @return This method returns the stack pointer.
492 */
493#define _CPU_Context_Get_SP( _context ) \
494  (_context)->stack_pointer
495
496/**
497 *  @ingroup CPUContext Management
498 *  This defines the complete set of floating point registers that must
499 *  be saved during any context switch from one thread to another.
500 */
501typedef struct {
502    /** FPU registers are listed here */
503    double      some_float_register;
504} Context_Control_fp;
505
506/**
507 *  @ingroup CPUContext Management
508 *  This defines the set of integer and processor state registers that must
509 *  be saved during an interrupt.  This set does not include any which are
510 *  in @ref Context_Control.
511 */
512typedef struct {
513    /** This field is a hint that a port will have a number of integer
514     *  registers that need to be saved when an interrupt occurs or
515     *  when a context switch occurs at the end of an ISR.
516     */
517    uint32_t   special_interrupt_register;
518} CPU_Interrupt_frame;
519
520/**
521 *  This variable is optional.  It is used on CPUs on which it is difficult
522 *  to generate an "uninitialized" FP context.  It is filled in by
523 *  @ref _CPU_Initialize and copied into the task's FP context area during
524 *  @ref _CPU_Context_Initialize.
525 *
526 *  Port Specific Information:
527 *
528 *  XXX document implementation including references if appropriate
529 */
530SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
531
532/**
533 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
534 *
535 *  On some CPUs, RTEMS supports a software managed interrupt stack.
536 *  This stack is allocated by the Interrupt Manager and the switch
537 *  is performed in @ref _ISR_Handler.  These variables contain pointers
538 *  to the lowest and highest addresses in the chunk of memory allocated
539 *  for the interrupt stack.  Since it is unknown whether the stack
540 *  grows up or down (in general), this give the CPU dependent
541 *  code the option of picking the version it wants to use.
542 *
543 *  @note These two variables are required if the macro
544 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
545 *
546 *  Port Specific Information:
547 *
548 *  XXX document implementation including references if appropriate
549 */
550
551/**
552 *  @ingroup CPUInterrupt
553 *  This variable points to the lowest physical address of the interrupt
554 *  stack.
555 */
556SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
557
558/**
559 *  @ingroup CPUInterrupt
560 *  This variable points to the lowest physical address of the interrupt
561 *  stack.
562 */
563SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
564
565/**
566 *  @ingroup CPUInterrupt
567 *  With some compilation systems, it is difficult if not impossible to
568 *  call a high-level language routine from assembly language.  This
569 *  is especially true of commercial Ada compilers and name mangling
570 *  C++ ones.  This variable can be optionally defined by the CPU porter
571 *  and contains the address of the routine @ref _Thread_Dispatch.  This
572 *  can make it easier to invoke that routine at the end of the interrupt
573 *  sequence (if a dispatch is necessary).
574 *
575 *  Port Specific Information:
576 *
577 *  XXX document implementation including references if appropriate
578 */
579SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)(void);
580
581/*
582 *  Nothing prevents the porter from declaring more CPU specific variables.
583 *
584 *  Port Specific Information:
585 *
586 *  XXX document implementation including references if appropriate
587 */
588
589/* XXX: if needed, put more variables here */
590
591/**
592 *  @ingroup CPUContext
593 *  The size of the floating point context area.  On some CPUs this
594 *  will not be a "sizeof" because the format of the floating point
595 *  area is not defined -- only the size is.  This is usually on
596 *  CPUs with a "floating point save context" instruction.
597 *
598 *  Port Specific Information:
599 *
600 *  XXX document implementation including references if appropriate
601 */
602#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
603
604/**
605 *  Amount of extra stack (above minimum stack size) required by
606 *  MPCI receive server thread.  Remember that in a multiprocessor
607 *  system this thread must exist and be able to process all directives.
608 *
609 *  Port Specific Information:
610 *
611 *  XXX document implementation including references if appropriate
612 */
613#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
614
615/**
616 *  @ingroup CPUInterrupt
617 *  This defines the number of entries in the @ref _ISR_Vector_table managed
618 *  by RTEMS.
619 *
620 *  Port Specific Information:
621 *
622 *  XXX document implementation including references if appropriate
623 */
624#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
625
626/**
627 *  @ingroup CPUInterrupt
628 *  This defines the highest interrupt vector number for this port.
629 */
630#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
631
632/**
633 *  @ingroup CPUInterrupt
634 *  This is defined if the port has a special way to report the ISR nesting
635 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
636 */
637#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
638
639/**
640 *  @ingroup CPUContext
641 *  Should be large enough to run all RTEMS tests.  This ensures
642 *  that a "reasonable" small application should not have any problems.
643 *
644 *  Port Specific Information:
645 *
646 *  XXX document implementation including references if appropriate
647 */
648#define CPU_STACK_MINIMUM_SIZE          (1024*4)
649
650/**
651 *  CPU's worst alignment requirement for data types on a byte boundary.  This
652 *  alignment does not take into account the requirements for the stack.
653 *
654 *  Port Specific Information:
655 *
656 *  XXX document implementation including references if appropriate
657 */
658#define CPU_ALIGNMENT              8
659
660/**
661 *  This number corresponds to the byte alignment requirement for the
662 *  heap handler.  This alignment requirement may be stricter than that
663 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
664 *  common for the heap to follow the same alignment requirement as
665 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
666 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
667 *
668 *  @note  This does not have to be a power of 2 although it should be
669 *         a multiple of 2 greater than or equal to 2.  The requirement
670 *         to be a multiple of 2 is because the heap uses the least
671 *         significant field of the front and back flags to indicate
672 *         that a block is in use or free.  So you do not want any odd
673 *         length blocks really putting length data in that bit.
674 *
675 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
676 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
677 *         elements allocated from the heap meet all restrictions.
678 *
679 *  Port Specific Information:
680 *
681 *  XXX document implementation including references if appropriate
682 */
683#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
684
685/**
686 *  This number corresponds to the byte alignment requirement for memory
687 *  buffers allocated by the partition manager.  This alignment requirement
688 *  may be stricter than that for the data types alignment specified by
689 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
690 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
691 *  strict enough for the partition, then this should be set to
692 *  @ref CPU_ALIGNMENT.
693 *
694 *  @note  This does not have to be a power of 2.  It does have to
695 *         be greater or equal to than @ref CPU_ALIGNMENT.
696 *
697 *  Port Specific Information:
698 *
699 *  XXX document implementation including references if appropriate
700 */
701#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
702
703/**
704 *  This number corresponds to the byte alignment requirement for the
705 *  stack.  This alignment requirement may be stricter than that for the
706 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
707 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
708 *  set to 0.
709 *
710 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
711 *
712 *  Port Specific Information:
713 *
714 *  XXX document implementation including references if appropriate
715 */
716#define CPU_STACK_ALIGNMENT        0
717
718/*
719 *  ISR handler macros
720 */
721
722/**
723 *  @ingroup CPUInterrupt
724 *  Support routine to initialize the RTEMS vector table after it is allocated.
725 *
726 *  Port Specific Information:
727 *
728 *  XXX document implementation including references if appropriate
729 */
730#define _CPU_Initialize_vectors()
731
732/**
733 *  @ingroup CPUInterrupt
734 *  Disable all interrupts for an RTEMS critical section.  The previous
735 *  level is returned in @a _isr_cookie.
736 *
737 *  @param[out] _isr_cookie will contain the previous level cookie
738 *
739 *  Port Specific Information:
740 *
741 *  XXX document implementation including references if appropriate
742 */
743#define _CPU_ISR_Disable( _isr_cookie ) \
744  { \
745    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
746  }
747
748/**
749 *  @ingroup CPUInterrupt
750 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
751 *  This indicates the end of an RTEMS critical section.  The parameter
752 *  @a _isr_cookie is not modified.
753 *
754 *  @param[in] _isr_cookie contain the previous level cookie
755 *
756 *  Port Specific Information:
757 *
758 *  XXX document implementation including references if appropriate
759 */
760#define _CPU_ISR_Enable( _isr_cookie )  \
761  { \
762  }
763
764/**
765 *  @ingroup CPUInterrupt
766 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
767 *  disabling them again.  This is used to divide long RTEMS critical
768 *  sections into two or more parts.  The parameter @a _isr_cookie is not
769 *  modified.
770 *
771 *  @param[in] _isr_cookie contain the previous level cookie
772 *
773 *  Port Specific Information:
774 *
775 *  XXX document implementation including references if appropriate
776 */
777#define _CPU_ISR_Flash( _isr_cookie ) \
778  { \
779  }
780
781/**
782 *  @ingroup CPUInterrupt
783 *
784 *  This routine and @ref _CPU_ISR_Get_level
785 *  Map the interrupt level in task mode onto the hardware that the CPU
786 *  actually provides.  Currently, interrupt levels which do not
787 *  map onto the CPU in a generic fashion are undefined.  Someday,
788 *  it would be nice if these were "mapped" by the application
789 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
790 *  8 - 255 would be available for bsp/application specific meaning.
791 *  This could be used to manage a programmable interrupt controller
792 *  via the rtems_task_mode directive.
793 *
794 *  Port Specific Information:
795 *
796 *  XXX document implementation including references if appropriate
797 */
798#define _CPU_ISR_Set_level( new_level ) \
799  { \
800  }
801
802/**
803 *  @ingroup CPUInterrupt
804 *  Return the current interrupt disable level for this task in
805 *  the format used by the interrupt level portion of the task mode.
806 *
807 *  @note This routine usually must be implemented as a subroutine.
808 *
809 *  Port Specific Information:
810 *
811 *  XXX document implementation including references if appropriate
812 */
813uint32_t   _CPU_ISR_Get_level( void );
814
815/* end of ISR handler macros */
816
817/* Context handler macros */
818
819/**
820 *  @ingroup CPUContext
821 *  Initialize the context to a state suitable for starting a
822 *  task after a context restore operation.  Generally, this
823 *  involves:
824 *
825 *     - setting a starting address
826 *     - preparing the stack
827 *     - preparing the stack and frame pointers
828 *     - setting the proper interrupt level in the context
829 *     - initializing the floating point context
830 *
831 *  This routine generally does not set any unnecessary register
832 *  in the context.  The state of the "general data" registers is
833 *  undefined at task start time.
834 *
835 *  @param[in] _the_context is the context structure to be initialized
836 *  @param[in] _stack_base is the lowest physical address of this task's stack
837 *  @param[in] _size is the size of this task's stack
838 *  @param[in] _isr is the interrupt disable level
839 *  @param[in] _entry_point is the thread's entry point.  This is
840 *         always @a _Thread_Handler
841 *  @param[in] _is_fp is TRUE if the thread is to be a floating
842 *        point thread.  This is typically only used on CPUs where the
843 *        FPU may be easily disabled by software such as on the SPARC
844 *        where the PSR contains an enable FPU bit.
845 *
846 *  Port Specific Information:
847 *
848 *  XXX document implementation including references if appropriate
849 */
850#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
851                                 _isr, _entry_point, _is_fp ) \
852  { \
853  }
854
855/**
856 *  This routine is responsible for somehow restarting the currently
857 *  executing task.  If you are lucky, then all that is necessary
858 *  is restoring the context.  Otherwise, there will need to be
859 *  a special assembly routine which does something special in this
860 *  case.  For many ports, simply adding a label to the restore path
861 *  of @ref _CPU_Context_switch will work.  On other ports, it may be
862 *  possibly to load a few arguments and jump to the restore path. It will
863 *  not work if restarting self conflicts with the stack frame
864 *  assumptions of restoring a context.
865 *
866 *  Port Specific Information:
867 *
868 *  XXX document implementation including references if appropriate
869 */
870#define _CPU_Context_Restart_self( _the_context ) \
871   _CPU_Context_restore( (_the_context) );
872
873/**
874 *  @ingroup CPUContext
875 *  The purpose of this macro is to allow the initial pointer into
876 *  a floating point context area (used to save the floating point
877 *  context) to be at an arbitrary place in the floating point
878 *  context area.
879 *
880 *  This is necessary because some FP units are designed to have
881 *  their context saved as a stack which grows into lower addresses.
882 *  Other FP units can be saved by simply moving registers into offsets
883 *  from the base of the context area.  Finally some FP units provide
884 *  a "dump context" instruction which could fill in from high to low
885 *  or low to high based on the whim of the CPU designers.
886 *
887 *  @param[in] _base is the lowest physical address of the floating point
888 *         context area
889 *  @param[in] _offset is the offset into the floating point area
890 *
891 *  Port Specific Information:
892 *
893 *  XXX document implementation including references if appropriate
894 */
895#define _CPU_Context_Fp_start( _base, _offset ) \
896   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
897
898/**
899 *  This routine initializes the FP context area passed to it to.
900 *  There are a few standard ways in which to initialize the
901 *  floating point context.  The code included for this macro assumes
902 *  that this is a CPU in which a "initial" FP context was saved into
903 *  @a _CPU_Null_fp_context and it simply copies it to the destination
904 *  context passed to it.
905 *
906 *  Other floating point context save/restore models include:
907 *    -# not doing anything, and
908 *    -# putting a "null FP status word" in the correct place in the FP context.
909 *
910 *  @param[in] _destination is the floating point context area
911 *
912 *  Port Specific Information:
913 *
914 *  XXX document implementation including references if appropriate
915 */
916#define _CPU_Context_Initialize_fp( _destination ) \
917  { \
918   *(*(_destination)) = _CPU_Null_fp_context; \
919  }
920
921/* end of Context handler macros */
922
923/* Fatal Error manager macros */
924
925/**
926 *  This routine copies _error into a known place -- typically a stack
927 *  location or a register, optionally disables interrupts, and
928 *  halts/stops the CPU.
929 *
930 *  Port Specific Information:
931 *
932 *  XXX document implementation including references if appropriate
933 */
934#define _CPU_Fatal_halt( _error ) \
935  { \
936  }
937
938/* end of Fatal Error manager macros */
939
940/* Bitfield handler macros */
941
942/**
943 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
944 *
945 *  This set of routines are used to implement fast searches for
946 *  the most important ready task.
947 */
948
949/**
950 *  @ingroup CPUBitfield
951 *  This definition is set to TRUE if the port uses the generic bitfield
952 *  manipulation implementation.
953 */
954#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
955
956/**
957 *  @ingroup CPUBitfield
958 *  This definition is set to TRUE if the port uses the data tables provided
959 *  by the generic bitfield manipulation implementation.
960 *  This can occur when actually using the generic bitfield manipulation
961 *  implementation or when implementing the same algorithm in assembly
962 *  language for improved performance.  It is unlikely that a port will use
963 *  the data if it has a bitfield scan instruction.
964 */
965#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
966
967/**
968 *  @ingroup CPUBitfield
969 *  This routine sets @a _output to the bit number of the first bit
970 *  set in @a _value.  @a _value is of CPU dependent type
971 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
972 *  wide although only the 16 least significant bits will be used.
973 *
974 *  There are a number of variables in using a "find first bit" type
975 *  instruction.
976 *
977 *    -# What happens when run on a value of zero?
978 *    -# Bits may be numbered from MSB to LSB or vice-versa.
979 *    -# The numbering may be zero or one based.
980 *    -# The "find first bit" instruction may search from MSB or LSB.
981 *
982 *  RTEMS guarantees that (1) will never happen so it is not a concern.
983 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
984 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
985 *  which must logically operate together.  Bits in the _value are
986 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
987 *  The basic major and minor values calculated by @ref _Priority_Major
988 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
989 *  to properly range between the values returned by the "find first bit"
990 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
991 *  calculate the major and directly index into the minor table.
992 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
993 *  is the first bit found.
994 *
995 *  This entire "find first bit" and mapping process depends heavily
996 *  on the manner in which a priority is broken into a major and minor
997 *  components with the major being the 4 MSB of a priority and minor
998 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
999 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1000 *  to the lowest priority.
1001 *
1002 *  If your CPU does not have a "find first bit" instruction, then
1003 *  there are ways to make do without it.  Here are a handful of ways
1004 *  to implement this in software:
1005 *
1006@verbatim
1007      - a series of 16 bit test instructions
1008      - a "binary search using if's"
1009      - _number = 0
1010        if _value > 0x00ff
1011          _value >>=8
1012          _number = 8;
1013 
1014        if _value > 0x0000f
1015          _value >=8
1016          _number += 4
1017 
1018        _number += bit_set_table[ _value ]
1019@endverbatim
1020 
1021 *    where bit_set_table[ 16 ] has values which indicate the first
1022 *      bit set
1023 *
1024 *  @param[in] _value is the value to be scanned
1025 *  @param[in] _output is the first bit set
1026 *
1027 *  Port Specific Information:
1028 *
1029 *  XXX document implementation including references if appropriate
1030 */
1031
1032#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1033#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1034  { \
1035    (_output) = 0;   /* do something to prevent warnings */ \
1036  }
1037#endif
1038
1039/* end of Bitfield handler macros */
1040
1041/**
1042 *  This routine builds the mask which corresponds to the bit fields
1043 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1044 *  for that routine.
1045 *
1046 *  Port Specific Information:
1047 *
1048 *  XXX document implementation including references if appropriate
1049 */
1050#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1051
1052#define _CPU_Priority_Mask( _bit_number ) \
1053  ( 1 << (_bit_number) )
1054
1055#endif
1056
1057/**
1058 *  @ingroup CPUBitfield
1059 *  This routine translates the bit numbers returned by
1060 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1061 *  a major or minor component of a priority.  See the discussion
1062 *  for that routine.
1063 *
1064 *  @param[in] _priority is the major or minor number to translate
1065 *
1066 *  Port Specific Information:
1067 *
1068 *  XXX document implementation including references if appropriate
1069 */
1070#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1071
1072#define _CPU_Priority_bits_index( _priority ) \
1073  (_priority)
1074
1075#endif
1076
1077/* end of Priority handler macros */
1078
1079/* functions */
1080
1081/**
1082 *  This routine performs CPU dependent initialization.
1083 *
1084 *  @param[in] thread_dispatch is the address of @ref _Thread_Dispatch
1085 *
1086 *  Port Specific Information:
1087 *
1088 *  XXX document implementation including references if appropriate
1089 */
1090void _CPU_Initialize(
1091  void      (*thread_dispatch)
1092);
1093
1094/**
1095 *  @ingroup CPUInterrupt
1096 *  This routine installs a "raw" interrupt handler directly into the
1097 *  processor's vector table.
1098 *
1099 *  @param[in] vector is the vector number
1100 *  @param[in] new_handler is the raw ISR handler to install
1101 *  @param[in] old_handler is the previously installed ISR Handler
1102 *
1103 *  Port Specific Information:
1104 *
1105 *  XXX document implementation including references if appropriate
1106 */
1107void _CPU_ISR_install_raw_handler(
1108  uint32_t    vector,
1109  proc_ptr    new_handler,
1110  proc_ptr   *old_handler
1111);
1112
1113/**
1114 *  @ingroup CPUInterrupt
1115 *  This routine installs an interrupt vector.
1116 *
1117 *  @param[in] vector is the vector number
1118 *  @param[in] new_handler is the RTEMS ISR handler to install
1119 *  @param[in] old_handler is the previously installed ISR Handler
1120 *
1121 *  Port Specific Information:
1122 *
1123 *  XXX document implementation including references if appropriate
1124 */
1125void _CPU_ISR_install_vector(
1126  uint32_t    vector,
1127  proc_ptr    new_handler,
1128  proc_ptr   *old_handler
1129);
1130
1131/**
1132 *  @ingroup CPUInterrupt
1133 *  This routine installs the hardware interrupt stack pointer.
1134 *
1135 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1136 *         is TRUE.
1137 *
1138 *  Port Specific Information:
1139 *
1140 *  XXX document implementation including references if appropriate
1141 */
1142void _CPU_Install_interrupt_stack( void );
1143
1144/**
1145 *  This routine is the CPU dependent IDLE thread body.
1146 *
1147 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1148 *         is TRUE.
1149 *
1150 *  Port Specific Information:
1151 *
1152 *  XXX document implementation including references if appropriate
1153 */
1154void *_CPU_Thread_Idle_body( uint32_t );
1155
1156/**
1157 *  @ingroup CPUContext
1158 *  This routine switches from the run context to the heir context.
1159 *
1160 *  @param[in] run points to the context of the currently executing task
1161 *  @param[in] heir points to the context of the heir task
1162 *
1163 *  Port Specific Information:
1164 *
1165 *  XXX document implementation including references if appropriate
1166 */
1167void _CPU_Context_switch(
1168  Context_Control  *run,
1169  Context_Control  *heir
1170);
1171
1172/**
1173 *  @ingroup CPUContext
1174 *  This routine is generally used only to restart self in an
1175 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1176 *
1177 *  @param[in] new_context points to the context to be restored.
1178 *
1179 *  @note May be unnecessary to reload some registers.
1180 *
1181 *  Port Specific Information:
1182 *
1183 *  XXX document implementation including references if appropriate
1184 */
1185void _CPU_Context_restore(
1186  Context_Control *new_context
1187);
1188
1189/**
1190 *  @ingroup CPUContext
1191 *  This routine saves the floating point context passed to it.
1192 *
1193 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1194 *  point context area
1195 *
1196 *  @return on output @a *fp_context_ptr will contain the address that
1197 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1198 *
1199 *  Port Specific Information:
1200 *
1201 *  XXX document implementation including references if appropriate
1202 */
1203void _CPU_Context_save_fp(
1204  Context_Control_fp **fp_context_ptr
1205);
1206
1207/**
1208 *  @ingroup CPUContext
1209 *  This routine restores the floating point context passed to it.
1210 *
1211 *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
1212 *  point context area to restore
1213 *
1214 *  @return on output @a *fp_context_ptr will contain the address that
1215 *  should be used with @ref _CPU_Context_save_fp to save this context.
1216 *
1217 *  Port Specific Information:
1218 *
1219 *  XXX document implementation including references if appropriate
1220 */
1221void _CPU_Context_restore_fp(
1222  Context_Control_fp **fp_context_ptr
1223);
1224
1225/**
1226 *  @ingroup CPUEndian
1227 *  The following routine swaps the endian format of an unsigned int.
1228 *  It must be static because it is referenced indirectly.
1229 *
1230 *  This version will work on any processor, but if there is a better
1231 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1232 *
1233 *     swap least significant two bytes with 16-bit rotate
1234 *     swap upper and lower 16-bits
1235 *     swap most significant two bytes with 16-bit rotate
1236 *
1237 *  Some CPUs have special instructions which swap a 32-bit quantity in
1238 *  a single instruction (e.g. i486).  It is probably best to avoid
1239 *  an "endian swapping control bit" in the CPU.  One good reason is
1240 *  that interrupts would probably have to be disabled to ensure that
1241 *  an interrupt does not try to access the same "chunk" with the wrong
1242 *  endian.  Another good reason is that on some CPUs, the endian bit
1243 *  endianness for ALL fetches -- both code and data -- so the code
1244 *  will be fetched incorrectly.
1245 *
1246 *  @param[in] value is the value to be swapped
1247 *  @return the value after being endian swapped
1248 *
1249 *  Port Specific Information:
1250 *
1251 *  XXX document implementation including references if appropriate
1252 */
1253static inline uint32_t CPU_swap_u32(
1254  uint32_t value
1255)
1256{
1257  uint32_t byte1, byte2, byte3, byte4, swapped;
1258 
1259  byte4 = (value >> 24) & 0xff;
1260  byte3 = (value >> 16) & 0xff;
1261  byte2 = (value >> 8)  & 0xff;
1262  byte1 =  value        & 0xff;
1263 
1264  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1265  return swapped;
1266}
1267
1268/**
1269 *  @ingroup CPUEndian
1270 *  This routine swaps a 16 bir quantity.
1271 *
1272 *  @param[in] value is the value to be swapped
1273 *  @return the value after being endian swapped
1274 */
1275#define CPU_swap_u16( value ) \
1276  (((value&0xff) << 8) | ((value >> 8)&0xff))
1277
1278#ifdef __cplusplus
1279}
1280#endif
1281
1282#endif
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