source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 2f6108f9

4.115
Last change on this file since 2f6108f9 was 2f6108f9, checked in by Sebastian Huber <sebastian.huber@…>, on May 28, 2013 at 8:58:19 AM

smp: Simplify SMP initialization sequence

Delete bsp_smp_wait_for(). Other parts of the system work without
timeout, e.g. the spinlocks. Using a timeout here does not make the
system more robust.

Delete bsp_smp_cpu_state and replace it with Per_CPU_State. The
Per_CPU_State follows the Score naming conventions. Add
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state() functions to
change and observe states.

Use Per_CPU_State in Per_CPU_Control instead of the anonymous integer.

Add _CPU_Processor_event_broadcast() and _CPU_Processor_event_receive()
functions provided by the CPU port. Use these functions in
_Per_CPU_Change_state() and _Per_CPU_Wait_for_state().

Add prototype for _SMP_Send_message().

Delete RTEMS_BSP_SMP_FIRST_TASK message. The first context switch is
now performed in rtems_smp_secondary_cpu_initialize(). Issuing the
first context switch in the context of the inter-processor interrupt is
not possible on systems with a modern interrupt controller. Such an
interrupt controler usually requires a handshake protocol with interrupt
acknowledge and end of interrupt signals. A direct context switch in an
interrupt handler circumvents the interrupt processing epilogue and may
leave the system in an inconsistent state.

Release lock in rtems_smp_process_interrupt() even if no message was
delivered. This prevents deadlock of the system.

Simplify and format _SMP_Send_message(),
_SMP_Request_other_cores_to_perform_first_context_switch(),
_SMP_Request_other_cores_to_dispatch() and
_SMP_Request_other_cores_to_shutdown().

  • Property mode set to 100644
File size: 45.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 *
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 */
30
31#ifndef _RTEMS_SCORE_CPU_H
32#define _RTEMS_SCORE_CPU_H
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#include <rtems/score/types.h>
39#include <rtems/score/no_cpu.h>
40
41/* conditional compilation parameters */
42
43/**
44 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
45 *
46 * If TRUE, then they are inlined.
47 * If FALSE, then a subroutine call is made.
48 *
49 * This conditional is an example of the classic trade-off of size
50 * versus speed.  Inlining the call (TRUE) typically increases the
51 * size of RTEMS while speeding up the enabling of dispatching.
52 *
53 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
54 * only be 0 or 1 unless you are in an interrupt handler and that
55 * interrupt handler invokes the executive.]  When not inlined
56 * something calls @ref _Thread_Enable_dispatch which in turns calls
57 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
58 * one subroutine call is avoided entirely.
59 *
60 * Port Specific Information:
61 *
62 * XXX document implementation including references if appropriate
63 */
64#define CPU_INLINE_ENABLE_DISPATCH       FALSE
65
66/**
67 * Should the body of the search loops in _Thread_queue_Enqueue_priority
68 * be unrolled one time?  In unrolled each iteration of the loop examines
69 * two "nodes" on the chain being searched.  Otherwise, only one node
70 * is examined per iteration.
71 *
72 * If TRUE, then the loops are unrolled.
73 * If FALSE, then the loops are not unrolled.
74 *
75 * The primary factor in making this decision is the cost of disabling
76 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
77 * body of the loop.  On some CPUs, the flash is more expensive than
78 * one iteration of the loop body.  In this case, it might be desirable
79 * to unroll the loop.  It is important to note that on some CPUs, this
80 * code is the longest interrupt disable period in RTEMS.  So it is
81 * necessary to strike a balance when setting this parameter.
82 *
83 * Port Specific Information:
84 *
85 * XXX document implementation including references if appropriate
86 */
87#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
88
89/**
90 * Does RTEMS manage a dedicated interrupt stack in software?
91 *
92 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
93 * If FALSE, nothing is done.
94 *
95 * If the CPU supports a dedicated interrupt stack in hardware,
96 * then it is generally the responsibility of the BSP to allocate it
97 * and set it up.
98 *
99 * If the CPU does not support a dedicated interrupt stack, then
100 * the porter has two options: (1) execute interrupts on the
101 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
102 * interrupt stack.
103 *
104 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
107 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 * possible that both are FALSE for a particular CPU.  Although it
109 * is unclear what that would imply about the interrupt processing
110 * procedure on that CPU.
111 *
112 * Port Specific Information:
113 *
114 * XXX document implementation including references if appropriate
115 */
116#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
117
118/**
119 * Does the CPU follow the simple vectored interrupt model?
120 *
121 * If TRUE, then RTEMS allocates the vector table it internally manages.
122 * If FALSE, then the BSP is assumed to allocate and manage the vector
123 * table
124 *
125 * Port Specific Information:
126 *
127 * XXX document implementation including references if appropriate
128 */
129#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
130
131/**
132 * Does this CPU have hardware support for a dedicated interrupt stack?
133 *
134 * If TRUE, then it must be installed during initialization.
135 * If FALSE, then no installation is performed.
136 *
137 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
138 *
139 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
140 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
141 * possible that both are FALSE for a particular CPU.  Although it
142 * is unclear what that would imply about the interrupt processing
143 * procedure on that CPU.
144 *
145 * Port Specific Information:
146 *
147 * XXX document implementation including references if appropriate
148 */
149#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
150
151/**
152 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
153 *
154 * If TRUE, then the memory is allocated during initialization.
155 * If FALSE, then the memory is allocated during initialization.
156 *
157 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
158 *
159 * Port Specific Information:
160 *
161 * XXX document implementation including references if appropriate
162 */
163#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
164
165/**
166 * Does the RTEMS invoke the user's ISR with the vector number and
167 * a pointer to the saved interrupt frame (1) or just the vector
168 * number (0)?
169 *
170 * Port Specific Information:
171 *
172 * XXX document implementation including references if appropriate
173 */
174#define CPU_ISR_PASSES_FRAME_POINTER 0
175
176/**
177 * @def CPU_HARDWARE_FP
178 *
179 * Does the CPU have hardware floating point?
180 *
181 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
182 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
183 *
184 * If there is a FP coprocessor such as the i387 or mc68881, then
185 * the answer is TRUE.
186 *
187 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
188 * It indicates whether or not this CPU model has FP support.  For
189 * example, it would be possible to have an i386_nofp CPU model
190 * which set this to false to indicate that you have an i386 without
191 * an i387 and wish to leave floating point support out of RTEMS.
192 */
193
194/**
195 * @def CPU_SOFTWARE_FP
196 *
197 * Does the CPU have no hardware floating point and GCC provides a
198 * software floating point implementation which must be context
199 * switched?
200 *
201 * This feature conditional is used to indicate whether or not there
202 * is software implemented floating point that must be context
203 * switched.  The determination of whether or not this applies
204 * is very tool specific and the state saved/restored is also
205 * compiler specific.
206 *
207 * Port Specific Information:
208 *
209 * XXX document implementation including references if appropriate
210 */
211#if ( NO_CPU_HAS_FPU == 1 )
212#define CPU_HARDWARE_FP     TRUE
213#else
214#define CPU_HARDWARE_FP     FALSE
215#endif
216#define CPU_SOFTWARE_FP     FALSE
217
218/**
219 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
220 *
221 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
222 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
223 *
224 * So far, the only CPUs in which this option has been used are the
225 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
226 * gcc both implicitly used the floating point registers to perform
227 * integer multiplies.  Similarly, the PowerPC port of gcc has been
228 * seen to allocate floating point local variables and touch the FPU
229 * even when the flow through a subroutine (like vfprintf()) might
230 * not use floating point formats.
231 *
232 * If a function which you would not think utilize the FP unit DOES,
233 * then one can not easily predict which tasks will use the FP hardware.
234 * In this case, this option should be TRUE.
235 *
236 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
237 *
238 * Port Specific Information:
239 *
240 * XXX document implementation including references if appropriate
241 */
242#define CPU_ALL_TASKS_ARE_FP     TRUE
243
244/**
245 * Should the IDLE task have a floating point context?
246 *
247 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
248 * and it has a floating point context which is switched in and out.
249 * If FALSE, then the IDLE task does not have a floating point context.
250 *
251 * Setting this to TRUE negatively impacts the time required to preempt
252 * the IDLE task from an interrupt because the floating point context
253 * must be saved as part of the preemption.
254 *
255 * Port Specific Information:
256 *
257 * XXX document implementation including references if appropriate
258 */
259#define CPU_IDLE_TASK_IS_FP      FALSE
260
261/**
262 * Should the saving of the floating point registers be deferred
263 * until a context switch is made to another different floating point
264 * task?
265 *
266 * If TRUE, then the floating point context will not be stored until
267 * necessary.  It will remain in the floating point registers and not
268 * disturned until another floating point task is switched to.
269 *
270 * If FALSE, then the floating point context is saved when a floating
271 * point task is switched out and restored when the next floating point
272 * task is restored.  The state of the floating point registers between
273 * those two operations is not specified.
274 *
275 * If the floating point context does NOT have to be saved as part of
276 * interrupt dispatching, then it should be safe to set this to TRUE.
277 *
278 * Setting this flag to TRUE results in using a different algorithm
279 * for deciding when to save and restore the floating point context.
280 * The deferred FP switch algorithm minimizes the number of times
281 * the FP context is saved and restored.  The FP context is not saved
282 * until a context switch is made to another, different FP task.
283 * Thus in a system with only one FP task, the FP context will never
284 * be saved or restored.
285 *
286 * Port Specific Information:
287 *
288 * XXX document implementation including references if appropriate
289 */
290#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
291
292/**
293 * Does this port provide a CPU dependent IDLE task implementation?
294 *
295 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
296 * must be provided and is the default IDLE thread body instead of
297 * @ref _CPU_Thread_Idle_body.
298 *
299 * If FALSE, then use the generic IDLE thread body if the BSP does
300 * not provide one.
301 *
302 * This is intended to allow for supporting processors which have
303 * a low power or idle mode.  When the IDLE thread is executed, then
304 * the CPU can be powered down.
305 *
306 * The order of precedence for selecting the IDLE thread body is:
307 *
308 *   -#  BSP provided
309 *   -#  CPU dependent (if provided)
310 *   -#  generic (if no BSP and no CPU dependent)
311 *
312 * Port Specific Information:
313 *
314 * XXX document implementation including references if appropriate
315 */
316#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
317
318/**
319 * Does the stack grow up (toward higher addresses) or down
320 * (toward lower addresses)?
321 *
322 * If TRUE, then the grows upward.
323 * If FALSE, then the grows toward smaller addresses.
324 *
325 * Port Specific Information:
326 *
327 * XXX document implementation including references if appropriate
328 */
329#define CPU_STACK_GROWS_UP               TRUE
330
331/**
332 * The following is the variable attribute used to force alignment
333 * of critical RTEMS structures.  On some processors it may make
334 * sense to have these aligned on tighter boundaries than
335 * the minimum requirements of the compiler in order to have as
336 * much of the critical data area as possible in a cache line.
337 *
338 * The placement of this macro in the declaration of the variables
339 * is based on the syntactically requirements of the GNU C
340 * "__attribute__" extension.  For example with GNU C, use
341 * the following to force a structures to a 32 byte boundary.
342 *
343 *     __attribute__ ((aligned (32)))
344 *
345 * NOTE: Currently only the Priority Bit Map table uses this feature.
346 *       To benefit from using this, the data must be heavily
347 *       used so it will stay in the cache and used frequently enough
348 *       in the executive to justify turning this on.
349 *
350 * Port Specific Information:
351 *
352 * XXX document implementation including references if appropriate
353 */
354#define CPU_STRUCTURE_ALIGNMENT
355
356/**
357 * @defgroup CPUTimestamp Processor Dependent Timestamp Support
358 *
359 * This group assists in issues related to timestamp implementation.
360 *
361 * The port must choose exactly one of the following defines:
362 * - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
363 * - #define CPU_TIMESTAMP_USE_INT64 TRUE
364 * - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
365 *
366 * Performance of int64_t versus struct timespec
367 * =============================================
368 *
369 * On PowerPC/psim, inlined int64_t saves ~50 instructions on each
370 *   _Thread_Dispatch operation which results in a context switch.
371 *   This works out to be about 10% faster dispatches and 7.5% faster
372 *   blocking semaphore obtains.  The following numbers are in instructions
373 *   and from tm02 and tm26.
374 *
375 *                        timespec  int64  inlined int64
376 *   dispatch:              446      446      400
377 *   blocking sem obtain:   627      626      581
378 *
379 * On SPARC/sis, inlined int64_t shows the same percentage gains.
380 *   The following numbers are in microseconds and from tm02 and tm26.
381 *
382 *                        timespec  int64  inlined int64
383 *   dispatch:               59       61       53
384 *   blocking sem obtain:    98      100       92
385 *
386 * Inlining appears to have a tendency to increase the size of
387 *   some executables.
388 * Not inlining reduces the execution improvement but does not seem to
389 *   be an improvement on the PowerPC and SPARC. The struct timespec
390 *   and the executables with int64 not inlined are about the same size.
391 *
392 */
393/**@{**/
394
395/**
396 * Selects the timestamp implementation using struct timespec.
397 *
398 * Port Specific Information:
399 *
400 * XXX document implementation including references if appropriate
401 */
402#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
403
404/**
405 * Selects the timestamp implementation using int64_t and no inlined methods.
406 *
407 * Port Specific Information:
408 *
409 * XXX document implementation including references if appropriate
410 */
411#define CPU_TIMESTAMP_USE_INT64 TRUE
412
413/**
414 * Selects the timestamp implementation using int64_t and inlined methods.
415 *
416 * Port Specific Information:
417 *
418 * XXX document implementation including references if appropriate
419 */
420#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
421
422/** @} */
423
424/**
425 * @defgroup CPUEndian Processor Dependent Endianness Support
426 *
427 * This group assists in issues related to processor endianness.
428 *
429 */
430/**@{**/
431
432/**
433 * Define what is required to specify how the network to host conversion
434 * routines are handled.
435 *
436 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
437 * same values.
438 *
439 * @see CPU_LITTLE_ENDIAN
440 *
441 * Port Specific Information:
442 *
443 * XXX document implementation including references if appropriate
444 */
445#define CPU_BIG_ENDIAN                           TRUE
446
447/**
448 * Define what is required to specify how the network to host conversion
449 * routines are handled.
450 *
451 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
452 * same values.
453 *
454 * @see CPU_BIG_ENDIAN
455 *
456 * Port Specific Information:
457 *
458 * XXX document implementation including references if appropriate
459 */
460#define CPU_LITTLE_ENDIAN                        FALSE
461
462/** @} */
463
464/**
465 * @ingroup CPUInterrupt
466 *
467 * The following defines the number of bits actually used in the
468 * interrupt field of the task mode.  How those bits map to the
469 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
470 *
471 * Port Specific Information:
472 *
473 * XXX document implementation including references if appropriate
474 */
475#define CPU_MODES_INTERRUPT_MASK   0x00000001
476
477/*
478 *  Processor defined structures required for cpukit/score.
479 *
480 *  Port Specific Information:
481 *
482 *  XXX document implementation including references if appropriate
483 */
484
485/* may need to put some structures here.  */
486
487/**
488 * @defgroup CPUContext Processor Dependent Context Management
489 *
490 * From the highest level viewpoint, there are 2 types of context to save.
491 *
492 *    -# Interrupt registers to save
493 *    -# Task level registers to save
494 *
495 * Since RTEMS handles integer and floating point contexts separately, this
496 * means we have the following 3 context items:
497 *
498 *    -# task level context stuff::  Context_Control
499 *    -# floating point task stuff:: Context_Control_fp
500 *    -# special interrupt level context :: CPU_Interrupt_frame
501 *
502 * On some processors, it is cost-effective to save only the callee
503 * preserved registers during a task context switch.  This means
504 * that the ISR code needs to save those registers which do not
505 * persist across function calls.  It is not mandatory to make this
506 * distinctions between the caller/callee saves registers for the
507 * purpose of minimizing context saved during task switch and on interrupts.
508 * If the cost of saving extra registers is minimal, simplicity is the
509 * choice.  Save the same context on interrupt entry as for tasks in
510 * this case.
511 *
512 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
513 * care should be used in designing the context area.
514 *
515 * On some CPUs with hardware floating point support, the Context_Control_fp
516 * structure will not be used or it simply consist of an array of a
517 * fixed number of bytes.   This is done when the floating point context
518 * is dumped by a "FP save context" type instruction and the format
519 * is not really defined by the CPU.  In this case, there is no need
520 * to figure out the exact format -- only the size.  Of course, although
521 * this is enough information for RTEMS, it is probably not enough for
522 * a debugger such as gdb.  But that is another problem.
523 *
524 * Port Specific Information:
525 *
526 * XXX document implementation including references if appropriate
527 *
528 */
529/**@{**/
530
531/**
532 * @ingroup Management
533 * This defines the minimal set of integer and processor state registers
534 * that must be saved during a voluntary context switch from one thread
535 * to another.
536 */
537typedef struct {
538    /**
539     * This field is a hint that a port will have a number of integer
540     * registers that need to be saved at a context switch.
541     */
542    uint32_t   some_integer_register;
543    /**
544     * This field is a hint that a port will have a number of system
545     * registers that need to be saved at a context switch.
546     */
547    uint32_t   some_system_register;
548
549    /**
550     * This field is a hint that a port will have a register that
551     * is the stack pointer.
552     */
553    uint32_t   stack_pointer;
554} Context_Control;
555
556/**
557 * @ingroup Management
558 *
559 * This macro returns the stack pointer associated with @a _context.
560 *
561 * @param[in] _context is the thread context area to access
562 *
563 * @return This method returns the stack pointer.
564 */
565#define _CPU_Context_Get_SP( _context ) \
566  (_context)->stack_pointer
567
568/**
569 * @ingroup Management
570 *
571 * This defines the complete set of floating point registers that must
572 * be saved during any context switch from one thread to another.
573 */
574typedef struct {
575    /** FPU registers are listed here */
576    double      some_float_register;
577} Context_Control_fp;
578
579/**
580 * @ingroup Management
581 *
582 * This defines the set of integer and processor state registers that must
583 * be saved during an interrupt.  This set does not include any which are
584 * in @ref Context_Control.
585 */
586typedef struct {
587    /**
588     * This field is a hint that a port will have a number of integer
589     * registers that need to be saved when an interrupt occurs or
590     * when a context switch occurs at the end of an ISR.
591     */
592    uint32_t   special_interrupt_register;
593} CPU_Interrupt_frame;
594
595/**
596 * This variable is optional.  It is used on CPUs on which it is difficult
597 * to generate an "uninitialized" FP context.  It is filled in by
598 * @ref _CPU_Initialize and copied into the task's FP context area during
599 * @ref _CPU_Context_Initialize.
600 *
601 * Port Specific Information:
602 *
603 * XXX document implementation including references if appropriate
604 */
605SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
606
607/** @} */
608
609/**
610 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
611 *
612 * On some CPUs, RTEMS supports a software managed interrupt stack.
613 * This stack is allocated by the Interrupt Manager and the switch
614 * is performed in @ref _ISR_Handler.  These variables contain pointers
615 * to the lowest and highest addresses in the chunk of memory allocated
616 * for the interrupt stack.  Since it is unknown whether the stack
617 * grows up or down (in general), this give the CPU dependent
618 * code the option of picking the version it wants to use.
619 *
620 * NOTE: These two variables are required if the macro
621 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
622 *
623 * Port Specific Information:
624 *
625 * XXX document implementation including references if appropriate
626 */
627
628/*
629 *  Nothing prevents the porter from declaring more CPU specific variables.
630 *
631 *  Port Specific Information:
632 *
633 *  XXX document implementation including references if appropriate
634 */
635
636/* XXX: if needed, put more variables here */
637
638/**
639 * @ingroup CPUContext
640 *
641 * The size of the floating point context area.  On some CPUs this
642 * will not be a "sizeof" because the format of the floating point
643 * area is not defined -- only the size is.  This is usually on
644 * CPUs with a "floating point save context" instruction.
645 *
646 * Port Specific Information:
647 *
648 * XXX document implementation including references if appropriate
649 */
650#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
651
652/**
653 * Amount of extra stack (above minimum stack size) required by
654 * MPCI receive server thread.  Remember that in a multiprocessor
655 * system this thread must exist and be able to process all directives.
656 *
657 * Port Specific Information:
658 *
659 * XXX document implementation including references if appropriate
660 */
661#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
662
663/**
664 * @ingroup CPUInterrupt
665 *
666 * This defines the number of entries in the @ref _ISR_Vector_table managed
667 * by RTEMS.
668 *
669 * Port Specific Information:
670 *
671 * XXX document implementation including references if appropriate
672 */
673#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
674
675/**
676 * @ingroup CPUInterrupt
677 *
678 * This defines the highest interrupt vector number for this port.
679 */
680#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
681
682/**
683 * @ingroup CPUInterrupt
684 *
685 * This is defined if the port has a special way to report the ISR nesting
686 * level.  Most ports maintain the variable @a _ISR_Nest_level.
687 */
688#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
689
690/**
691 * @ingroup CPUContext
692 *
693 * Should be large enough to run all RTEMS tests.  This ensures
694 * that a "reasonable" small application should not have any problems.
695 *
696 * Port Specific Information:
697 *
698 * XXX document implementation including references if appropriate
699 */
700#define CPU_STACK_MINIMUM_SIZE          (1024*4)
701
702/**
703 * Size of a pointer.
704 *
705 * This must be an integer literal that can be used by the assembler.  This
706 * value will be used to calculate offsets of structure members.  These
707 * offsets will be used in assembler code.
708 */
709#define CPU_SIZEOF_POINTER         4
710
711/**
712 * CPU's worst alignment requirement for data types on a byte boundary.  This
713 * alignment does not take into account the requirements for the stack.
714 *
715 * Port Specific Information:
716 *
717 * XXX document implementation including references if appropriate
718 */
719#define CPU_ALIGNMENT              8
720
721/**
722 * This number corresponds to the byte alignment requirement for the
723 * heap handler.  This alignment requirement may be stricter than that
724 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
725 * common for the heap to follow the same alignment requirement as
726 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
727 * the heap, then this should be set to @ref CPU_ALIGNMENT.
728 *
729 * NOTE:  This does not have to be a power of 2 although it should be
730 *        a multiple of 2 greater than or equal to 2.  The requirement
731 *        to be a multiple of 2 is because the heap uses the least
732 *        significant field of the front and back flags to indicate
733 *        that a block is in use or free.  So you do not want any odd
734 *        length blocks really putting length data in that bit.
735 *
736 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
737 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
738 *        elements allocated from the heap meet all restrictions.
739 *
740 * Port Specific Information:
741 *
742 * XXX document implementation including references if appropriate
743 */
744#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
745
746/**
747 * This number corresponds to the byte alignment requirement for memory
748 * buffers allocated by the partition manager.  This alignment requirement
749 * may be stricter than that for the data types alignment specified by
750 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
751 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
752 * strict enough for the partition, then this should be set to
753 * @ref CPU_ALIGNMENT.
754 *
755 * NOTE:  This does not have to be a power of 2.  It does have to
756 *        be greater or equal to than @ref CPU_ALIGNMENT.
757 *
758 * Port Specific Information:
759 *
760 * XXX document implementation including references if appropriate
761 */
762#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
763
764/**
765 * This number corresponds to the byte alignment requirement for the
766 * stack.  This alignment requirement may be stricter than that for the
767 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
768 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
769 * set to 0.
770 *
771 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
772 *
773 * Port Specific Information:
774 *
775 * XXX document implementation including references if appropriate
776 */
777#define CPU_STACK_ALIGNMENT        0
778
779/*
780 *  ISR handler macros
781 */
782
783/**
784 * @ingroup CPUInterrupt
785 *
786 * Support routine to initialize the RTEMS vector table after it is allocated.
787 *
788 * Port Specific Information:
789 *
790 * XXX document implementation including references if appropriate
791 */
792#define _CPU_Initialize_vectors()
793
794/**
795 * @ingroup CPUInterrupt
796 *
797 * Disable all interrupts for an RTEMS critical section.  The previous
798 * level is returned in @a _isr_cookie.
799 *
800 * @param[out] _isr_cookie will contain the previous level cookie
801 *
802 * Port Specific Information:
803 *
804 * XXX document implementation including references if appropriate
805 */
806#define _CPU_ISR_Disable( _isr_cookie ) \
807  { \
808    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
809  }
810
811/**
812 * @ingroup CPUInterrupt
813 *
814 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
815 * This indicates the end of an RTEMS critical section.  The parameter
816 * @a _isr_cookie is not modified.
817 *
818 * @param[in] _isr_cookie contain the previous level cookie
819 *
820 * Port Specific Information:
821 *
822 * XXX document implementation including references if appropriate
823 */
824#define _CPU_ISR_Enable( _isr_cookie )  \
825  { \
826  }
827
828/**
829 * @ingroup CPUInterrupt
830 *
831 * This temporarily restores the interrupt to @a _isr_cookie before immediately
832 * disabling them again.  This is used to divide long RTEMS critical
833 * sections into two or more parts.  The parameter @a _isr_cookie is not
834 * modified.
835 *
836 * @param[in] _isr_cookie contain the previous level cookie
837 *
838 * Port Specific Information:
839 *
840 * XXX document implementation including references if appropriate
841 */
842#define _CPU_ISR_Flash( _isr_cookie ) \
843  { \
844  }
845
846/**
847 * @ingroup CPUInterrupt
848 *
849 * This routine and @ref _CPU_ISR_Get_level
850 * Map the interrupt level in task mode onto the hardware that the CPU
851 * actually provides.  Currently, interrupt levels which do not
852 * map onto the CPU in a generic fashion are undefined.  Someday,
853 * it would be nice if these were "mapped" by the application
854 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
855 * 8 - 255 would be available for bsp/application specific meaning.
856 * This could be used to manage a programmable interrupt controller
857 * via the rtems_task_mode directive.
858 *
859 * Port Specific Information:
860 *
861 * XXX document implementation including references if appropriate
862 */
863#define _CPU_ISR_Set_level( new_level ) \
864  { \
865  }
866
867/**
868 * @ingroup CPUInterrupt
869 *
870 * Return the current interrupt disable level for this task in
871 * the format used by the interrupt level portion of the task mode.
872 *
873 * NOTE: This routine usually must be implemented as a subroutine.
874 *
875 * Port Specific Information:
876 *
877 * XXX document implementation including references if appropriate
878 */
879uint32_t   _CPU_ISR_Get_level( void );
880
881/* end of ISR handler macros */
882
883/* Context handler macros */
884
885/**
886 *  @ingroup CPUContext
887 *
888 * Initialize the context to a state suitable for starting a
889 * task after a context restore operation.  Generally, this
890 * involves:
891 *
892 *    - setting a starting address
893 *    - preparing the stack
894 *    - preparing the stack and frame pointers
895 *    - setting the proper interrupt level in the context
896 *    - initializing the floating point context
897 *
898 * This routine generally does not set any unnecessary register
899 * in the context.  The state of the "general data" registers is
900 * undefined at task start time.
901 *
902 * @param[in] _the_context is the context structure to be initialized
903 * @param[in] _stack_base is the lowest physical address of this task's stack
904 * @param[in] _size is the size of this task's stack
905 * @param[in] _isr is the interrupt disable level
906 * @param[in] _entry_point is the thread's entry point.  This is
907 *        always @a _Thread_Handler
908 * @param[in] _is_fp is TRUE if the thread is to be a floating
909 *       point thread.  This is typically only used on CPUs where the
910 *       FPU may be easily disabled by software such as on the SPARC
911 *       where the PSR contains an enable FPU bit.
912 *
913 * Port Specific Information:
914 *
915 * XXX document implementation including references if appropriate
916 */
917#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
918                                 _isr, _entry_point, _is_fp ) \
919  { \
920  }
921
922/**
923 * This routine is responsible for somehow restarting the currently
924 * executing task.  If you are lucky, then all that is necessary
925 * is restoring the context.  Otherwise, there will need to be
926 * a special assembly routine which does something special in this
927 * case.  For many ports, simply adding a label to the restore path
928 * of @ref _CPU_Context_switch will work.  On other ports, it may be
929 * possibly to load a few arguments and jump to the restore path. It will
930 * not work if restarting self conflicts with the stack frame
931 * assumptions of restoring a context.
932 *
933 * Port Specific Information:
934 *
935 * XXX document implementation including references if appropriate
936 */
937#define _CPU_Context_Restart_self( _the_context ) \
938   _CPU_Context_restore( (_the_context) );
939
940/**
941 * @ingroup CPUContext
942 *
943 * The purpose of this macro is to allow the initial pointer into
944 * a floating point context area (used to save the floating point
945 * context) to be at an arbitrary place in the floating point
946 *context area.
947 *
948 * This is necessary because some FP units are designed to have
949 * their context saved as a stack which grows into lower addresses.
950 * Other FP units can be saved by simply moving registers into offsets
951 * from the base of the context area.  Finally some FP units provide
952 * a "dump context" instruction which could fill in from high to low
953 * or low to high based on the whim of the CPU designers.
954 *
955 * @param[in] _base is the lowest physical address of the floating point
956 *        context area
957 * @param[in] _offset is the offset into the floating point area
958 *
959 * Port Specific Information:
960 *
961 * XXX document implementation including references if appropriate
962 */
963#define _CPU_Context_Fp_start( _base, _offset ) \
964   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
965
966/**
967 * This routine initializes the FP context area passed to it to.
968 * There are a few standard ways in which to initialize the
969 * floating point context.  The code included for this macro assumes
970 * that this is a CPU in which a "initial" FP context was saved into
971 * @a _CPU_Null_fp_context and it simply copies it to the destination
972 * context passed to it.
973 *
974 * Other floating point context save/restore models include:
975 *   -# not doing anything, and
976 *   -# putting a "null FP status word" in the correct place in the FP context.
977 *
978 * @param[in] _destination is the floating point context area
979 *
980 * Port Specific Information:
981 *
982 * XXX document implementation including references if appropriate
983 */
984#define _CPU_Context_Initialize_fp( _destination ) \
985  { \
986   *(*(_destination)) = _CPU_Null_fp_context; \
987  }
988
989/* end of Context handler macros */
990
991/* Fatal Error manager macros */
992
993/**
994 * This routine copies _error into a known place -- typically a stack
995 * location or a register, optionally disables interrupts, and
996 * halts/stops the CPU.
997 *
998 * Port Specific Information:
999 *
1000 * XXX document implementation including references if appropriate
1001 */
1002#define _CPU_Fatal_halt( _error ) \
1003  { \
1004  }
1005
1006/* end of Fatal Error manager macros */
1007
1008/* Bitfield handler macros */
1009
1010/**
1011 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1012 *
1013 * This set of routines are used to implement fast searches for
1014 * the most important ready task.
1015 *
1016 */
1017/**@{**/
1018
1019/**
1020 * This definition is set to TRUE if the port uses the generic bitfield
1021 * manipulation implementation.
1022 */
1023#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1024
1025/**
1026 * This definition is set to TRUE if the port uses the data tables provided
1027 * by the generic bitfield manipulation implementation.
1028 * This can occur when actually using the generic bitfield manipulation
1029 * implementation or when implementing the same algorithm in assembly
1030 * language for improved performance.  It is unlikely that a port will use
1031 * the data if it has a bitfield scan instruction.
1032 */
1033#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1034
1035/**
1036 * This routine sets @a _output to the bit number of the first bit
1037 * set in @a _value.  @a _value is of CPU dependent type
1038 * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
1039 * wide although only the 16 least significant bits will be used.
1040 *
1041 * There are a number of variables in using a "find first bit" type
1042 * instruction.
1043 *
1044 *   -# What happens when run on a value of zero?
1045 *   -# Bits may be numbered from MSB to LSB or vice-versa.
1046 *   -# The numbering may be zero or one based.
1047 *   -# The "find first bit" instruction may search from MSB or LSB.
1048 *
1049 * RTEMS guarantees that (1) will never happen so it is not a concern.
1050 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1051 * @ref _CPU_Priority_bits_index.  These three form a set of routines
1052 * which must logically operate together.  Bits in the _value are
1053 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
1054 * The basic major and minor values calculated by @ref _Priority_Major
1055 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1056 * to properly range between the values returned by the "find first bit"
1057 * instruction.  This makes it possible for @ref _Priority_Get_highest to
1058 * calculate the major and directly index into the minor table.
1059 * This mapping is necessary to ensure that 0 (a high priority major/minor)
1060 * is the first bit found.
1061 *
1062 * This entire "find first bit" and mapping process depends heavily
1063 * on the manner in which a priority is broken into a major and minor
1064 * components with the major being the 4 MSB of a priority and minor
1065 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1066 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1067 * to the lowest priority.
1068 *
1069 * If your CPU does not have a "find first bit" instruction, then
1070 * there are ways to make do without it.  Here are a handful of ways
1071 * to implement this in software:
1072 *
1073@verbatim
1074      - a series of 16 bit test instructions
1075      - a "binary search using if's"
1076      - _number = 0
1077        if _value > 0x00ff
1078          _value >>=8
1079          _number = 8;
1080
1081        if _value > 0x0000f
1082          _value >=8
1083          _number += 4
1084
1085        _number += bit_set_table[ _value ]
1086@endverbatim
1087
1088 *   where bit_set_table[ 16 ] has values which indicate the first
1089 *     bit set
1090 *
1091 * @param[in] _value is the value to be scanned
1092 * @param[in] _output is the first bit set
1093 *
1094 * Port Specific Information:
1095 *
1096 * XXX document implementation including references if appropriate
1097 */
1098
1099#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1100#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1101  { \
1102    (_output) = 0;   /* do something to prevent warnings */ \
1103  }
1104#endif
1105
1106/** @} */
1107
1108/* end of Bitfield handler macros */
1109
1110/**
1111 * This routine builds the mask which corresponds to the bit fields
1112 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1113 * for that routine.
1114 *
1115 * Port Specific Information:
1116 *
1117 * XXX document implementation including references if appropriate
1118 */
1119#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1120
1121#define _CPU_Priority_Mask( _bit_number ) \
1122  ( 1 << (_bit_number) )
1123
1124#endif
1125
1126/**
1127 * @ingroup CPUBitfield
1128 *
1129 * This routine translates the bit numbers returned by
1130 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1131 * a major or minor component of a priority.  See the discussion
1132 * for that routine.
1133 *
1134 * @param[in] _priority is the major or minor number to translate
1135 *
1136 * Port Specific Information:
1137 *
1138 * XXX document implementation including references if appropriate
1139 */
1140#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1141
1142#define _CPU_Priority_bits_index( _priority ) \
1143  (_priority)
1144
1145#endif
1146
1147/* end of Priority handler macros */
1148
1149/* functions */
1150
1151/**
1152 * This routine performs CPU dependent initialization.
1153 *
1154 * Port Specific Information:
1155 *
1156 * XXX document implementation including references if appropriate
1157 */
1158void _CPU_Initialize(void);
1159
1160/**
1161 * @ingroup CPUInterrupt
1162 *
1163 * This routine installs a "raw" interrupt handler directly into the
1164 * processor's vector table.
1165 *
1166 * @param[in] vector is the vector number
1167 * @param[in] new_handler is the raw ISR handler to install
1168 * @param[in] old_handler is the previously installed ISR Handler
1169 *
1170 * Port Specific Information:
1171 *
1172 * XXX document implementation including references if appropriate
1173 */
1174void _CPU_ISR_install_raw_handler(
1175  uint32_t    vector,
1176  proc_ptr    new_handler,
1177  proc_ptr   *old_handler
1178);
1179
1180/**
1181 * @ingroup CPUInterrupt
1182 *
1183 * This routine installs an interrupt vector.
1184 *
1185 * @param[in] vector is the vector number
1186 * @param[in] new_handler is the RTEMS ISR handler to install
1187 * @param[in] old_handler is the previously installed ISR Handler
1188 *
1189 * Port Specific Information:
1190 *
1191 * XXX document implementation including references if appropriate
1192 */
1193void _CPU_ISR_install_vector(
1194  uint32_t    vector,
1195  proc_ptr    new_handler,
1196  proc_ptr   *old_handler
1197);
1198
1199/**
1200 * @ingroup CPUInterrupt
1201 * This routine installs the hardware interrupt stack pointer.
1202 *
1203 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1204 *        is TRUE.
1205 *
1206 * Port Specific Information:
1207 *
1208 * XXX document implementation including references if appropriate
1209 */
1210void _CPU_Install_interrupt_stack( void );
1211
1212/**
1213 * This routine is the CPU dependent IDLE thread body.
1214 *
1215 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1216 *         is TRUE.
1217 *
1218 * Port Specific Information:
1219 *
1220 * XXX document implementation including references if appropriate
1221 */
1222void *_CPU_Thread_Idle_body( uintptr_t ignored );
1223
1224/**
1225 * @ingroup CPUContext
1226 *
1227 * This routine switches from the run context to the heir context.
1228 *
1229 * @param[in] run points to the context of the currently executing task
1230 * @param[in] heir points to the context of the heir task
1231 *
1232 * Port Specific Information:
1233 *
1234 * XXX document implementation including references if appropriate
1235 */
1236void _CPU_Context_switch(
1237  Context_Control  *run,
1238  Context_Control  *heir
1239);
1240
1241/**
1242 * @ingroup CPUContext
1243 *
1244 * This routine is generally used only to restart self in an
1245 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1246 *
1247 * @param[in] new_context points to the context to be restored.
1248 *
1249 * NOTE: May be unnecessary to reload some registers.
1250 *
1251 * Port Specific Information:
1252 *
1253 * XXX document implementation including references if appropriate
1254 */
1255void _CPU_Context_restore(
1256  Context_Control *new_context
1257) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1258
1259/**
1260 * @ingroup CPUContext
1261 *
1262 * This routine saves the floating point context passed to it.
1263 *
1264 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1265 * point context area
1266 *
1267 * @return on output @a *fp_context_ptr will contain the address that
1268 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1269 *
1270 * Port Specific Information:
1271 *
1272 * XXX document implementation including references if appropriate
1273 */
1274void _CPU_Context_save_fp(
1275  Context_Control_fp **fp_context_ptr
1276);
1277
1278/**
1279 * @ingroup CPUContext
1280 *
1281 * This routine restores the floating point context passed to it.
1282 *
1283 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1284 * point context area to restore
1285 *
1286 * @return on output @a *fp_context_ptr will contain the address that
1287 * should be used with @ref _CPU_Context_save_fp to save this context.
1288 *
1289 * Port Specific Information:
1290 *
1291 * XXX document implementation including references if appropriate
1292 */
1293void _CPU_Context_restore_fp(
1294  Context_Control_fp **fp_context_ptr
1295);
1296
1297/**
1298 * @ingroup CPUContext
1299 *
1300 * @brief Clobbers all volatile registers with values derived from the pattern
1301 * parameter.
1302 *
1303 * This function is used only in test sptests/spcontext01.
1304 *
1305 * @param[in] pattern Pattern used to generate distinct register values.
1306 *
1307 * @see _CPU_Context_validate().
1308 */
1309void _CPU_Context_volatile_clobber( uintptr_t pattern );
1310
1311/**
1312 * @ingroup CPUContext
1313 *
1314 * @brief Initializes and validates the CPU context with values derived from
1315 * the pattern parameter.
1316 *
1317 * This function will not return if the CPU context remains consistent.  In
1318 * case this function returns the CPU port is broken.
1319 *
1320 * This function is used only in test sptests/spcontext01.
1321 *
1322 * @param[in] pattern Pattern used to generate distinct register values.
1323 *
1324 * @see _CPU_Context_volatile_clobber().
1325 */
1326void _CPU_Context_validate( uintptr_t pattern );
1327
1328/**
1329 * @brief The set of registers that specifies the complete processor state.
1330 *
1331 * The CPU exception frame may be available in fatal error conditions like for
1332 * example illegal opcodes, instruction fetch errors, or data access errors.
1333 *
1334 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1335 * rtems_exception_frame_print().
1336 */
1337typedef struct {
1338  uint32_t processor_state_register;
1339  uint32_t integer_registers [1];
1340  double float_registers [1];
1341} CPU_Exception_frame;
1342
1343/**
1344 * @brief Prints the exception frame via printk().
1345 *
1346 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1347 */
1348void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1349
1350/**
1351 * @ingroup CPUEndian
1352 *
1353 * The following routine swaps the endian format of an unsigned int.
1354 * It must be static because it is referenced indirectly.
1355 *
1356 * This version will work on any processor, but if there is a better
1357 * way for your CPU PLEASE use it.  The most common way to do this is to:
1358 *
1359 *    swap least significant two bytes with 16-bit rotate
1360 *    swap upper and lower 16-bits
1361 *    swap most significant two bytes with 16-bit rotate
1362 *
1363 * Some CPUs have special instructions which swap a 32-bit quantity in
1364 * a single instruction (e.g. i486).  It is probably best to avoid
1365 * an "endian swapping control bit" in the CPU.  One good reason is
1366 * that interrupts would probably have to be disabled to ensure that
1367 * an interrupt does not try to access the same "chunk" with the wrong
1368 * endian.  Another good reason is that on some CPUs, the endian bit
1369 * endianness for ALL fetches -- both code and data -- so the code
1370 * will be fetched incorrectly.
1371 *
1372 * @param[in] value is the value to be swapped
1373 * @return the value after being endian swapped
1374 *
1375 * Port Specific Information:
1376 *
1377 * XXX document implementation including references if appropriate
1378 */
1379static inline uint32_t CPU_swap_u32(
1380  uint32_t value
1381)
1382{
1383  uint32_t byte1, byte2, byte3, byte4, swapped;
1384
1385  byte4 = (value >> 24) & 0xff;
1386  byte3 = (value >> 16) & 0xff;
1387  byte2 = (value >> 8)  & 0xff;
1388  byte1 =  value        & 0xff;
1389
1390  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1391  return swapped;
1392}
1393
1394/**
1395 * @ingroup CPUEndian
1396 *
1397 * This routine swaps a 16 bir quantity.
1398 *
1399 * @param[in] value is the value to be swapped
1400 * @return the value after being endian swapped
1401 */
1402#define CPU_swap_u16( value ) \
1403  (((value&0xff) << 8) | ((value >> 8)&0xff))
1404
1405#ifdef RTEMS_SMP
1406  /**
1407   * @brief Broadcasts a processor event.
1408   *
1409   * Some architectures provide a low-level synchronization primitive for
1410   * processors in a multi-processor environment.  Processors waiting for this
1411   * event may go into a low-power state and stop generating system bus
1412   * transactions.  This function must ensure that preceding store operations
1413   * can be observed by other processors.
1414   *
1415   * @see _CPU_Processor_event_receive().
1416   */
1417  static inline void _CPU_Processor_event_broadcast( void )
1418  {
1419    __asm__ volatile ( "" : : : "memory" );
1420  }
1421
1422  /**
1423   * @brief Receives a processor event.
1424   *
1425   * This function will wait for the processor event and may wait forever if no
1426   * such event arrives.
1427   *
1428   * @see _CPU_Processor_event_broadcast().
1429   */
1430  static inline void _CPU_Processor_event_receive( void )
1431  {
1432    __asm__ volatile ( "" : : : "memory" );
1433  }
1434#endif
1435
1436#ifdef __cplusplus
1437}
1438#endif
1439
1440#endif
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