source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 14c8ef9

4.104.114.84.95
Last change on this file since 14c8ef9 was 14c8ef9, checked in by Joel Sherrill <joel.sherrill@…>, on 04/03/02 at 14:05:43

2001-04-03 Joel Sherrill <joel@…>

  • Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
  • rtems/score/no_cputypes.h: Removed.
  • rtems/score/types.h: New file via CVS magic.
  • Makefile.am, rtems/score/cpu.h: Account for name change.
  • Property mode set to 100644
File size: 35.2 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the XXX
4 *  processor.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/no_cpu.h>            /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/types.h>
26#endif
27
28/* conditional compilation parameters */
29
30/*
31 *  Should the calls to _Thread_Enable_dispatch be inlined?
32 *
33 *  If TRUE, then they are inlined.
34 *  If FALSE, then a subroutine call is made.
35 *
36 *  Basically this is an example of the classic trade-off of size
37 *  versus speed.  Inlining the call (TRUE) typically increases the
38 *  size of RTEMS while speeding up the enabling of dispatching.
39 *  [NOTE: In general, the _Thread_Dispatch_disable_level will
40 *  only be 0 or 1 unless you are in an interrupt handler and that
41 *  interrupt handler invokes the executive.]  When not inlined
42 *  something calls _Thread_Enable_dispatch which in turns calls
43 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
44 *  one subroutine call is avoided entirely.]
45 *
46 *  NO_CPU Specific Information:
47 *
48 *  XXX document implementation including references if appropriate
49 */
50
51#define CPU_INLINE_ENABLE_DISPATCH       FALSE
52
53/*
54 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
55 *  be unrolled one time?  In unrolled each iteration of the loop examines
56 *  two "nodes" on the chain being searched.  Otherwise, only one node
57 *  is examined per iteration.
58 *
59 *  If TRUE, then the loops are unrolled.
60 *  If FALSE, then the loops are not unrolled.
61 *
62 *  The primary factor in making this decision is the cost of disabling
63 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
64 *  body of the loop.  On some CPUs, the flash is more expensive than
65 *  one iteration of the loop body.  In this case, it might be desirable
66 *  to unroll the loop.  It is important to note that on some CPUs, this
67 *  code is the longest interrupt disable period in RTEMS.  So it is
68 *  necessary to strike a balance when setting this parameter.
69 *
70 *  NO_CPU Specific Information:
71 *
72 *  XXX document implementation including references if appropriate
73 */
74
75#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
76
77/*
78 *  Does RTEMS manage a dedicated interrupt stack in software?
79 *
80 *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
81 *  If FALSE, nothing is done.
82 *
83 *  If the CPU supports a dedicated interrupt stack in hardware,
84 *  then it is generally the responsibility of the BSP to allocate it
85 *  and set it up.
86 *
87 *  If the CPU does not support a dedicated interrupt stack, then
88 *  the porter has two options: (1) execute interrupts on the
89 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
90 *  interrupt stack.
91 *
92 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
93 *
94 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
95 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
96 *  possible that both are FALSE for a particular CPU.  Although it
97 *  is unclear what that would imply about the interrupt processing
98 *  procedure on that CPU.
99 *
100 *  NO_CPU Specific Information:
101 *
102 *  XXX document implementation including references if appropriate
103 */
104
105#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
106
107/*
108 *  Does this CPU have hardware support for a dedicated interrupt stack?
109 *
110 *  If TRUE, then it must be installed during initialization.
111 *  If FALSE, then no installation is performed.
112 *
113 *  If this is TRUE, CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
114 *
115 *  Only one of CPU_HAS_SOFTWARE_INTERRUPT_STACK and
116 *  CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
117 *  possible that both are FALSE for a particular CPU.  Although it
118 *  is unclear what that would imply about the interrupt processing
119 *  procedure on that CPU.
120 *
121 *  NO_CPU Specific Information:
122 *
123 *  XXX document implementation including references if appropriate
124 */
125
126#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
127
128/*
129 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
130 *
131 *  If TRUE, then the memory is allocated during initialization.
132 *  If FALSE, then the memory is allocated during initialization.
133 *
134 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
135 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
136 *
137 *  NO_CPU Specific Information:
138 *
139 *  XXX document implementation including references if appropriate
140 */
141
142#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
143
144/*
145 *  Does the RTEMS invoke the user's ISR with the vector number and
146 *  a pointer to the saved interrupt frame (1) or just the vector
147 *  number (0)?
148 *
149 *  NO_CPU Specific Information:
150 *
151 *  XXX document implementation including references if appropriate
152 */
153
154#define CPU_ISR_PASSES_FRAME_POINTER 0
155
156/*
157 *  Does the CPU have hardware floating point?
158 *
159 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
160 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
161 *
162 *  If there is a FP coprocessor such as the i387 or mc68881, then
163 *  the answer is TRUE.
164 *
165 *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
166 *  It indicates whether or not this CPU model has FP support.  For
167 *  example, it would be possible to have an i386_nofp CPU model
168 *  which set this to false to indicate that you have an i386 without
169 *  an i387 and wish to leave floating point support out of RTEMS.
170 *
171 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
172 *  is software implemented floating point that must be context
173 *  switched.  The determination of whether or not this applies
174 *  is very tool specific and the state saved/restored is also
175 *  compiler specific.
176 *
177 *  NO_CPU Specific Information:
178 *
179 *  XXX document implementation including references if appropriate
180 */
181
182#if ( NO_CPU_HAS_FPU == 1 )
183#define CPU_HARDWARE_FP     TRUE
184#else
185#define CPU_HARDWARE_FP     FALSE
186#endif
187#define CPU_SOFTWARE_FP     FALSE
188
189/*
190 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
191 *
192 *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
193 *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
194 *
195 *  So far, the only CPU in which this option has been used is the
196 *  HP PA-RISC.  The HP C compiler and gcc both implicitly use the
197 *  floating point registers to perform integer multiplies.  If
198 *  a function which you would not think utilize the FP unit DOES,
199 *  then one can not easily predict which tasks will use the FP hardware.
200 *  In this case, this option should be TRUE.
201 *
202 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
203 *
204 *  NO_CPU Specific Information:
205 *
206 *  XXX document implementation including references if appropriate
207 */
208
209#define CPU_ALL_TASKS_ARE_FP     TRUE
210
211/*
212 *  Should the IDLE task have a floating point context?
213 *
214 *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
215 *  and it has a floating point context which is switched in and out.
216 *  If FALSE, then the IDLE task does not have a floating point context.
217 *
218 *  Setting this to TRUE negatively impacts the time required to preempt
219 *  the IDLE task from an interrupt because the floating point context
220 *  must be saved as part of the preemption.
221 *
222 *  NO_CPU Specific Information:
223 *
224 *  XXX document implementation including references if appropriate
225 */
226
227#define CPU_IDLE_TASK_IS_FP      FALSE
228
229/*
230 *  Should the saving of the floating point registers be deferred
231 *  until a context switch is made to another different floating point
232 *  task?
233 *
234 *  If TRUE, then the floating point context will not be stored until
235 *  necessary.  It will remain in the floating point registers and not
236 *  disturned until another floating point task is switched to.
237 *
238 *  If FALSE, then the floating point context is saved when a floating
239 *  point task is switched out and restored when the next floating point
240 *  task is restored.  The state of the floating point registers between
241 *  those two operations is not specified.
242 *
243 *  If the floating point context does NOT have to be saved as part of
244 *  interrupt dispatching, then it should be safe to set this to TRUE.
245 *
246 *  Setting this flag to TRUE results in using a different algorithm
247 *  for deciding when to save and restore the floating point context.
248 *  The deferred FP switch algorithm minimizes the number of times
249 *  the FP context is saved and restored.  The FP context is not saved
250 *  until a context switch is made to another, different FP task.
251 *  Thus in a system with only one FP task, the FP context will never
252 *  be saved or restored.
253 *
254 *  NO_CPU Specific Information:
255 *
256 *  XXX document implementation including references if appropriate
257 */
258
259#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
260
261/*
262 *  Does this port provide a CPU dependent IDLE task implementation?
263 *
264 *  If TRUE, then the routine _CPU_Thread_Idle_body
265 *  must be provided and is the default IDLE thread body instead of
266 *  _CPU_Thread_Idle_body.
267 *
268 *  If FALSE, then use the generic IDLE thread body if the BSP does
269 *  not provide one.
270 *
271 *  This is intended to allow for supporting processors which have
272 *  a low power or idle mode.  When the IDLE thread is executed, then
273 *  the CPU can be powered down.
274 *
275 *  The order of precedence for selecting the IDLE thread body is:
276 *
277 *    1.  BSP provided
278 *    2.  CPU dependent (if provided)
279 *    3.  generic (if no BSP and no CPU dependent)
280 *
281 *  NO_CPU Specific Information:
282 *
283 *  XXX document implementation including references if appropriate
284 */
285
286#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
287
288/*
289 *  Does the stack grow up (toward higher addresses) or down
290 *  (toward lower addresses)?
291 *
292 *  If TRUE, then the grows upward.
293 *  If FALSE, then the grows toward smaller addresses.
294 *
295 *  NO_CPU Specific Information:
296 *
297 *  XXX document implementation including references if appropriate
298 */
299
300#define CPU_STACK_GROWS_UP               TRUE
301
302/*
303 *  The following is the variable attribute used to force alignment
304 *  of critical RTEMS structures.  On some processors it may make
305 *  sense to have these aligned on tighter boundaries than
306 *  the minimum requirements of the compiler in order to have as
307 *  much of the critical data area as possible in a cache line.
308 *
309 *  The placement of this macro in the declaration of the variables
310 *  is based on the syntactically requirements of the GNU C
311 *  "__attribute__" extension.  For example with GNU C, use
312 *  the following to force a structures to a 32 byte boundary.
313 *
314 *      __attribute__ ((aligned (32)))
315 *
316 *  NOTE:  Currently only the Priority Bit Map table uses this feature.
317 *         To benefit from using this, the data must be heavily
318 *         used so it will stay in the cache and used frequently enough
319 *         in the executive to justify turning this on.
320 *
321 *  NO_CPU Specific Information:
322 *
323 *  XXX document implementation including references if appropriate
324 */
325
326#define CPU_STRUCTURE_ALIGNMENT
327
328/*
329 *  Define what is required to specify how the network to host conversion
330 *  routines are handled.
331 *
332 *  NO_CPU Specific Information:
333 *
334 *  XXX document implementation including references if appropriate
335 */
336
337#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
338#define CPU_BIG_ENDIAN                           TRUE
339#define CPU_LITTLE_ENDIAN                        FALSE
340
341/*
342 *  The following defines the number of bits actually used in the
343 *  interrupt field of the task mode.  How those bits map to the
344 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
345 *
346 *  NO_CPU Specific Information:
347 *
348 *  XXX document implementation including references if appropriate
349 */
350
351#define CPU_MODES_INTERRUPT_MASK   0x00000001
352
353/*
354 *  Processor defined structures
355 *
356 *  Examples structures include the descriptor tables from the i386
357 *  and the processor control structure on the i960ca.
358 *
359 *  NO_CPU Specific Information:
360 *
361 *  XXX document implementation including references if appropriate
362 */
363
364/* may need to put some structures here.  */
365
366/*
367 * Contexts
368 *
369 *  Generally there are 2 types of context to save.
370 *     1. Interrupt registers to save
371 *     2. Task level registers to save
372 *
373 *  This means we have the following 3 context items:
374 *     1. task level context stuff::  Context_Control
375 *     2. floating point task stuff:: Context_Control_fp
376 *     3. special interrupt level context :: Context_Control_interrupt
377 *
378 *  On some processors, it is cost-effective to save only the callee
379 *  preserved registers during a task context switch.  This means
380 *  that the ISR code needs to save those registers which do not
381 *  persist across function calls.  It is not mandatory to make this
382 *  distinctions between the caller/callee saves registers for the
383 *  purpose of minimizing context saved during task switch and on interrupts.
384 *  If the cost of saving extra registers is minimal, simplicity is the
385 *  choice.  Save the same context on interrupt entry as for tasks in
386 *  this case.
387 *
388 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
389 *  care should be used in designing the context area.
390 *
391 *  On some CPUs with hardware floating point support, the Context_Control_fp
392 *  structure will not be used or it simply consist of an array of a
393 *  fixed number of bytes.   This is done when the floating point context
394 *  is dumped by a "FP save context" type instruction and the format
395 *  is not really defined by the CPU.  In this case, there is no need
396 *  to figure out the exact format -- only the size.  Of course, although
397 *  this is enough information for RTEMS, it is probably not enough for
398 *  a debugger such as gdb.  But that is another problem.
399 *
400 *  NO_CPU Specific Information:
401 *
402 *  XXX document implementation including references if appropriate
403 */
404
405typedef struct {
406    unsigned32 some_integer_register;
407    unsigned32 some_system_register;
408} Context_Control;
409
410typedef struct {
411    double      some_float_register;
412} Context_Control_fp;
413
414typedef struct {
415    unsigned32 special_interrupt_register;
416} CPU_Interrupt_frame;
417
418
419/*
420 *  The following table contains the information required to configure
421 *  the XXX processor specific parameters.
422 *
423 *  NO_CPU Specific Information:
424 *
425 *  XXX document implementation including references if appropriate
426 */
427
428typedef struct {
429  void       (*pretasking_hook)( void );
430  void       (*predriver_hook)( void );
431  void       (*postdriver_hook)( void );
432  void       (*idle_task)( void );
433  boolean      do_zero_of_workspace;
434  unsigned32   idle_task_stack_size;
435  unsigned32   interrupt_stack_size;
436  unsigned32   extra_mpci_receive_server_stack;
437  void *     (*stack_allocate_hook)( unsigned32 );
438  void       (*stack_free_hook)( void* );
439  /* end of fields required on all CPUs */
440
441}   rtems_cpu_table;
442
443/*
444 *  Macros to access required entires in the CPU Table are in
445 *  the file rtems/system.h.
446 *
447 *  NO_CPU Specific Information:
448 *
449 *  XXX document implementation including references if appropriate
450 */
451
452/*
453 *  Macros to access NO_CPU specific additions to the CPU Table
454 *
455 *  NO_CPU Specific Information:
456 *
457 *  XXX document implementation including references if appropriate
458 */
459
460/* There are no CPU specific additions to the CPU Table for this port. */
461
462/*
463 *  This variable is optional.  It is used on CPUs on which it is difficult
464 *  to generate an "uninitialized" FP context.  It is filled in by
465 *  _CPU_Initialize and copied into the task's FP context area during
466 *  _CPU_Context_Initialize.
467 *
468 *  NO_CPU Specific Information:
469 *
470 *  XXX document implementation including references if appropriate
471 */
472
473SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
474
475/*
476 *  On some CPUs, RTEMS supports a software managed interrupt stack.
477 *  This stack is allocated by the Interrupt Manager and the switch
478 *  is performed in _ISR_Handler.  These variables contain pointers
479 *  to the lowest and highest addresses in the chunk of memory allocated
480 *  for the interrupt stack.  Since it is unknown whether the stack
481 *  grows up or down (in general), this give the CPU dependent
482 *  code the option of picking the version it wants to use.
483 *
484 *  NOTE: These two variables are required if the macro
485 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
486 *
487 *  NO_CPU Specific Information:
488 *
489 *  XXX document implementation including references if appropriate
490 */
491
492SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
493SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
494
495/*
496 *  With some compilation systems, it is difficult if not impossible to
497 *  call a high-level language routine from assembly language.  This
498 *  is especially true of commercial Ada compilers and name mangling
499 *  C++ ones.  This variable can be optionally defined by the CPU porter
500 *  and contains the address of the routine _Thread_Dispatch.  This
501 *  can make it easier to invoke that routine at the end of the interrupt
502 *  sequence (if a dispatch is necessary).
503 *
504 *  NO_CPU Specific Information:
505 *
506 *  XXX document implementation including references if appropriate
507 */
508
509SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
510
511/*
512 *  Nothing prevents the porter from declaring more CPU specific variables.
513 *
514 *  NO_CPU Specific Information:
515 *
516 *  XXX document implementation including references if appropriate
517 */
518
519/* XXX: if needed, put more variables here */
520
521/*
522 *  The size of the floating point context area.  On some CPUs this
523 *  will not be a "sizeof" because the format of the floating point
524 *  area is not defined -- only the size is.  This is usually on
525 *  CPUs with a "floating point save context" instruction.
526 *
527 *  NO_CPU Specific Information:
528 *
529 *  XXX document implementation including references if appropriate
530 */
531
532#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
533
534/*
535 *  Amount of extra stack (above minimum stack size) required by
536 *  MPCI receive server thread.  Remember that in a multiprocessor
537 *  system this thread must exist and be able to process all directives.
538 *
539 *  NO_CPU Specific Information:
540 *
541 *  XXX document implementation including references if appropriate
542 */
543
544#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
545
546/*
547 *  This defines the number of entries in the ISR_Vector_table managed
548 *  by RTEMS.
549 *
550 *  NO_CPU Specific Information:
551 *
552 *  XXX document implementation including references if appropriate
553 */
554
555#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
556#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
557
558/*
559 *  This is defined if the port has a special way to report the ISR nesting
560 *  level.  Most ports maintain the variable _ISR_Nest_level.
561 */
562
563#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
564
565/*
566 *  Should be large enough to run all RTEMS tests.  This insures
567 *  that a "reasonable" small application should not have any problems.
568 *
569 *  NO_CPU Specific Information:
570 *
571 *  XXX document implementation including references if appropriate
572 */
573
574#define CPU_STACK_MINIMUM_SIZE          (1024*4)
575
576/*
577 *  CPU's worst alignment requirement for data types on a byte boundary.  This
578 *  alignment does not take into account the requirements for the stack.
579 *
580 *  NO_CPU Specific Information:
581 *
582 *  XXX document implementation including references if appropriate
583 */
584
585#define CPU_ALIGNMENT              8
586
587/*
588 *  This number corresponds to the byte alignment requirement for the
589 *  heap handler.  This alignment requirement may be stricter than that
590 *  for the data types alignment specified by CPU_ALIGNMENT.  It is
591 *  common for the heap to follow the same alignment requirement as
592 *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
593 *  then this should be set to CPU_ALIGNMENT.
594 *
595 *  NOTE:  This does not have to be a power of 2 although it should be
596 *         a multiple of 2 greater than or equal to 2.  The requirement
597 *         to be a multiple of 2 is because the heap uses the least
598 *         significant field of the front and back flags to indicate
599 *         that a block is in use or free.  So you do not want any odd
600 *         length blocks really putting length data in that bit.
601 *
602 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
603 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
604 *         elements allocated from the heap meet all restrictions.
605 *
606 *  NO_CPU Specific Information:
607 *
608 *  XXX document implementation including references if appropriate
609 */
610
611#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
612
613/*
614 *  This number corresponds to the byte alignment requirement for memory
615 *  buffers allocated by the partition manager.  This alignment requirement
616 *  may be stricter than that for the data types alignment specified by
617 *  CPU_ALIGNMENT.  It is common for the partition to follow the same
618 *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
619 *  enough for the partition, then this should be set to CPU_ALIGNMENT.
620 *
621 *  NOTE:  This does not have to be a power of 2.  It does have to
622 *         be greater or equal to than CPU_ALIGNMENT.
623 *
624 *  NO_CPU Specific Information:
625 *
626 *  XXX document implementation including references if appropriate
627 */
628
629#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
630
631/*
632 *  This number corresponds to the byte alignment requirement for the
633 *  stack.  This alignment requirement may be stricter than that for the
634 *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
635 *  is strict enough for the stack, then this should be set to 0.
636 *
637 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
638 *
639 *  NO_CPU Specific Information:
640 *
641 *  XXX document implementation including references if appropriate
642 */
643
644#define CPU_STACK_ALIGNMENT        0
645
646/*
647 *  ISR handler macros
648 */
649
650/*
651 *  Support routine to initialize the RTEMS vector table after it is allocated.
652 *
653 *  NO_CPU Specific Information:
654 *
655 *  XXX document implementation including references if appropriate
656 */
657
658#define _CPU_Initialize_vectors()
659
660/*
661 *  Disable all interrupts for an RTEMS critical section.  The previous
662 *  level is returned in _level.
663 *
664 *  NO_CPU Specific Information:
665 *
666 *  XXX document implementation including references if appropriate
667 */
668
669#define _CPU_ISR_Disable( _isr_cookie ) \
670  { \
671    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
672  }
673
674/*
675 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
676 *  This indicates the end of an RTEMS critical section.  The parameter
677 *  _level is not modified.
678 *
679 *  NO_CPU Specific Information:
680 *
681 *  XXX document implementation including references if appropriate
682 */
683
684#define _CPU_ISR_Enable( _isr_cookie )  \
685  { \
686  }
687
688/*
689 *  This temporarily restores the interrupt to _level before immediately
690 *  disabling them again.  This is used to divide long RTEMS critical
691 *  sections into two or more parts.  The parameter _level is not
692 * modified.
693 *
694 *  NO_CPU Specific Information:
695 *
696 *  XXX document implementation including references if appropriate
697 */
698
699#define _CPU_ISR_Flash( _isr_cookie ) \
700  { \
701  }
702
703/*
704 *  Map interrupt level in task mode onto the hardware that the CPU
705 *  actually provides.  Currently, interrupt levels which do not
706 *  map onto the CPU in a generic fashion are undefined.  Someday,
707 *  it would be nice if these were "mapped" by the application
708 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
709 *  8 - 255 would be available for bsp/application specific meaning.
710 *  This could be used to manage a programmable interrupt controller
711 *  via the rtems_task_mode directive.
712 *
713 *  The get routine usually must be implemented as a subroutine.
714 *
715 *  NO_CPU Specific Information:
716 *
717 *  XXX document implementation including references if appropriate
718 */
719
720#define _CPU_ISR_Set_level( new_level ) \
721  { \
722  }
723
724unsigned32 _CPU_ISR_Get_level( void );
725
726/* end of ISR handler macros */
727
728/* Context handler macros */
729
730/*
731 *  Initialize the context to a state suitable for starting a
732 *  task after a context restore operation.  Generally, this
733 *  involves:
734 *
735 *     - setting a starting address
736 *     - preparing the stack
737 *     - preparing the stack and frame pointers
738 *     - setting the proper interrupt level in the context
739 *     - initializing the floating point context
740 *
741 *  This routine generally does not set any unnecessary register
742 *  in the context.  The state of the "general data" registers is
743 *  undefined at task start time.
744 *
745 *  NOTE: This is_fp parameter is TRUE if the thread is to be a floating
746 *        point thread.  This is typically only used on CPUs where the
747 *        FPU may be easily disabled by software such as on the SPARC
748 *        where the PSR contains an enable FPU bit.
749 *
750 *  NO_CPU Specific Information:
751 *
752 *  XXX document implementation including references if appropriate
753 */
754
755#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
756                                 _isr, _entry_point, _is_fp ) \
757  { \
758  }
759
760/*
761 *  This routine is responsible for somehow restarting the currently
762 *  executing task.  If you are lucky, then all that is necessary
763 *  is restoring the context.  Otherwise, there will need to be
764 *  a special assembly routine which does something special in this
765 *  case.  Context_Restore should work most of the time.  It will
766 *  not work if restarting self conflicts with the stack frame
767 *  assumptions of restoring a context.
768 *
769 *  NO_CPU Specific Information:
770 *
771 *  XXX document implementation including references if appropriate
772 */
773
774#define _CPU_Context_Restart_self( _the_context ) \
775   _CPU_Context_restore( (_the_context) );
776
777/*
778 *  The purpose of this macro is to allow the initial pointer into
779 *  a floating point context area (used to save the floating point
780 *  context) to be at an arbitrary place in the floating point
781 *  context area.
782 *
783 *  This is necessary because some FP units are designed to have
784 *  their context saved as a stack which grows into lower addresses.
785 *  Other FP units can be saved by simply moving registers into offsets
786 *  from the base of the context area.  Finally some FP units provide
787 *  a "dump context" instruction which could fill in from high to low
788 *  or low to high based on the whim of the CPU designers.
789 *
790 *  NO_CPU Specific Information:
791 *
792 *  XXX document implementation including references if appropriate
793 */
794
795#define _CPU_Context_Fp_start( _base, _offset ) \
796   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
797
798/*
799 *  This routine initializes the FP context area passed to it to.
800 *  There are a few standard ways in which to initialize the
801 *  floating point context.  The code included for this macro assumes
802 *  that this is a CPU in which a "initial" FP context was saved into
803 *  _CPU_Null_fp_context and it simply copies it to the destination
804 *  context passed to it.
805 *
806 *  Other models include (1) not doing anything, and (2) putting
807 *  a "null FP status word" in the correct place in the FP context.
808 *
809 *  NO_CPU Specific Information:
810 *
811 *  XXX document implementation including references if appropriate
812 */
813
814#define _CPU_Context_Initialize_fp( _destination ) \
815  { \
816   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
817  }
818
819/* end of Context handler macros */
820
821/* Fatal Error manager macros */
822
823/*
824 *  This routine copies _error into a known place -- typically a stack
825 *  location or a register, optionally disables interrupts, and
826 *  halts/stops the CPU.
827 *
828 *  NO_CPU Specific Information:
829 *
830 *  XXX document implementation including references if appropriate
831 */
832
833#define _CPU_Fatal_halt( _error ) \
834  { \
835  }
836
837/* end of Fatal Error manager macros */
838
839/* Bitfield handler macros */
840
841/*
842 *  This routine sets _output to the bit number of the first bit
843 *  set in _value.  _value is of CPU dependent type Priority_Bit_map_control.
844 *  This type may be either 16 or 32 bits wide although only the 16
845 *  least significant bits will be used.
846 *
847 *  There are a number of variables in using a "find first bit" type
848 *  instruction.
849 *
850 *    (1) What happens when run on a value of zero?
851 *    (2) Bits may be numbered from MSB to LSB or vice-versa.
852 *    (3) The numbering may be zero or one based.
853 *    (4) The "find first bit" instruction may search from MSB or LSB.
854 *
855 *  RTEMS guarantees that (1) will never happen so it is not a concern.
856 *  (2),(3), (4) are handled by the macros _CPU_Priority_mask() and
857 *  _CPU_Priority_bits_index().  These three form a set of routines
858 *  which must logically operate together.  Bits in the _value are
859 *  set and cleared based on masks built by _CPU_Priority_mask().
860 *  The basic major and minor values calculated by _Priority_Major()
861 *  and _Priority_Minor() are "massaged" by _CPU_Priority_bits_index()
862 *  to properly range between the values returned by the "find first bit"
863 *  instruction.  This makes it possible for _Priority_Get_highest() to
864 *  calculate the major and directly index into the minor table.
865 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
866 *  is the first bit found.
867 *
868 *  This entire "find first bit" and mapping process depends heavily
869 *  on the manner in which a priority is broken into a major and minor
870 *  components with the major being the 4 MSB of a priority and minor
871 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
872 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
873 *  to the lowest priority.
874 *
875 *  If your CPU does not have a "find first bit" instruction, then
876 *  there are ways to make do without it.  Here are a handful of ways
877 *  to implement this in software:
878 *
879 *    - a series of 16 bit test instructions
880 *    - a "binary search using if's"
881 *    - _number = 0
882 *      if _value > 0x00ff
883 *        _value >>=8
884 *        _number = 8;
885 *
886 *      if _value > 0x0000f
887 *        _value >=8
888 *        _number += 4
889 *
890 *      _number += bit_set_table[ _value ]
891 *
892 *    where bit_set_table[ 16 ] has values which indicate the first
893 *      bit set
894 *
895 *  NO_CPU Specific Information:
896 *
897 *  XXX document implementation including references if appropriate
898 */
899
900#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
901#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
902
903#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
904
905#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
906  { \
907    (_output) = 0;   /* do something to prevent warnings */ \
908  }
909
910#endif
911
912/* end of Bitfield handler macros */
913
914/*
915 *  This routine builds the mask which corresponds to the bit fields
916 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
917 *  for that routine.
918 *
919 *  NO_CPU Specific Information:
920 *
921 *  XXX document implementation including references if appropriate
922 */
923
924#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
925
926#define _CPU_Priority_Mask( _bit_number ) \
927  ( 1 << (_bit_number) )
928
929#endif
930
931/*
932 *  This routine translates the bit numbers returned by
933 *  _CPU_Bitfield_Find_first_bit() into something suitable for use as
934 *  a major or minor component of a priority.  See the discussion
935 *  for that routine.
936 *
937 *  NO_CPU Specific Information:
938 *
939 *  XXX document implementation including references if appropriate
940 */
941
942#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
943
944#define _CPU_Priority_bits_index( _priority ) \
945  (_priority)
946
947#endif
948
949/* end of Priority handler macros */
950
951/* functions */
952
953/*
954 *  _CPU_Initialize
955 *
956 *  This routine performs CPU dependent initialization.
957 *
958 *  NO_CPU Specific Information:
959 *
960 *  XXX document implementation including references if appropriate
961 */
962
963void _CPU_Initialize(
964  rtems_cpu_table  *cpu_table,
965  void      (*thread_dispatch)
966);
967
968/*
969 *  _CPU_ISR_install_raw_handler
970 *
971 *  This routine installs a "raw" interrupt handler directly into the
972 *  processor's vector table.
973 *
974 *  NO_CPU Specific Information:
975 *
976 *  XXX document implementation including references if appropriate
977 */
978 
979void _CPU_ISR_install_raw_handler(
980  unsigned32  vector,
981  proc_ptr    new_handler,
982  proc_ptr   *old_handler
983);
984
985/*
986 *  _CPU_ISR_install_vector
987 *
988 *  This routine installs an interrupt vector.
989 *
990 *  NO_CPU Specific Information:
991 *
992 *  XXX document implementation including references if appropriate
993 */
994
995void _CPU_ISR_install_vector(
996  unsigned32  vector,
997  proc_ptr    new_handler,
998  proc_ptr   *old_handler
999);
1000
1001/*
1002 *  _CPU_Install_interrupt_stack
1003 *
1004 *  This routine installs the hardware interrupt stack pointer.
1005 *
1006 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
1007 *         is TRUE.
1008 *
1009 *  NO_CPU Specific Information:
1010 *
1011 *  XXX document implementation including references if appropriate
1012 */
1013
1014void _CPU_Install_interrupt_stack( void );
1015
1016/*
1017 *  _CPU_Thread_Idle_body
1018 *
1019 *  This routine is the CPU dependent IDLE thread body.
1020 *
1021 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
1022 *         is TRUE.
1023 *
1024 *  NO_CPU Specific Information:
1025 *
1026 *  XXX document implementation including references if appropriate
1027 */
1028
1029void _CPU_Thread_Idle_body( void );
1030
1031/*
1032 *  _CPU_Context_switch
1033 *
1034 *  This routine switches from the run context to the heir context.
1035 *
1036 *  NO_CPU Specific Information:
1037 *
1038 *  XXX document implementation including references if appropriate
1039 */
1040
1041void _CPU_Context_switch(
1042  Context_Control  *run,
1043  Context_Control  *heir
1044);
1045
1046/*
1047 *  _CPU_Context_restore
1048 *
1049 *  This routine is generally used only to restart self in an
1050 *  efficient manner.  It may simply be a label in _CPU_Context_switch.
1051 *
1052 *  NOTE: May be unnecessary to reload some registers.
1053 *
1054 *  NO_CPU Specific Information:
1055 *
1056 *  XXX document implementation including references if appropriate
1057 */
1058
1059void _CPU_Context_restore(
1060  Context_Control *new_context
1061);
1062
1063/*
1064 *  _CPU_Context_save_fp
1065 *
1066 *  This routine saves the floating point context passed to it.
1067 *
1068 *  NO_CPU Specific Information:
1069 *
1070 *  XXX document implementation including references if appropriate
1071 */
1072
1073void _CPU_Context_save_fp(
1074  void **fp_context_ptr
1075);
1076
1077/*
1078 *  _CPU_Context_restore_fp
1079 *
1080 *  This routine restores the floating point context passed to it.
1081 *
1082 *  NO_CPU Specific Information:
1083 *
1084 *  XXX document implementation including references if appropriate
1085 */
1086
1087void _CPU_Context_restore_fp(
1088  void **fp_context_ptr
1089);
1090
1091/*  The following routine swaps the endian format of an unsigned int.
1092 *  It must be static because it is referenced indirectly.
1093 *
1094 *  This version will work on any processor, but if there is a better
1095 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1096 *
1097 *     swap least significant two bytes with 16-bit rotate
1098 *     swap upper and lower 16-bits
1099 *     swap most significant two bytes with 16-bit rotate
1100 *
1101 *  Some CPUs have special instructions which swap a 32-bit quantity in
1102 *  a single instruction (e.g. i486).  It is probably best to avoid
1103 *  an "endian swapping control bit" in the CPU.  One good reason is
1104 *  that interrupts would probably have to be disabled to insure that
1105 *  an interrupt does not try to access the same "chunk" with the wrong
1106 *  endian.  Another good reason is that on some CPUs, the endian bit
1107 *  endianness for ALL fetches -- both code and data -- so the code
1108 *  will be fetched incorrectly.
1109 *
1110 *  NO_CPU Specific Information:
1111 *
1112 *  XXX document implementation including references if appropriate
1113 */
1114 
1115static inline unsigned int CPU_swap_u32(
1116  unsigned int value
1117)
1118{
1119  unsigned32 byte1, byte2, byte3, byte4, swapped;
1120 
1121  byte4 = (value >> 24) & 0xff;
1122  byte3 = (value >> 16) & 0xff;
1123  byte2 = (value >> 8)  & 0xff;
1124  byte1 =  value        & 0xff;
1125 
1126  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1127  return( swapped );
1128}
1129
1130#define CPU_swap_u16( value ) \
1131  (((value&0xff) << 8) | ((value >> 8)&0xff))
1132
1133#ifdef __cplusplus
1134}
1135#endif
1136
1137#endif
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