source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 10fd4aac

4.11
Last change on this file since 10fd4aac was 10fd4aac, checked in by Sebastian Huber <sebastian.huber@…>, on Aug 2, 2013 at 11:54:08 AM

score/cpu: Add CPU_Per_CPU_control

Add CPU port specific per-CPU control.

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1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 *
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*
23 *  COPYRIGHT (c) 1989-2008.
24 *  On-Line Applications Research Corporation (OAR).
25 *
26 *  The license and distribution terms for this file may be
27 *  found in the file LICENSE in this distribution or at
28 *  http://www.rtems.com/license/LICENSE.
29 */
30
31#ifndef _RTEMS_SCORE_CPU_H
32#define _RTEMS_SCORE_CPU_H
33
34#ifdef __cplusplus
35extern "C" {
36#endif
37
38#include <rtems/score/types.h>
39#include <rtems/score/no_cpu.h>
40
41/* conditional compilation parameters */
42
43/**
44 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
45 *
46 * If TRUE, then they are inlined.
47 * If FALSE, then a subroutine call is made.
48 *
49 * This conditional is an example of the classic trade-off of size
50 * versus speed.  Inlining the call (TRUE) typically increases the
51 * size of RTEMS while speeding up the enabling of dispatching.
52 *
53 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
54 * only be 0 or 1 unless you are in an interrupt handler and that
55 * interrupt handler invokes the executive.]  When not inlined
56 * something calls @ref _Thread_Enable_dispatch which in turns calls
57 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
58 * one subroutine call is avoided entirely.
59 *
60 * Port Specific Information:
61 *
62 * XXX document implementation including references if appropriate
63 */
64#define CPU_INLINE_ENABLE_DISPATCH       FALSE
65
66/**
67 * Should the body of the search loops in _Thread_queue_Enqueue_priority
68 * be unrolled one time?  In unrolled each iteration of the loop examines
69 * two "nodes" on the chain being searched.  Otherwise, only one node
70 * is examined per iteration.
71 *
72 * If TRUE, then the loops are unrolled.
73 * If FALSE, then the loops are not unrolled.
74 *
75 * The primary factor in making this decision is the cost of disabling
76 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
77 * body of the loop.  On some CPUs, the flash is more expensive than
78 * one iteration of the loop body.  In this case, it might be desirable
79 * to unroll the loop.  It is important to note that on some CPUs, this
80 * code is the longest interrupt disable period in RTEMS.  So it is
81 * necessary to strike a balance when setting this parameter.
82 *
83 * Port Specific Information:
84 *
85 * XXX document implementation including references if appropriate
86 */
87#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
88
89/**
90 * Does RTEMS manage a dedicated interrupt stack in software?
91 *
92 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
93 * If FALSE, nothing is done.
94 *
95 * If the CPU supports a dedicated interrupt stack in hardware,
96 * then it is generally the responsibility of the BSP to allocate it
97 * and set it up.
98 *
99 * If the CPU does not support a dedicated interrupt stack, then
100 * the porter has two options: (1) execute interrupts on the
101 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
102 * interrupt stack.
103 *
104 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
105 *
106 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
107 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
108 * possible that both are FALSE for a particular CPU.  Although it
109 * is unclear what that would imply about the interrupt processing
110 * procedure on that CPU.
111 *
112 * Port Specific Information:
113 *
114 * XXX document implementation including references if appropriate
115 */
116#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
117
118/**
119 * Does the CPU follow the simple vectored interrupt model?
120 *
121 * If TRUE, then RTEMS allocates the vector table it internally manages.
122 * If FALSE, then the BSP is assumed to allocate and manage the vector
123 * table
124 *
125 * Port Specific Information:
126 *
127 * XXX document implementation including references if appropriate
128 */
129#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
130
131/**
132 * Does this CPU have hardware support for a dedicated interrupt stack?
133 *
134 * If TRUE, then it must be installed during initialization.
135 * If FALSE, then no installation is performed.
136 *
137 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
138 *
139 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
140 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
141 * possible that both are FALSE for a particular CPU.  Although it
142 * is unclear what that would imply about the interrupt processing
143 * procedure on that CPU.
144 *
145 * Port Specific Information:
146 *
147 * XXX document implementation including references if appropriate
148 */
149#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
150
151/**
152 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
153 *
154 * If TRUE, then the memory is allocated during initialization.
155 * If FALSE, then the memory is allocated during initialization.
156 *
157 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
158 *
159 * Port Specific Information:
160 *
161 * XXX document implementation including references if appropriate
162 */
163#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
164
165/**
166 * Does the RTEMS invoke the user's ISR with the vector number and
167 * a pointer to the saved interrupt frame (1) or just the vector
168 * number (0)?
169 *
170 * Port Specific Information:
171 *
172 * XXX document implementation including references if appropriate
173 */
174#define CPU_ISR_PASSES_FRAME_POINTER 0
175
176/**
177 * @def CPU_HARDWARE_FP
178 *
179 * Does the CPU have hardware floating point?
180 *
181 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
182 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
183 *
184 * If there is a FP coprocessor such as the i387 or mc68881, then
185 * the answer is TRUE.
186 *
187 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
188 * It indicates whether or not this CPU model has FP support.  For
189 * example, it would be possible to have an i386_nofp CPU model
190 * which set this to false to indicate that you have an i386 without
191 * an i387 and wish to leave floating point support out of RTEMS.
192 */
193
194/**
195 * @def CPU_SOFTWARE_FP
196 *
197 * Does the CPU have no hardware floating point and GCC provides a
198 * software floating point implementation which must be context
199 * switched?
200 *
201 * This feature conditional is used to indicate whether or not there
202 * is software implemented floating point that must be context
203 * switched.  The determination of whether or not this applies
204 * is very tool specific and the state saved/restored is also
205 * compiler specific.
206 *
207 * Port Specific Information:
208 *
209 * XXX document implementation including references if appropriate
210 */
211#if ( NO_CPU_HAS_FPU == 1 )
212#define CPU_HARDWARE_FP     TRUE
213#else
214#define CPU_HARDWARE_FP     FALSE
215#endif
216#define CPU_SOFTWARE_FP     FALSE
217
218/**
219 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
220 *
221 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
222 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
223 *
224 * So far, the only CPUs in which this option has been used are the
225 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
226 * gcc both implicitly used the floating point registers to perform
227 * integer multiplies.  Similarly, the PowerPC port of gcc has been
228 * seen to allocate floating point local variables and touch the FPU
229 * even when the flow through a subroutine (like vfprintf()) might
230 * not use floating point formats.
231 *
232 * If a function which you would not think utilize the FP unit DOES,
233 * then one can not easily predict which tasks will use the FP hardware.
234 * In this case, this option should be TRUE.
235 *
236 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
237 *
238 * Port Specific Information:
239 *
240 * XXX document implementation including references if appropriate
241 */
242#define CPU_ALL_TASKS_ARE_FP     TRUE
243
244/**
245 * Should the IDLE task have a floating point context?
246 *
247 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
248 * and it has a floating point context which is switched in and out.
249 * If FALSE, then the IDLE task does not have a floating point context.
250 *
251 * Setting this to TRUE negatively impacts the time required to preempt
252 * the IDLE task from an interrupt because the floating point context
253 * must be saved as part of the preemption.
254 *
255 * Port Specific Information:
256 *
257 * XXX document implementation including references if appropriate
258 */
259#define CPU_IDLE_TASK_IS_FP      FALSE
260
261/**
262 * Should the saving of the floating point registers be deferred
263 * until a context switch is made to another different floating point
264 * task?
265 *
266 * If TRUE, then the floating point context will not be stored until
267 * necessary.  It will remain in the floating point registers and not
268 * disturned until another floating point task is switched to.
269 *
270 * If FALSE, then the floating point context is saved when a floating
271 * point task is switched out and restored when the next floating point
272 * task is restored.  The state of the floating point registers between
273 * those two operations is not specified.
274 *
275 * If the floating point context does NOT have to be saved as part of
276 * interrupt dispatching, then it should be safe to set this to TRUE.
277 *
278 * Setting this flag to TRUE results in using a different algorithm
279 * for deciding when to save and restore the floating point context.
280 * The deferred FP switch algorithm minimizes the number of times
281 * the FP context is saved and restored.  The FP context is not saved
282 * until a context switch is made to another, different FP task.
283 * Thus in a system with only one FP task, the FP context will never
284 * be saved or restored.
285 *
286 * Port Specific Information:
287 *
288 * XXX document implementation including references if appropriate
289 */
290#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
291
292/**
293 * Does this port provide a CPU dependent IDLE task implementation?
294 *
295 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
296 * must be provided and is the default IDLE thread body instead of
297 * @ref _CPU_Thread_Idle_body.
298 *
299 * If FALSE, then use the generic IDLE thread body if the BSP does
300 * not provide one.
301 *
302 * This is intended to allow for supporting processors which have
303 * a low power or idle mode.  When the IDLE thread is executed, then
304 * the CPU can be powered down.
305 *
306 * The order of precedence for selecting the IDLE thread body is:
307 *
308 *   -#  BSP provided
309 *   -#  CPU dependent (if provided)
310 *   -#  generic (if no BSP and no CPU dependent)
311 *
312 * Port Specific Information:
313 *
314 * XXX document implementation including references if appropriate
315 */
316#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
317
318/**
319 * Does the stack grow up (toward higher addresses) or down
320 * (toward lower addresses)?
321 *
322 * If TRUE, then the grows upward.
323 * If FALSE, then the grows toward smaller addresses.
324 *
325 * Port Specific Information:
326 *
327 * XXX document implementation including references if appropriate
328 */
329#define CPU_STACK_GROWS_UP               TRUE
330
331/**
332 * The following is the variable attribute used to force alignment
333 * of critical RTEMS structures.  On some processors it may make
334 * sense to have these aligned on tighter boundaries than
335 * the minimum requirements of the compiler in order to have as
336 * much of the critical data area as possible in a cache line.
337 *
338 * The placement of this macro in the declaration of the variables
339 * is based on the syntactically requirements of the GNU C
340 * "__attribute__" extension.  For example with GNU C, use
341 * the following to force a structures to a 32 byte boundary.
342 *
343 *     __attribute__ ((aligned (32)))
344 *
345 * NOTE: Currently only the Priority Bit Map table uses this feature.
346 *       To benefit from using this, the data must be heavily
347 *       used so it will stay in the cache and used frequently enough
348 *       in the executive to justify turning this on.
349 *
350 * Port Specific Information:
351 *
352 * XXX document implementation including references if appropriate
353 */
354#define CPU_STRUCTURE_ALIGNMENT
355
356/**
357 * @defgroup CPUTimestamp Processor Dependent Timestamp Support
358 *
359 * This group assists in issues related to timestamp implementation.
360 *
361 * The port must choose exactly one of the following defines:
362 * - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
363 * - #define CPU_TIMESTAMP_USE_INT64 TRUE
364 * - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
365 *
366 * Performance of int64_t versus struct timespec
367 * =============================================
368 *
369 * On PowerPC/psim, inlined int64_t saves ~50 instructions on each
370 *   _Thread_Dispatch operation which results in a context switch.
371 *   This works out to be about 10% faster dispatches and 7.5% faster
372 *   blocking semaphore obtains.  The following numbers are in instructions
373 *   and from tm02 and tm26.
374 *
375 *                        timespec  int64  inlined int64
376 *   dispatch:              446      446      400
377 *   blocking sem obtain:   627      626      581
378 *
379 * On SPARC/sis, inlined int64_t shows the same percentage gains.
380 *   The following numbers are in microseconds and from tm02 and tm26.
381 *
382 *                        timespec  int64  inlined int64
383 *   dispatch:               59       61       53
384 *   blocking sem obtain:    98      100       92
385 *
386 * Inlining appears to have a tendency to increase the size of
387 *   some executables.
388 * Not inlining reduces the execution improvement but does not seem to
389 *   be an improvement on the PowerPC and SPARC. The struct timespec
390 *   and the executables with int64 not inlined are about the same size.
391 *
392 */
393/**@{**/
394
395/**
396 * Selects the timestamp implementation using struct timespec.
397 *
398 * Port Specific Information:
399 *
400 * XXX document implementation including references if appropriate
401 */
402#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
403
404/**
405 * Selects the timestamp implementation using int64_t and no inlined methods.
406 *
407 * Port Specific Information:
408 *
409 * XXX document implementation including references if appropriate
410 */
411#define CPU_TIMESTAMP_USE_INT64 TRUE
412
413/**
414 * Selects the timestamp implementation using int64_t and inlined methods.
415 *
416 * Port Specific Information:
417 *
418 * XXX document implementation including references if appropriate
419 */
420#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
421
422/** @} */
423
424/**
425 * @defgroup CPUEndian Processor Dependent Endianness Support
426 *
427 * This group assists in issues related to processor endianness.
428 *
429 */
430/**@{**/
431
432/**
433 * Define what is required to specify how the network to host conversion
434 * routines are handled.
435 *
436 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
437 * same values.
438 *
439 * @see CPU_LITTLE_ENDIAN
440 *
441 * Port Specific Information:
442 *
443 * XXX document implementation including references if appropriate
444 */
445#define CPU_BIG_ENDIAN                           TRUE
446
447/**
448 * Define what is required to specify how the network to host conversion
449 * routines are handled.
450 *
451 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
452 * same values.
453 *
454 * @see CPU_BIG_ENDIAN
455 *
456 * Port Specific Information:
457 *
458 * XXX document implementation including references if appropriate
459 */
460#define CPU_LITTLE_ENDIAN                        FALSE
461
462/** @} */
463
464/**
465 * @ingroup CPUInterrupt
466 *
467 * The following defines the number of bits actually used in the
468 * interrupt field of the task mode.  How those bits map to the
469 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
470 *
471 * Port Specific Information:
472 *
473 * XXX document implementation including references if appropriate
474 */
475#define CPU_MODES_INTERRUPT_MASK   0x00000001
476
477/**
478 * @brief The size of the CPU specific per-CPU control.
479 *
480 * This define must be visible to assember files since it is used to derive
481 * structure offsets.
482 */
483#define CPU_PER_CPU_CONTROL_SIZE 0
484
485/*
486 *  Processor defined structures required for cpukit/score.
487 *
488 *  Port Specific Information:
489 *
490 *  XXX document implementation including references if appropriate
491 */
492
493/* may need to put some structures here.  */
494
495/**
496 * @brief The CPU specific per-CPU control.
497 *
498 * The CPU port can place here all state information that must be available and
499 * maintained for each CPU in the system.
500 */
501typedef struct {
502  /* CPU specific per-CPU state */
503} CPU_Per_CPU_control;
504
505/**
506 * @defgroup CPUContext Processor Dependent Context Management
507 *
508 * From the highest level viewpoint, there are 2 types of context to save.
509 *
510 *    -# Interrupt registers to save
511 *    -# Task level registers to save
512 *
513 * Since RTEMS handles integer and floating point contexts separately, this
514 * means we have the following 3 context items:
515 *
516 *    -# task level context stuff::  Context_Control
517 *    -# floating point task stuff:: Context_Control_fp
518 *    -# special interrupt level context :: CPU_Interrupt_frame
519 *
520 * On some processors, it is cost-effective to save only the callee
521 * preserved registers during a task context switch.  This means
522 * that the ISR code needs to save those registers which do not
523 * persist across function calls.  It is not mandatory to make this
524 * distinctions between the caller/callee saves registers for the
525 * purpose of minimizing context saved during task switch and on interrupts.
526 * If the cost of saving extra registers is minimal, simplicity is the
527 * choice.  Save the same context on interrupt entry as for tasks in
528 * this case.
529 *
530 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
531 * care should be used in designing the context area.
532 *
533 * On some CPUs with hardware floating point support, the Context_Control_fp
534 * structure will not be used or it simply consist of an array of a
535 * fixed number of bytes.   This is done when the floating point context
536 * is dumped by a "FP save context" type instruction and the format
537 * is not really defined by the CPU.  In this case, there is no need
538 * to figure out the exact format -- only the size.  Of course, although
539 * this is enough information for RTEMS, it is probably not enough for
540 * a debugger such as gdb.  But that is another problem.
541 *
542 * Port Specific Information:
543 *
544 * XXX document implementation including references if appropriate
545 *
546 */
547/**@{**/
548
549/**
550 * @ingroup Management
551 * This defines the minimal set of integer and processor state registers
552 * that must be saved during a voluntary context switch from one thread
553 * to another.
554 */
555typedef struct {
556    /**
557     * This field is a hint that a port will have a number of integer
558     * registers that need to be saved at a context switch.
559     */
560    uint32_t   some_integer_register;
561    /**
562     * This field is a hint that a port will have a number of system
563     * registers that need to be saved at a context switch.
564     */
565    uint32_t   some_system_register;
566
567    /**
568     * This field is a hint that a port will have a register that
569     * is the stack pointer.
570     */
571    uint32_t   stack_pointer;
572} Context_Control;
573
574/**
575 * @ingroup Management
576 *
577 * This macro returns the stack pointer associated with @a _context.
578 *
579 * @param[in] _context is the thread context area to access
580 *
581 * @return This method returns the stack pointer.
582 */
583#define _CPU_Context_Get_SP( _context ) \
584  (_context)->stack_pointer
585
586/**
587 * @ingroup Management
588 *
589 * This defines the complete set of floating point registers that must
590 * be saved during any context switch from one thread to another.
591 */
592typedef struct {
593    /** FPU registers are listed here */
594    double      some_float_register;
595} Context_Control_fp;
596
597/**
598 * @ingroup Management
599 *
600 * This defines the set of integer and processor state registers that must
601 * be saved during an interrupt.  This set does not include any which are
602 * in @ref Context_Control.
603 */
604typedef struct {
605    /**
606     * This field is a hint that a port will have a number of integer
607     * registers that need to be saved when an interrupt occurs or
608     * when a context switch occurs at the end of an ISR.
609     */
610    uint32_t   special_interrupt_register;
611} CPU_Interrupt_frame;
612
613/**
614 * This variable is optional.  It is used on CPUs on which it is difficult
615 * to generate an "uninitialized" FP context.  It is filled in by
616 * @ref _CPU_Initialize and copied into the task's FP context area during
617 * @ref _CPU_Context_Initialize.
618 *
619 * Port Specific Information:
620 *
621 * XXX document implementation including references if appropriate
622 */
623SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
624
625/** @} */
626
627/**
628 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
629 *
630 * On some CPUs, RTEMS supports a software managed interrupt stack.
631 * This stack is allocated by the Interrupt Manager and the switch
632 * is performed in @ref _ISR_Handler.  These variables contain pointers
633 * to the lowest and highest addresses in the chunk of memory allocated
634 * for the interrupt stack.  Since it is unknown whether the stack
635 * grows up or down (in general), this give the CPU dependent
636 * code the option of picking the version it wants to use.
637 *
638 * NOTE: These two variables are required if the macro
639 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
640 *
641 * Port Specific Information:
642 *
643 * XXX document implementation including references if appropriate
644 */
645
646/*
647 *  Nothing prevents the porter from declaring more CPU specific variables.
648 *
649 *  Port Specific Information:
650 *
651 *  XXX document implementation including references if appropriate
652 */
653
654/* XXX: if needed, put more variables here */
655
656/**
657 * @ingroup CPUContext
658 *
659 * The size of the floating point context area.  On some CPUs this
660 * will not be a "sizeof" because the format of the floating point
661 * area is not defined -- only the size is.  This is usually on
662 * CPUs with a "floating point save context" instruction.
663 *
664 * Port Specific Information:
665 *
666 * XXX document implementation including references if appropriate
667 */
668#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
669
670/**
671 * Amount of extra stack (above minimum stack size) required by
672 * MPCI receive server thread.  Remember that in a multiprocessor
673 * system this thread must exist and be able to process all directives.
674 *
675 * Port Specific Information:
676 *
677 * XXX document implementation including references if appropriate
678 */
679#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
680
681/**
682 * @ingroup CPUInterrupt
683 *
684 * This defines the number of entries in the @ref _ISR_Vector_table managed
685 * by RTEMS.
686 *
687 * Port Specific Information:
688 *
689 * XXX document implementation including references if appropriate
690 */
691#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
692
693/**
694 * @ingroup CPUInterrupt
695 *
696 * This defines the highest interrupt vector number for this port.
697 */
698#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
699
700/**
701 * @ingroup CPUInterrupt
702 *
703 * This is defined if the port has a special way to report the ISR nesting
704 * level.  Most ports maintain the variable @a _ISR_Nest_level.
705 */
706#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
707
708/**
709 * @ingroup CPUContext
710 *
711 * Should be large enough to run all RTEMS tests.  This ensures
712 * that a "reasonable" small application should not have any problems.
713 *
714 * Port Specific Information:
715 *
716 * XXX document implementation including references if appropriate
717 */
718#define CPU_STACK_MINIMUM_SIZE          (1024*4)
719
720/**
721 * Size of a pointer.
722 *
723 * This must be an integer literal that can be used by the assembler.  This
724 * value will be used to calculate offsets of structure members.  These
725 * offsets will be used in assembler code.
726 */
727#define CPU_SIZEOF_POINTER         4
728
729/**
730 * CPU's worst alignment requirement for data types on a byte boundary.  This
731 * alignment does not take into account the requirements for the stack.
732 *
733 * Port Specific Information:
734 *
735 * XXX document implementation including references if appropriate
736 */
737#define CPU_ALIGNMENT              8
738
739/**
740 * This number corresponds to the byte alignment requirement for the
741 * heap handler.  This alignment requirement may be stricter than that
742 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
743 * common for the heap to follow the same alignment requirement as
744 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
745 * the heap, then this should be set to @ref CPU_ALIGNMENT.
746 *
747 * NOTE:  This does not have to be a power of 2 although it should be
748 *        a multiple of 2 greater than or equal to 2.  The requirement
749 *        to be a multiple of 2 is because the heap uses the least
750 *        significant field of the front and back flags to indicate
751 *        that a block is in use or free.  So you do not want any odd
752 *        length blocks really putting length data in that bit.
753 *
754 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
755 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
756 *        elements allocated from the heap meet all restrictions.
757 *
758 * Port Specific Information:
759 *
760 * XXX document implementation including references if appropriate
761 */
762#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
763
764/**
765 * This number corresponds to the byte alignment requirement for memory
766 * buffers allocated by the partition manager.  This alignment requirement
767 * may be stricter than that for the data types alignment specified by
768 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
769 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
770 * strict enough for the partition, then this should be set to
771 * @ref CPU_ALIGNMENT.
772 *
773 * NOTE:  This does not have to be a power of 2.  It does have to
774 *        be greater or equal to than @ref CPU_ALIGNMENT.
775 *
776 * Port Specific Information:
777 *
778 * XXX document implementation including references if appropriate
779 */
780#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
781
782/**
783 * This number corresponds to the byte alignment requirement for the
784 * stack.  This alignment requirement may be stricter than that for the
785 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
786 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
787 * set to 0.
788 *
789 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
790 *
791 * Port Specific Information:
792 *
793 * XXX document implementation including references if appropriate
794 */
795#define CPU_STACK_ALIGNMENT        0
796
797/*
798 *  ISR handler macros
799 */
800
801/**
802 * @ingroup CPUInterrupt
803 *
804 * Support routine to initialize the RTEMS vector table after it is allocated.
805 *
806 * Port Specific Information:
807 *
808 * XXX document implementation including references if appropriate
809 */
810#define _CPU_Initialize_vectors()
811
812/**
813 * @ingroup CPUInterrupt
814 *
815 * Disable all interrupts for an RTEMS critical section.  The previous
816 * level is returned in @a _isr_cookie.
817 *
818 * @param[out] _isr_cookie will contain the previous level cookie
819 *
820 * Port Specific Information:
821 *
822 * XXX document implementation including references if appropriate
823 */
824#define _CPU_ISR_Disable( _isr_cookie ) \
825  { \
826    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
827  }
828
829/**
830 * @ingroup CPUInterrupt
831 *
832 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
833 * This indicates the end of an RTEMS critical section.  The parameter
834 * @a _isr_cookie is not modified.
835 *
836 * @param[in] _isr_cookie contain the previous level cookie
837 *
838 * Port Specific Information:
839 *
840 * XXX document implementation including references if appropriate
841 */
842#define _CPU_ISR_Enable( _isr_cookie )  \
843  { \
844  }
845
846/**
847 * @ingroup CPUInterrupt
848 *
849 * This temporarily restores the interrupt to @a _isr_cookie before immediately
850 * disabling them again.  This is used to divide long RTEMS critical
851 * sections into two or more parts.  The parameter @a _isr_cookie is not
852 * modified.
853 *
854 * @param[in] _isr_cookie contain the previous level cookie
855 *
856 * Port Specific Information:
857 *
858 * XXX document implementation including references if appropriate
859 */
860#define _CPU_ISR_Flash( _isr_cookie ) \
861  { \
862  }
863
864/**
865 * @ingroup CPUInterrupt
866 *
867 * This routine and @ref _CPU_ISR_Get_level
868 * Map the interrupt level in task mode onto the hardware that the CPU
869 * actually provides.  Currently, interrupt levels which do not
870 * map onto the CPU in a generic fashion are undefined.  Someday,
871 * it would be nice if these were "mapped" by the application
872 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
873 * 8 - 255 would be available for bsp/application specific meaning.
874 * This could be used to manage a programmable interrupt controller
875 * via the rtems_task_mode directive.
876 *
877 * Port Specific Information:
878 *
879 * XXX document implementation including references if appropriate
880 */
881#define _CPU_ISR_Set_level( new_level ) \
882  { \
883  }
884
885/**
886 * @ingroup CPUInterrupt
887 *
888 * Return the current interrupt disable level for this task in
889 * the format used by the interrupt level portion of the task mode.
890 *
891 * NOTE: This routine usually must be implemented as a subroutine.
892 *
893 * Port Specific Information:
894 *
895 * XXX document implementation including references if appropriate
896 */
897uint32_t   _CPU_ISR_Get_level( void );
898
899/* end of ISR handler macros */
900
901/* Context handler macros */
902
903/**
904 *  @ingroup CPUContext
905 *
906 * Initialize the context to a state suitable for starting a
907 * task after a context restore operation.  Generally, this
908 * involves:
909 *
910 *    - setting a starting address
911 *    - preparing the stack
912 *    - preparing the stack and frame pointers
913 *    - setting the proper interrupt level in the context
914 *    - initializing the floating point context
915 *
916 * This routine generally does not set any unnecessary register
917 * in the context.  The state of the "general data" registers is
918 * undefined at task start time.
919 *
920 * @param[in] _the_context is the context structure to be initialized
921 * @param[in] _stack_base is the lowest physical address of this task's stack
922 * @param[in] _size is the size of this task's stack
923 * @param[in] _isr is the interrupt disable level
924 * @param[in] _entry_point is the thread's entry point.  This is
925 *        always @a _Thread_Handler
926 * @param[in] _is_fp is TRUE if the thread is to be a floating
927 *       point thread.  This is typically only used on CPUs where the
928 *       FPU may be easily disabled by software such as on the SPARC
929 *       where the PSR contains an enable FPU bit.
930 *
931 * Port Specific Information:
932 *
933 * XXX document implementation including references if appropriate
934 */
935#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
936                                 _isr, _entry_point, _is_fp ) \
937  { \
938  }
939
940/**
941 * This routine is responsible for somehow restarting the currently
942 * executing task.  If you are lucky, then all that is necessary
943 * is restoring the context.  Otherwise, there will need to be
944 * a special assembly routine which does something special in this
945 * case.  For many ports, simply adding a label to the restore path
946 * of @ref _CPU_Context_switch will work.  On other ports, it may be
947 * possibly to load a few arguments and jump to the restore path. It will
948 * not work if restarting self conflicts with the stack frame
949 * assumptions of restoring a context.
950 *
951 * Port Specific Information:
952 *
953 * XXX document implementation including references if appropriate
954 */
955#define _CPU_Context_Restart_self( _the_context ) \
956   _CPU_Context_restore( (_the_context) );
957
958/**
959 * @ingroup CPUContext
960 *
961 * The purpose of this macro is to allow the initial pointer into
962 * a floating point context area (used to save the floating point
963 * context) to be at an arbitrary place in the floating point
964 *context area.
965 *
966 * This is necessary because some FP units are designed to have
967 * their context saved as a stack which grows into lower addresses.
968 * Other FP units can be saved by simply moving registers into offsets
969 * from the base of the context area.  Finally some FP units provide
970 * a "dump context" instruction which could fill in from high to low
971 * or low to high based on the whim of the CPU designers.
972 *
973 * @param[in] _base is the lowest physical address of the floating point
974 *        context area
975 * @param[in] _offset is the offset into the floating point area
976 *
977 * Port Specific Information:
978 *
979 * XXX document implementation including references if appropriate
980 */
981#define _CPU_Context_Fp_start( _base, _offset ) \
982   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
983
984/**
985 * This routine initializes the FP context area passed to it to.
986 * There are a few standard ways in which to initialize the
987 * floating point context.  The code included for this macro assumes
988 * that this is a CPU in which a "initial" FP context was saved into
989 * @a _CPU_Null_fp_context and it simply copies it to the destination
990 * context passed to it.
991 *
992 * Other floating point context save/restore models include:
993 *   -# not doing anything, and
994 *   -# putting a "null FP status word" in the correct place in the FP context.
995 *
996 * @param[in] _destination is the floating point context area
997 *
998 * Port Specific Information:
999 *
1000 * XXX document implementation including references if appropriate
1001 */
1002#define _CPU_Context_Initialize_fp( _destination ) \
1003  { \
1004   *(*(_destination)) = _CPU_Null_fp_context; \
1005  }
1006
1007/* end of Context handler macros */
1008
1009/* Fatal Error manager macros */
1010
1011/**
1012 * This routine copies _error into a known place -- typically a stack
1013 * location or a register, optionally disables interrupts, and
1014 * halts/stops the CPU.
1015 *
1016 * Port Specific Information:
1017 *
1018 * XXX document implementation including references if appropriate
1019 */
1020#define _CPU_Fatal_halt( _error ) \
1021  { \
1022  }
1023
1024/* end of Fatal Error manager macros */
1025
1026/* Bitfield handler macros */
1027
1028/**
1029 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1030 *
1031 * This set of routines are used to implement fast searches for
1032 * the most important ready task.
1033 *
1034 */
1035/**@{**/
1036
1037/**
1038 * This definition is set to TRUE if the port uses the generic bitfield
1039 * manipulation implementation.
1040 */
1041#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1042
1043/**
1044 * This definition is set to TRUE if the port uses the data tables provided
1045 * by the generic bitfield manipulation implementation.
1046 * This can occur when actually using the generic bitfield manipulation
1047 * implementation or when implementing the same algorithm in assembly
1048 * language for improved performance.  It is unlikely that a port will use
1049 * the data if it has a bitfield scan instruction.
1050 */
1051#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1052
1053/**
1054 * This routine sets @a _output to the bit number of the first bit
1055 * set in @a _value.  @a _value is of CPU dependent type
1056 * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
1057 * wide although only the 16 least significant bits will be used.
1058 *
1059 * There are a number of variables in using a "find first bit" type
1060 * instruction.
1061 *
1062 *   -# What happens when run on a value of zero?
1063 *   -# Bits may be numbered from MSB to LSB or vice-versa.
1064 *   -# The numbering may be zero or one based.
1065 *   -# The "find first bit" instruction may search from MSB or LSB.
1066 *
1067 * RTEMS guarantees that (1) will never happen so it is not a concern.
1068 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1069 * @ref _CPU_Priority_bits_index.  These three form a set of routines
1070 * which must logically operate together.  Bits in the _value are
1071 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
1072 * The basic major and minor values calculated by @ref _Priority_Major
1073 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1074 * to properly range between the values returned by the "find first bit"
1075 * instruction.  This makes it possible for @ref _Priority_Get_highest to
1076 * calculate the major and directly index into the minor table.
1077 * This mapping is necessary to ensure that 0 (a high priority major/minor)
1078 * is the first bit found.
1079 *
1080 * This entire "find first bit" and mapping process depends heavily
1081 * on the manner in which a priority is broken into a major and minor
1082 * components with the major being the 4 MSB of a priority and minor
1083 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1084 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1085 * to the lowest priority.
1086 *
1087 * If your CPU does not have a "find first bit" instruction, then
1088 * there are ways to make do without it.  Here are a handful of ways
1089 * to implement this in software:
1090 *
1091@verbatim
1092      - a series of 16 bit test instructions
1093      - a "binary search using if's"
1094      - _number = 0
1095        if _value > 0x00ff
1096          _value >>=8
1097          _number = 8;
1098
1099        if _value > 0x0000f
1100          _value >=8
1101          _number += 4
1102
1103        _number += bit_set_table[ _value ]
1104@endverbatim
1105
1106 *   where bit_set_table[ 16 ] has values which indicate the first
1107 *     bit set
1108 *
1109 * @param[in] _value is the value to be scanned
1110 * @param[in] _output is the first bit set
1111 *
1112 * Port Specific Information:
1113 *
1114 * XXX document implementation including references if appropriate
1115 */
1116
1117#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1118#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1119  { \
1120    (_output) = 0;   /* do something to prevent warnings */ \
1121  }
1122#endif
1123
1124/** @} */
1125
1126/* end of Bitfield handler macros */
1127
1128/**
1129 * This routine builds the mask which corresponds to the bit fields
1130 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1131 * for that routine.
1132 *
1133 * Port Specific Information:
1134 *
1135 * XXX document implementation including references if appropriate
1136 */
1137#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1138
1139#define _CPU_Priority_Mask( _bit_number ) \
1140  ( 1 << (_bit_number) )
1141
1142#endif
1143
1144/**
1145 * @ingroup CPUBitfield
1146 *
1147 * This routine translates the bit numbers returned by
1148 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1149 * a major or minor component of a priority.  See the discussion
1150 * for that routine.
1151 *
1152 * @param[in] _priority is the major or minor number to translate
1153 *
1154 * Port Specific Information:
1155 *
1156 * XXX document implementation including references if appropriate
1157 */
1158#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1159
1160#define _CPU_Priority_bits_index( _priority ) \
1161  (_priority)
1162
1163#endif
1164
1165/* end of Priority handler macros */
1166
1167/* functions */
1168
1169/**
1170 * This routine performs CPU dependent initialization.
1171 *
1172 * Port Specific Information:
1173 *
1174 * XXX document implementation including references if appropriate
1175 */
1176void _CPU_Initialize(void);
1177
1178/**
1179 * @ingroup CPUInterrupt
1180 *
1181 * This routine installs a "raw" interrupt handler directly into the
1182 * processor's vector table.
1183 *
1184 * @param[in] vector is the vector number
1185 * @param[in] new_handler is the raw ISR handler to install
1186 * @param[in] old_handler is the previously installed ISR Handler
1187 *
1188 * Port Specific Information:
1189 *
1190 * XXX document implementation including references if appropriate
1191 */
1192void _CPU_ISR_install_raw_handler(
1193  uint32_t    vector,
1194  proc_ptr    new_handler,
1195  proc_ptr   *old_handler
1196);
1197
1198/**
1199 * @ingroup CPUInterrupt
1200 *
1201 * This routine installs an interrupt vector.
1202 *
1203 * @param[in] vector is the vector number
1204 * @param[in] new_handler is the RTEMS ISR handler to install
1205 * @param[in] old_handler is the previously installed ISR Handler
1206 *
1207 * Port Specific Information:
1208 *
1209 * XXX document implementation including references if appropriate
1210 */
1211void _CPU_ISR_install_vector(
1212  uint32_t    vector,
1213  proc_ptr    new_handler,
1214  proc_ptr   *old_handler
1215);
1216
1217/**
1218 * @ingroup CPUInterrupt
1219 * This routine installs the hardware interrupt stack pointer.
1220 *
1221 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1222 *        is TRUE.
1223 *
1224 * Port Specific Information:
1225 *
1226 * XXX document implementation including references if appropriate
1227 */
1228void _CPU_Install_interrupt_stack( void );
1229
1230/**
1231 * This routine is the CPU dependent IDLE thread body.
1232 *
1233 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1234 *         is TRUE.
1235 *
1236 * Port Specific Information:
1237 *
1238 * XXX document implementation including references if appropriate
1239 */
1240void *_CPU_Thread_Idle_body( uintptr_t ignored );
1241
1242/**
1243 * @ingroup CPUContext
1244 *
1245 * This routine switches from the run context to the heir context.
1246 *
1247 * @param[in] run points to the context of the currently executing task
1248 * @param[in] heir points to the context of the heir task
1249 *
1250 * Port Specific Information:
1251 *
1252 * XXX document implementation including references if appropriate
1253 */
1254void _CPU_Context_switch(
1255  Context_Control  *run,
1256  Context_Control  *heir
1257);
1258
1259/**
1260 * @ingroup CPUContext
1261 *
1262 * This routine is generally used only to restart self in an
1263 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1264 *
1265 * @param[in] new_context points to the context to be restored.
1266 *
1267 * NOTE: May be unnecessary to reload some registers.
1268 *
1269 * Port Specific Information:
1270 *
1271 * XXX document implementation including references if appropriate
1272 */
1273void _CPU_Context_restore(
1274  Context_Control *new_context
1275) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1276
1277/**
1278 * @ingroup CPUContext
1279 *
1280 * This routine saves the floating point context passed to it.
1281 *
1282 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1283 * point context area
1284 *
1285 * @return on output @a *fp_context_ptr will contain the address that
1286 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1287 *
1288 * Port Specific Information:
1289 *
1290 * XXX document implementation including references if appropriate
1291 */
1292void _CPU_Context_save_fp(
1293  Context_Control_fp **fp_context_ptr
1294);
1295
1296/**
1297 * @ingroup CPUContext
1298 *
1299 * This routine restores the floating point context passed to it.
1300 *
1301 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1302 * point context area to restore
1303 *
1304 * @return on output @a *fp_context_ptr will contain the address that
1305 * should be used with @ref _CPU_Context_save_fp to save this context.
1306 *
1307 * Port Specific Information:
1308 *
1309 * XXX document implementation including references if appropriate
1310 */
1311void _CPU_Context_restore_fp(
1312  Context_Control_fp **fp_context_ptr
1313);
1314
1315/**
1316 * @ingroup CPUContext
1317 *
1318 * @brief Clobbers all volatile registers with values derived from the pattern
1319 * parameter.
1320 *
1321 * This function is used only in test sptests/spcontext01.
1322 *
1323 * @param[in] pattern Pattern used to generate distinct register values.
1324 *
1325 * @see _CPU_Context_validate().
1326 */
1327void _CPU_Context_volatile_clobber( uintptr_t pattern );
1328
1329/**
1330 * @ingroup CPUContext
1331 *
1332 * @brief Initializes and validates the CPU context with values derived from
1333 * the pattern parameter.
1334 *
1335 * This function will not return if the CPU context remains consistent.  In
1336 * case this function returns the CPU port is broken.
1337 *
1338 * This function is used only in test sptests/spcontext01.
1339 *
1340 * @param[in] pattern Pattern used to generate distinct register values.
1341 *
1342 * @see _CPU_Context_volatile_clobber().
1343 */
1344void _CPU_Context_validate( uintptr_t pattern );
1345
1346/**
1347 * @brief The set of registers that specifies the complete processor state.
1348 *
1349 * The CPU exception frame may be available in fatal error conditions like for
1350 * example illegal opcodes, instruction fetch errors, or data access errors.
1351 *
1352 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1353 * rtems_exception_frame_print().
1354 */
1355typedef struct {
1356  uint32_t processor_state_register;
1357  uint32_t integer_registers [1];
1358  double float_registers [1];
1359} CPU_Exception_frame;
1360
1361/**
1362 * @brief Prints the exception frame via printk().
1363 *
1364 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1365 */
1366void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1367
1368/**
1369 * @ingroup CPUEndian
1370 *
1371 * The following routine swaps the endian format of an unsigned int.
1372 * It must be static because it is referenced indirectly.
1373 *
1374 * This version will work on any processor, but if there is a better
1375 * way for your CPU PLEASE use it.  The most common way to do this is to:
1376 *
1377 *    swap least significant two bytes with 16-bit rotate
1378 *    swap upper and lower 16-bits
1379 *    swap most significant two bytes with 16-bit rotate
1380 *
1381 * Some CPUs have special instructions which swap a 32-bit quantity in
1382 * a single instruction (e.g. i486).  It is probably best to avoid
1383 * an "endian swapping control bit" in the CPU.  One good reason is
1384 * that interrupts would probably have to be disabled to ensure that
1385 * an interrupt does not try to access the same "chunk" with the wrong
1386 * endian.  Another good reason is that on some CPUs, the endian bit
1387 * endianness for ALL fetches -- both code and data -- so the code
1388 * will be fetched incorrectly.
1389 *
1390 * @param[in] value is the value to be swapped
1391 * @return the value after being endian swapped
1392 *
1393 * Port Specific Information:
1394 *
1395 * XXX document implementation including references if appropriate
1396 */
1397static inline uint32_t CPU_swap_u32(
1398  uint32_t value
1399)
1400{
1401  uint32_t byte1, byte2, byte3, byte4, swapped;
1402
1403  byte4 = (value >> 24) & 0xff;
1404  byte3 = (value >> 16) & 0xff;
1405  byte2 = (value >> 8)  & 0xff;
1406  byte1 =  value        & 0xff;
1407
1408  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1409  return swapped;
1410}
1411
1412/**
1413 * @ingroup CPUEndian
1414 *
1415 * This routine swaps a 16 bir quantity.
1416 *
1417 * @param[in] value is the value to be swapped
1418 * @return the value after being endian swapped
1419 */
1420#define CPU_swap_u16( value ) \
1421  (((value&0xff) << 8) | ((value >> 8)&0xff))
1422
1423#ifdef RTEMS_SMP
1424  /**
1425   * @brief Returns the index of the current processor.
1426   *
1427   * An architecture specific method must be used to obtain the index of the
1428   * current processor in the system.  The set of processor indices is the
1429   * range of integers starting with zero up to the processor count minus one.
1430   */
1431  RTEMS_COMPILER_PURE_ATTRIBUTE static inline uint32_t
1432    _CPU_SMP_Get_current_processor( void )
1433  {
1434    return 123;
1435  }
1436
1437  /**
1438   * @brief Sends an inter-processor interrupt to the specified target
1439   * processor.
1440   *
1441   * This operation is undefined for target processor indices out of range.
1442   *
1443   * @param[in] target_processor_index The target processor index.
1444   */
1445  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1446
1447  /**
1448   * @brief Broadcasts a processor event.
1449   *
1450   * Some architectures provide a low-level synchronization primitive for
1451   * processors in a multi-processor environment.  Processors waiting for this
1452   * event may go into a low-power state and stop generating system bus
1453   * transactions.  This function must ensure that preceding store operations
1454   * can be observed by other processors.
1455   *
1456   * @see _CPU_SMP_Processor_event_receive().
1457   */
1458  static inline void _CPU_SMP_Processor_event_broadcast( void )
1459  {
1460    __asm__ volatile ( "" : : : "memory" );
1461  }
1462
1463  /**
1464   * @brief Receives a processor event.
1465   *
1466   * This function will wait for the processor event and may wait forever if no
1467   * such event arrives.
1468   *
1469   * @see _CPU_SMP_Processor_event_broadcast().
1470   */
1471  static inline void _CPU_SMP_Processor_event_receive( void )
1472  {
1473    __asm__ volatile ( "" : : : "memory" );
1474  }
1475#endif
1476
1477#ifdef __cplusplus
1478}
1479#endif
1480
1481#endif
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