source: rtems/cpukit/score/cpu/no_cpu/rtems/score/cpu.h @ 03b7789

4.11
Last change on this file since 03b7789 was 03b7789, checked in by Sebastian Huber <sebastian.huber@…>, on Apr 26, 2014 at 1:09:10 PM

score: Statically initialize _ISR_Vector_table

  • Property mode set to 100644
File size: 50.1 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief NO_CPU Department Source
5 *
6 * This include file contains information pertaining to the NO_CPU
7 * processor.
8 */
9
10/*
11 *  This include file contains information pertaining to the XXX
12 *  processor.
13 *
14 *  @note This file is part of a porting template that is intended
15 *  to be used as the starting point when porting RTEMS to a new
16 *  CPU family.  The following needs to be done when using this as
17 *  the starting point for a new port:
18 *
19 *  + Anywhere there is an XXX, it should be replaced
20 *    with information about the CPU family being ported to.
21 *
22 *  + At the end of each comment section, there is a heading which
23 *    says "Port Specific Information:".  When porting to RTEMS,
24 *    add CPU family specific information in this section
25 */
26
27/*
28 *  COPYRIGHT (c) 1989-2008.
29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.org/license/LICENSE.
34 */
35
36#ifndef _RTEMS_SCORE_CPU_H
37#define _RTEMS_SCORE_CPU_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/types.h>
44#include <rtems/score/no_cpu.h>
45
46/* conditional compilation parameters */
47
48/**
49 * Should the calls to @ref _Thread_Enable_dispatch be inlined?
50 *
51 * If TRUE, then they are inlined.
52 * If FALSE, then a subroutine call is made.
53 *
54 * This conditional is an example of the classic trade-off of size
55 * versus speed.  Inlining the call (TRUE) typically increases the
56 * size of RTEMS while speeding up the enabling of dispatching.
57 *
58 * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
59 * only be 0 or 1 unless you are in an interrupt handler and that
60 * interrupt handler invokes the executive.]  When not inlined
61 * something calls @ref _Thread_Enable_dispatch which in turns calls
62 * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
63 * one subroutine call is avoided entirely.
64 *
65 * Port Specific Information:
66 *
67 * XXX document implementation including references if appropriate
68 */
69#define CPU_INLINE_ENABLE_DISPATCH       FALSE
70
71/**
72 * Should the body of the search loops in _Thread_queue_Enqueue_priority
73 * be unrolled one time?  In unrolled each iteration of the loop examines
74 * two "nodes" on the chain being searched.  Otherwise, only one node
75 * is examined per iteration.
76 *
77 * If TRUE, then the loops are unrolled.
78 * If FALSE, then the loops are not unrolled.
79 *
80 * The primary factor in making this decision is the cost of disabling
81 * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
82 * body of the loop.  On some CPUs, the flash is more expensive than
83 * one iteration of the loop body.  In this case, it might be desirable
84 * to unroll the loop.  It is important to note that on some CPUs, this
85 * code is the longest interrupt disable period in RTEMS.  So it is
86 * necessary to strike a balance when setting this parameter.
87 *
88 * Port Specific Information:
89 *
90 * XXX document implementation including references if appropriate
91 */
92#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
93
94/**
95 * Does RTEMS manage a dedicated interrupt stack in software?
96 *
97 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
98 * If FALSE, nothing is done.
99 *
100 * If the CPU supports a dedicated interrupt stack in hardware,
101 * then it is generally the responsibility of the BSP to allocate it
102 * and set it up.
103 *
104 * If the CPU does not support a dedicated interrupt stack, then
105 * the porter has two options: (1) execute interrupts on the
106 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
107 * interrupt stack.
108 *
109 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
110 *
111 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
112 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
113 * possible that both are FALSE for a particular CPU.  Although it
114 * is unclear what that would imply about the interrupt processing
115 * procedure on that CPU.
116 *
117 * Port Specific Information:
118 *
119 * XXX document implementation including references if appropriate
120 */
121#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
122
123/**
124 * Does the CPU follow the simple vectored interrupt model?
125 *
126 * If TRUE, then RTEMS allocates the vector table it internally manages.
127 * If FALSE, then the BSP is assumed to allocate and manage the vector
128 * table
129 *
130 * Port Specific Information:
131 *
132 * XXX document implementation including references if appropriate
133 */
134#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
135
136/**
137 * Does this CPU have hardware support for a dedicated interrupt stack?
138 *
139 * If TRUE, then it must be installed during initialization.
140 * If FALSE, then no installation is performed.
141 *
142 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
143 *
144 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
145 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
146 * possible that both are FALSE for a particular CPU.  Although it
147 * is unclear what that would imply about the interrupt processing
148 * procedure on that CPU.
149 *
150 * Port Specific Information:
151 *
152 * XXX document implementation including references if appropriate
153 */
154#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
155
156/**
157 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
158 *
159 * If TRUE, then the memory is allocated during initialization.
160 * If FALSE, then the memory is allocated during initialization.
161 *
162 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
163 *
164 * Port Specific Information:
165 *
166 * XXX document implementation including references if appropriate
167 */
168#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
169
170/**
171 * Does the RTEMS invoke the user's ISR with the vector number and
172 * a pointer to the saved interrupt frame (1) or just the vector
173 * number (0)?
174 *
175 * Port Specific Information:
176 *
177 * XXX document implementation including references if appropriate
178 */
179#define CPU_ISR_PASSES_FRAME_POINTER 0
180
181/**
182 * @def CPU_HARDWARE_FP
183 *
184 * Does the CPU have hardware floating point?
185 *
186 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
187 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
188 *
189 * If there is a FP coprocessor such as the i387 or mc68881, then
190 * the answer is TRUE.
191 *
192 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
193 * It indicates whether or not this CPU model has FP support.  For
194 * example, it would be possible to have an i386_nofp CPU model
195 * which set this to false to indicate that you have an i386 without
196 * an i387 and wish to leave floating point support out of RTEMS.
197 */
198
199/**
200 * @def CPU_SOFTWARE_FP
201 *
202 * Does the CPU have no hardware floating point and GCC provides a
203 * software floating point implementation which must be context
204 * switched?
205 *
206 * This feature conditional is used to indicate whether or not there
207 * is software implemented floating point that must be context
208 * switched.  The determination of whether or not this applies
209 * is very tool specific and the state saved/restored is also
210 * compiler specific.
211 *
212 * Port Specific Information:
213 *
214 * XXX document implementation including references if appropriate
215 */
216#if ( NO_CPU_HAS_FPU == 1 )
217#define CPU_HARDWARE_FP     TRUE
218#else
219#define CPU_HARDWARE_FP     FALSE
220#endif
221#define CPU_SOFTWARE_FP     FALSE
222
223/**
224 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
225 *
226 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
227 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
228 *
229 * So far, the only CPUs in which this option has been used are the
230 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
231 * gcc both implicitly used the floating point registers to perform
232 * integer multiplies.  Similarly, the PowerPC port of gcc has been
233 * seen to allocate floating point local variables and touch the FPU
234 * even when the flow through a subroutine (like vfprintf()) might
235 * not use floating point formats.
236 *
237 * If a function which you would not think utilize the FP unit DOES,
238 * then one can not easily predict which tasks will use the FP hardware.
239 * In this case, this option should be TRUE.
240 *
241 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
242 *
243 * Port Specific Information:
244 *
245 * XXX document implementation including references if appropriate
246 */
247#define CPU_ALL_TASKS_ARE_FP     TRUE
248
249/**
250 * Should the IDLE task have a floating point context?
251 *
252 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
253 * and it has a floating point context which is switched in and out.
254 * If FALSE, then the IDLE task does not have a floating point context.
255 *
256 * Setting this to TRUE negatively impacts the time required to preempt
257 * the IDLE task from an interrupt because the floating point context
258 * must be saved as part of the preemption.
259 *
260 * Port Specific Information:
261 *
262 * XXX document implementation including references if appropriate
263 */
264#define CPU_IDLE_TASK_IS_FP      FALSE
265
266/**
267 * Should the saving of the floating point registers be deferred
268 * until a context switch is made to another different floating point
269 * task?
270 *
271 * If TRUE, then the floating point context will not be stored until
272 * necessary.  It will remain in the floating point registers and not
273 * disturned until another floating point task is switched to.
274 *
275 * If FALSE, then the floating point context is saved when a floating
276 * point task is switched out and restored when the next floating point
277 * task is restored.  The state of the floating point registers between
278 * those two operations is not specified.
279 *
280 * If the floating point context does NOT have to be saved as part of
281 * interrupt dispatching, then it should be safe to set this to TRUE.
282 *
283 * Setting this flag to TRUE results in using a different algorithm
284 * for deciding when to save and restore the floating point context.
285 * The deferred FP switch algorithm minimizes the number of times
286 * the FP context is saved and restored.  The FP context is not saved
287 * until a context switch is made to another, different FP task.
288 * Thus in a system with only one FP task, the FP context will never
289 * be saved or restored.
290 *
291 * Port Specific Information:
292 *
293 * XXX document implementation including references if appropriate
294 */
295#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
296
297/**
298 * Does this port provide a CPU dependent IDLE task implementation?
299 *
300 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
301 * must be provided and is the default IDLE thread body instead of
302 * @ref _CPU_Thread_Idle_body.
303 *
304 * If FALSE, then use the generic IDLE thread body if the BSP does
305 * not provide one.
306 *
307 * This is intended to allow for supporting processors which have
308 * a low power or idle mode.  When the IDLE thread is executed, then
309 * the CPU can be powered down.
310 *
311 * The order of precedence for selecting the IDLE thread body is:
312 *
313 *   -#  BSP provided
314 *   -#  CPU dependent (if provided)
315 *   -#  generic (if no BSP and no CPU dependent)
316 *
317 * Port Specific Information:
318 *
319 * XXX document implementation including references if appropriate
320 */
321#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
322
323/**
324 * Does the stack grow up (toward higher addresses) or down
325 * (toward lower addresses)?
326 *
327 * If TRUE, then the grows upward.
328 * If FALSE, then the grows toward smaller addresses.
329 *
330 * Port Specific Information:
331 *
332 * XXX document implementation including references if appropriate
333 */
334#define CPU_STACK_GROWS_UP               TRUE
335
336/**
337 * The following is the variable attribute used to force alignment
338 * of critical RTEMS structures.  On some processors it may make
339 * sense to have these aligned on tighter boundaries than
340 * the minimum requirements of the compiler in order to have as
341 * much of the critical data area as possible in a cache line.
342 *
343 * The placement of this macro in the declaration of the variables
344 * is based on the syntactically requirements of the GNU C
345 * "__attribute__" extension.  For example with GNU C, use
346 * the following to force a structures to a 32 byte boundary.
347 *
348 *     __attribute__ ((aligned (32)))
349 *
350 * NOTE: Currently only the Priority Bit Map table uses this feature.
351 *       To benefit from using this, the data must be heavily
352 *       used so it will stay in the cache and used frequently enough
353 *       in the executive to justify turning this on.
354 *
355 * Port Specific Information:
356 *
357 * XXX document implementation including references if appropriate
358 */
359#define CPU_STRUCTURE_ALIGNMENT
360
361/**
362 * @defgroup CPUTimestamp Processor Dependent Timestamp Support
363 *
364 * This group assists in issues related to timestamp implementation.
365 *
366 * The port must choose exactly one of the following defines:
367 * - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
368 * - #define CPU_TIMESTAMP_USE_INT64 TRUE
369 * - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
370 *
371 * Performance of int64_t versus struct timespec
372 * =============================================
373 *
374 * On PowerPC/psim, inlined int64_t saves ~50 instructions on each
375 *   _Thread_Dispatch operation which results in a context switch.
376 *   This works out to be about 10% faster dispatches and 7.5% faster
377 *   blocking semaphore obtains.  The following numbers are in instructions
378 *   and from tm02 and tm26.
379 *
380 *                        timespec  int64  inlined int64
381 *   dispatch:              446      446      400
382 *   blocking sem obtain:   627      626      581
383 *
384 * On SPARC/sis, inlined int64_t shows the same percentage gains.
385 *   The following numbers are in microseconds and from tm02 and tm26.
386 *
387 *                        timespec  int64  inlined int64
388 *   dispatch:               59       61       53
389 *   blocking sem obtain:    98      100       92
390 *
391 * Inlining appears to have a tendency to increase the size of
392 *   some executables.
393 * Not inlining reduces the execution improvement but does not seem to
394 *   be an improvement on the PowerPC and SPARC. The struct timespec
395 *   and the executables with int64 not inlined are about the same size.
396 *
397 */
398/**@{**/
399
400/**
401 * Selects the timestamp implementation using struct timespec.
402 *
403 * Port Specific Information:
404 *
405 * XXX document implementation including references if appropriate
406 */
407#define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
408
409/**
410 * Selects the timestamp implementation using int64_t and no inlined methods.
411 *
412 * Port Specific Information:
413 *
414 * XXX document implementation including references if appropriate
415 */
416#define CPU_TIMESTAMP_USE_INT64 TRUE
417
418/**
419 * Selects the timestamp implementation using int64_t and inlined methods.
420 *
421 * Port Specific Information:
422 *
423 * XXX document implementation including references if appropriate
424 */
425#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
426
427/** @} */
428
429/**
430 * @defgroup CPUEndian Processor Dependent Endianness Support
431 *
432 * This group assists in issues related to processor endianness.
433 *
434 */
435/**@{**/
436
437/**
438 * Define what is required to specify how the network to host conversion
439 * routines are handled.
440 *
441 * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
442 * same values.
443 *
444 * @see CPU_LITTLE_ENDIAN
445 *
446 * Port Specific Information:
447 *
448 * XXX document implementation including references if appropriate
449 */
450#define CPU_BIG_ENDIAN                           TRUE
451
452/**
453 * Define what is required to specify how the network to host conversion
454 * routines are handled.
455 *
456 * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
457 * same values.
458 *
459 * @see CPU_BIG_ENDIAN
460 *
461 * Port Specific Information:
462 *
463 * XXX document implementation including references if appropriate
464 */
465#define CPU_LITTLE_ENDIAN                        FALSE
466
467/** @} */
468
469/**
470 * @ingroup CPUInterrupt
471 *
472 * The following defines the number of bits actually used in the
473 * interrupt field of the task mode.  How those bits map to the
474 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
475 *
476 * Port Specific Information:
477 *
478 * XXX document implementation including references if appropriate
479 */
480#define CPU_MODES_INTERRUPT_MASK   0x00000001
481
482/**
483 * @brief The size of the CPU specific per-CPU control.
484 *
485 * This define must be visible to assember files since it is used to derive
486 * structure offsets.
487 */
488#define CPU_PER_CPU_CONTROL_SIZE 0
489
490/*
491 *  Processor defined structures required for cpukit/score.
492 *
493 *  Port Specific Information:
494 *
495 *  XXX document implementation including references if appropriate
496 */
497
498/* may need to put some structures here.  */
499
500/**
501 * @brief The CPU specific per-CPU control.
502 *
503 * The CPU port can place here all state information that must be available and
504 * maintained for each CPU in the system.
505 */
506typedef struct {
507  /* CPU specific per-CPU state */
508} CPU_Per_CPU_control;
509
510/**
511 * @defgroup CPUContext Processor Dependent Context Management
512 *
513 * From the highest level viewpoint, there are 2 types of context to save.
514 *
515 *    -# Interrupt registers to save
516 *    -# Task level registers to save
517 *
518 * Since RTEMS handles integer and floating point contexts separately, this
519 * means we have the following 3 context items:
520 *
521 *    -# task level context stuff::  Context_Control
522 *    -# floating point task stuff:: Context_Control_fp
523 *    -# special interrupt level context :: CPU_Interrupt_frame
524 *
525 * On some processors, it is cost-effective to save only the callee
526 * preserved registers during a task context switch.  This means
527 * that the ISR code needs to save those registers which do not
528 * persist across function calls.  It is not mandatory to make this
529 * distinctions between the caller/callee saves registers for the
530 * purpose of minimizing context saved during task switch and on interrupts.
531 * If the cost of saving extra registers is minimal, simplicity is the
532 * choice.  Save the same context on interrupt entry as for tasks in
533 * this case.
534 *
535 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
536 * care should be used in designing the context area.
537 *
538 * On some CPUs with hardware floating point support, the Context_Control_fp
539 * structure will not be used or it simply consist of an array of a
540 * fixed number of bytes.   This is done when the floating point context
541 * is dumped by a "FP save context" type instruction and the format
542 * is not really defined by the CPU.  In this case, there is no need
543 * to figure out the exact format -- only the size.  Of course, although
544 * this is enough information for RTEMS, it is probably not enough for
545 * a debugger such as gdb.  But that is another problem.
546 *
547 * Port Specific Information:
548 *
549 * XXX document implementation including references if appropriate
550 *
551 */
552/**@{**/
553
554/**
555 * @ingroup Management
556 * This defines the minimal set of integer and processor state registers
557 * that must be saved during a voluntary context switch from one thread
558 * to another.
559 */
560typedef struct {
561    /**
562     * This field is a hint that a port will have a number of integer
563     * registers that need to be saved at a context switch.
564     */
565    uint32_t   some_integer_register;
566    /**
567     * This field is a hint that a port will have a number of system
568     * registers that need to be saved at a context switch.
569     */
570    uint32_t   some_system_register;
571
572    /**
573     * This field is a hint that a port will have a register that
574     * is the stack pointer.
575     */
576    uint32_t   stack_pointer;
577} Context_Control;
578
579/**
580 * @ingroup Management
581 *
582 * This macro returns the stack pointer associated with @a _context.
583 *
584 * @param[in] _context is the thread context area to access
585 *
586 * @return This method returns the stack pointer.
587 */
588#define _CPU_Context_Get_SP( _context ) \
589  (_context)->stack_pointer
590
591/**
592 * @ingroup Management
593 *
594 * This defines the complete set of floating point registers that must
595 * be saved during any context switch from one thread to another.
596 */
597typedef struct {
598    /** FPU registers are listed here */
599    double      some_float_register;
600} Context_Control_fp;
601
602/**
603 * @ingroup Management
604 *
605 * This defines the set of integer and processor state registers that must
606 * be saved during an interrupt.  This set does not include any which are
607 * in @ref Context_Control.
608 */
609typedef struct {
610    /**
611     * This field is a hint that a port will have a number of integer
612     * registers that need to be saved when an interrupt occurs or
613     * when a context switch occurs at the end of an ISR.
614     */
615    uint32_t   special_interrupt_register;
616} CPU_Interrupt_frame;
617
618/**
619 * This variable is optional.  It is used on CPUs on which it is difficult
620 * to generate an "uninitialized" FP context.  It is filled in by
621 * @ref _CPU_Initialize and copied into the task's FP context area during
622 * @ref _CPU_Context_Initialize.
623 *
624 * Port Specific Information:
625 *
626 * XXX document implementation including references if appropriate
627 */
628SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
629
630/** @} */
631
632/**
633 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
634 *
635 * On some CPUs, RTEMS supports a software managed interrupt stack.
636 * This stack is allocated by the Interrupt Manager and the switch
637 * is performed in @ref _ISR_Handler.  These variables contain pointers
638 * to the lowest and highest addresses in the chunk of memory allocated
639 * for the interrupt stack.  Since it is unknown whether the stack
640 * grows up or down (in general), this give the CPU dependent
641 * code the option of picking the version it wants to use.
642 *
643 * NOTE: These two variables are required if the macro
644 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
645 *
646 * Port Specific Information:
647 *
648 * XXX document implementation including references if appropriate
649 */
650
651/*
652 *  Nothing prevents the porter from declaring more CPU specific variables.
653 *
654 *  Port Specific Information:
655 *
656 *  XXX document implementation including references if appropriate
657 */
658
659/* XXX: if needed, put more variables here */
660
661/**
662 * @ingroup CPUContext
663 *
664 * The size of the floating point context area.  On some CPUs this
665 * will not be a "sizeof" because the format of the floating point
666 * area is not defined -- only the size is.  This is usually on
667 * CPUs with a "floating point save context" instruction.
668 *
669 * Port Specific Information:
670 *
671 * XXX document implementation including references if appropriate
672 */
673#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
674
675/**
676 * Amount of extra stack (above minimum stack size) required by
677 * MPCI receive server thread.  Remember that in a multiprocessor
678 * system this thread must exist and be able to process all directives.
679 *
680 * Port Specific Information:
681 *
682 * XXX document implementation including references if appropriate
683 */
684#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
685
686/**
687 * @ingroup CPUInterrupt
688 *
689 * This defines the number of entries in the _ISR_Vector_table managed by RTEMS
690 * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be a
691 * compile-time constant.
692 *
693 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
694 * FALSE.
695 */
696#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
697
698/**
699 * @ingroup CPUInterrupt
700 *
701 * This defines the highest interrupt vector number for this port in case
702 * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be less than
703 * CPU_INTERRUPT_NUMBER_OF_VECTORS.  It may be not a compile-time constant.
704 *
705 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
706 * FALSE.
707 */
708#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
709
710/**
711 * @ingroup CPUInterrupt
712 *
713 * This is defined if the port has a special way to report the ISR nesting
714 * level.  Most ports maintain the variable @a _ISR_Nest_level.
715 */
716#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
717
718/**
719 * @ingroup CPUContext
720 *
721 * Should be large enough to run all RTEMS tests.  This ensures
722 * that a "reasonable" small application should not have any problems.
723 *
724 * Port Specific Information:
725 *
726 * XXX document implementation including references if appropriate
727 */
728#define CPU_STACK_MINIMUM_SIZE          (1024*4)
729
730/**
731 * Size of a pointer.
732 *
733 * This must be an integer literal that can be used by the assembler.  This
734 * value will be used to calculate offsets of structure members.  These
735 * offsets will be used in assembler code.
736 */
737#define CPU_SIZEOF_POINTER         4
738
739/**
740 * CPU's worst alignment requirement for data types on a byte boundary.  This
741 * alignment does not take into account the requirements for the stack.  It
742 * must be a power of two greater than or equal to two.  The power of two
743 * requirement makes it possible to align values easily using simple bit
744 * operations.
745 *
746 * Port Specific Information:
747 *
748 * XXX document implementation including references if appropriate
749 */
750#define CPU_ALIGNMENT              8
751
752/**
753 * This number corresponds to the byte alignment requirement for the
754 * heap handler.  This alignment requirement may be stricter than that
755 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
756 * common for the heap to follow the same alignment requirement as
757 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
758 * the heap, then this should be set to @ref CPU_ALIGNMENT.
759 *
760 * NOTE:  It must be a power of two greater than or equal to two.  The
761 *        requirement to be a multiple of two is because the heap uses the
762 *        least significant field of the front and back flags to indicate that
763 *        a block is in use or free.  So you do not want any odd length blocks
764 *        really putting length data in that bit.
765 *
766 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
767 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
768 *        elements allocated from the heap meet all restrictions.
769 *
770 * Port Specific Information:
771 *
772 * XXX document implementation including references if appropriate
773 */
774#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
775
776/**
777 * This number corresponds to the byte alignment requirement for memory
778 * buffers allocated by the partition manager.  This alignment requirement
779 * may be stricter than that for the data types alignment specified by
780 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
781 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
782 * strict enough for the partition, then this should be set to
783 * @ref CPU_ALIGNMENT.
784 *
785 * NOTE:  This does not have to be a power of 2.  It does have to
786 *        be greater or equal to than @ref CPU_ALIGNMENT.
787 *
788 * Port Specific Information:
789 *
790 * XXX document implementation including references if appropriate
791 */
792#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
793
794/**
795 * This number corresponds to the byte alignment requirement for the
796 * stack.  This alignment requirement may be stricter than that for the
797 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
798 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
799 * set to 0.
800 *
801 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
802 *
803 * Port Specific Information:
804 *
805 * XXX document implementation including references if appropriate
806 */
807#define CPU_STACK_ALIGNMENT        0
808
809/*
810 *  ISR handler macros
811 */
812
813/**
814 * @ingroup CPUInterrupt
815 *
816 * Support routine to initialize the RTEMS vector table after it is allocated.
817 *
818 * Port Specific Information:
819 *
820 * XXX document implementation including references if appropriate
821 */
822#define _CPU_Initialize_vectors()
823
824/**
825 * @ingroup CPUInterrupt
826 *
827 * Disable all interrupts for an RTEMS critical section.  The previous
828 * level is returned in @a _isr_cookie.
829 *
830 * @param[out] _isr_cookie will contain the previous level cookie
831 *
832 * Port Specific Information:
833 *
834 * XXX document implementation including references if appropriate
835 */
836#define _CPU_ISR_Disable( _isr_cookie ) \
837  { \
838    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
839  }
840
841/**
842 * @ingroup CPUInterrupt
843 *
844 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
845 * This indicates the end of an RTEMS critical section.  The parameter
846 * @a _isr_cookie is not modified.
847 *
848 * @param[in] _isr_cookie contain the previous level cookie
849 *
850 * Port Specific Information:
851 *
852 * XXX document implementation including references if appropriate
853 */
854#define _CPU_ISR_Enable( _isr_cookie )  \
855  { \
856  }
857
858/**
859 * @ingroup CPUInterrupt
860 *
861 * This temporarily restores the interrupt to @a _isr_cookie before immediately
862 * disabling them again.  This is used to divide long RTEMS critical
863 * sections into two or more parts.  The parameter @a _isr_cookie is not
864 * modified.
865 *
866 * @param[in] _isr_cookie contain the previous level cookie
867 *
868 * Port Specific Information:
869 *
870 * XXX document implementation including references if appropriate
871 */
872#define _CPU_ISR_Flash( _isr_cookie ) \
873  { \
874  }
875
876/**
877 * @ingroup CPUInterrupt
878 *
879 * This routine and @ref _CPU_ISR_Get_level
880 * Map the interrupt level in task mode onto the hardware that the CPU
881 * actually provides.  Currently, interrupt levels which do not
882 * map onto the CPU in a generic fashion are undefined.  Someday,
883 * it would be nice if these were "mapped" by the application
884 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
885 * 8 - 255 would be available for bsp/application specific meaning.
886 * This could be used to manage a programmable interrupt controller
887 * via the rtems_task_mode directive.
888 *
889 * Port Specific Information:
890 *
891 * XXX document implementation including references if appropriate
892 */
893#define _CPU_ISR_Set_level( new_level ) \
894  { \
895  }
896
897/**
898 * @ingroup CPUInterrupt
899 *
900 * Return the current interrupt disable level for this task in
901 * the format used by the interrupt level portion of the task mode.
902 *
903 * NOTE: This routine usually must be implemented as a subroutine.
904 *
905 * Port Specific Information:
906 *
907 * XXX document implementation including references if appropriate
908 */
909uint32_t   _CPU_ISR_Get_level( void );
910
911/* end of ISR handler macros */
912
913/* Context handler macros */
914
915/**
916 *  @ingroup CPUContext
917 *
918 * Initialize the context to a state suitable for starting a
919 * task after a context restore operation.  Generally, this
920 * involves:
921 *
922 *    - setting a starting address
923 *    - preparing the stack
924 *    - preparing the stack and frame pointers
925 *    - setting the proper interrupt level in the context
926 *    - initializing the floating point context
927 *
928 * This routine generally does not set any unnecessary register
929 * in the context.  The state of the "general data" registers is
930 * undefined at task start time.
931 *
932 * @param[in] _the_context is the context structure to be initialized
933 * @param[in] _stack_base is the lowest physical address of this task's stack
934 * @param[in] _size is the size of this task's stack
935 * @param[in] _isr is the interrupt disable level
936 * @param[in] _entry_point is the thread's entry point.  This is
937 *        always @a _Thread_Handler
938 * @param[in] _is_fp is TRUE if the thread is to be a floating
939 *       point thread.  This is typically only used on CPUs where the
940 *       FPU may be easily disabled by software such as on the SPARC
941 *       where the PSR contains an enable FPU bit.
942 * @param[in] _tls_area The thread-local storage (TLS) area.
943 *
944 * Port Specific Information:
945 *
946 * XXX document implementation including references if appropriate
947 */
948#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
949                                 _isr, _entry_point, _is_fp, _tls_area ) \
950  { \
951  }
952
953/**
954 * This routine is responsible for somehow restarting the currently
955 * executing task.  If you are lucky, then all that is necessary
956 * is restoring the context.  Otherwise, there will need to be
957 * a special assembly routine which does something special in this
958 * case.  For many ports, simply adding a label to the restore path
959 * of @ref _CPU_Context_switch will work.  On other ports, it may be
960 * possibly to load a few arguments and jump to the restore path. It will
961 * not work if restarting self conflicts with the stack frame
962 * assumptions of restoring a context.
963 *
964 * Port Specific Information:
965 *
966 * XXX document implementation including references if appropriate
967 */
968#define _CPU_Context_Restart_self( _the_context ) \
969   _CPU_Context_restore( (_the_context) );
970
971/**
972 * @ingroup CPUContext
973 *
974 * The purpose of this macro is to allow the initial pointer into
975 * a floating point context area (used to save the floating point
976 * context) to be at an arbitrary place in the floating point
977 *context area.
978 *
979 * This is necessary because some FP units are designed to have
980 * their context saved as a stack which grows into lower addresses.
981 * Other FP units can be saved by simply moving registers into offsets
982 * from the base of the context area.  Finally some FP units provide
983 * a "dump context" instruction which could fill in from high to low
984 * or low to high based on the whim of the CPU designers.
985 *
986 * @param[in] _base is the lowest physical address of the floating point
987 *        context area
988 * @param[in] _offset is the offset into the floating point area
989 *
990 * Port Specific Information:
991 *
992 * XXX document implementation including references if appropriate
993 */
994#define _CPU_Context_Fp_start( _base, _offset ) \
995   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
996
997/**
998 * This routine initializes the FP context area passed to it to.
999 * There are a few standard ways in which to initialize the
1000 * floating point context.  The code included for this macro assumes
1001 * that this is a CPU in which a "initial" FP context was saved into
1002 * @a _CPU_Null_fp_context and it simply copies it to the destination
1003 * context passed to it.
1004 *
1005 * Other floating point context save/restore models include:
1006 *   -# not doing anything, and
1007 *   -# putting a "null FP status word" in the correct place in the FP context.
1008 *
1009 * @param[in] _destination is the floating point context area
1010 *
1011 * Port Specific Information:
1012 *
1013 * XXX document implementation including references if appropriate
1014 */
1015#define _CPU_Context_Initialize_fp( _destination ) \
1016  { \
1017   *(*(_destination)) = _CPU_Null_fp_context; \
1018  }
1019
1020/* end of Context handler macros */
1021
1022/* Fatal Error manager macros */
1023
1024/**
1025 * This routine copies _error into a known place -- typically a stack
1026 * location or a register, optionally disables interrupts, and
1027 * halts/stops the CPU.
1028 *
1029 * Port Specific Information:
1030 *
1031 * XXX document implementation including references if appropriate
1032 */
1033#define _CPU_Fatal_halt( _error ) \
1034  { \
1035  }
1036
1037/* end of Fatal Error manager macros */
1038
1039/* Bitfield handler macros */
1040
1041/**
1042 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1043 *
1044 * This set of routines are used to implement fast searches for
1045 * the most important ready task.
1046 *
1047 */
1048/**@{**/
1049
1050/**
1051 * This definition is set to TRUE if the port uses the generic bitfield
1052 * manipulation implementation.
1053 */
1054#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1055
1056/**
1057 * This definition is set to TRUE if the port uses the data tables provided
1058 * by the generic bitfield manipulation implementation.
1059 * This can occur when actually using the generic bitfield manipulation
1060 * implementation or when implementing the same algorithm in assembly
1061 * language for improved performance.  It is unlikely that a port will use
1062 * the data if it has a bitfield scan instruction.
1063 */
1064#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1065
1066/**
1067 * This routine sets @a _output to the bit number of the first bit
1068 * set in @a _value.  @a _value is of CPU dependent type
1069 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
1070 * wide although only the 16 least significant bits will be used.
1071 *
1072 * There are a number of variables in using a "find first bit" type
1073 * instruction.
1074 *
1075 *   -# What happens when run on a value of zero?
1076 *   -# Bits may be numbered from MSB to LSB or vice-versa.
1077 *   -# The numbering may be zero or one based.
1078 *   -# The "find first bit" instruction may search from MSB or LSB.
1079 *
1080 * RTEMS guarantees that (1) will never happen so it is not a concern.
1081 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1082 * @ref _CPU_Priority_bits_index.  These three form a set of routines
1083 * which must logically operate together.  Bits in the _value are
1084 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
1085 * The basic major and minor values calculated by @ref _Priority_Major
1086 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1087 * to properly range between the values returned by the "find first bit"
1088 * instruction.  This makes it possible for @ref _Priority_Get_highest to
1089 * calculate the major and directly index into the minor table.
1090 * This mapping is necessary to ensure that 0 (a high priority major/minor)
1091 * is the first bit found.
1092 *
1093 * This entire "find first bit" and mapping process depends heavily
1094 * on the manner in which a priority is broken into a major and minor
1095 * components with the major being the 4 MSB of a priority and minor
1096 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1097 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1098 * to the lowest priority.
1099 *
1100 * If your CPU does not have a "find first bit" instruction, then
1101 * there are ways to make do without it.  Here are a handful of ways
1102 * to implement this in software:
1103 *
1104@verbatim
1105      - a series of 16 bit test instructions
1106      - a "binary search using if's"
1107      - _number = 0
1108        if _value > 0x00ff
1109          _value >>=8
1110          _number = 8;
1111
1112        if _value > 0x0000f
1113          _value >=8
1114          _number += 4
1115
1116        _number += bit_set_table[ _value ]
1117@endverbatim
1118
1119 *   where bit_set_table[ 16 ] has values which indicate the first
1120 *     bit set
1121 *
1122 * @param[in] _value is the value to be scanned
1123 * @param[in] _output is the first bit set
1124 *
1125 * Port Specific Information:
1126 *
1127 * XXX document implementation including references if appropriate
1128 */
1129
1130#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1131#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1132  { \
1133    (_output) = 0;   /* do something to prevent warnings */ \
1134  }
1135#endif
1136
1137/** @} */
1138
1139/* end of Bitfield handler macros */
1140
1141/**
1142 * This routine builds the mask which corresponds to the bit fields
1143 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1144 * for that routine.
1145 *
1146 * Port Specific Information:
1147 *
1148 * XXX document implementation including references if appropriate
1149 */
1150#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1151
1152#define _CPU_Priority_Mask( _bit_number ) \
1153  ( 1 << (_bit_number) )
1154
1155#endif
1156
1157/**
1158 * @ingroup CPUBitfield
1159 *
1160 * This routine translates the bit numbers returned by
1161 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1162 * a major or minor component of a priority.  See the discussion
1163 * for that routine.
1164 *
1165 * @param[in] _priority is the major or minor number to translate
1166 *
1167 * Port Specific Information:
1168 *
1169 * XXX document implementation including references if appropriate
1170 */
1171#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1172
1173#define _CPU_Priority_bits_index( _priority ) \
1174  (_priority)
1175
1176#endif
1177
1178/* end of Priority handler macros */
1179
1180/* functions */
1181
1182/**
1183 * This routine performs CPU dependent initialization.
1184 *
1185 * Port Specific Information:
1186 *
1187 * XXX document implementation including references if appropriate
1188 */
1189void _CPU_Initialize(void);
1190
1191/**
1192 * @ingroup CPUInterrupt
1193 *
1194 * This routine installs a "raw" interrupt handler directly into the
1195 * processor's vector table.
1196 *
1197 * @param[in] vector is the vector number
1198 * @param[in] new_handler is the raw ISR handler to install
1199 * @param[in] old_handler is the previously installed ISR Handler
1200 *
1201 * Port Specific Information:
1202 *
1203 * XXX document implementation including references if appropriate
1204 */
1205void _CPU_ISR_install_raw_handler(
1206  uint32_t    vector,
1207  proc_ptr    new_handler,
1208  proc_ptr   *old_handler
1209);
1210
1211/**
1212 * @ingroup CPUInterrupt
1213 *
1214 * This routine installs an interrupt vector.
1215 *
1216 * @param[in] vector is the vector number
1217 * @param[in] new_handler is the RTEMS ISR handler to install
1218 * @param[in] old_handler is the previously installed ISR Handler
1219 *
1220 * Port Specific Information:
1221 *
1222 * XXX document implementation including references if appropriate
1223 */
1224void _CPU_ISR_install_vector(
1225  uint32_t    vector,
1226  proc_ptr    new_handler,
1227  proc_ptr   *old_handler
1228);
1229
1230/**
1231 * @ingroup CPUInterrupt
1232 * This routine installs the hardware interrupt stack pointer.
1233 *
1234 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1235 *        is TRUE.
1236 *
1237 * Port Specific Information:
1238 *
1239 * XXX document implementation including references if appropriate
1240 */
1241void _CPU_Install_interrupt_stack( void );
1242
1243/**
1244 * This routine is the CPU dependent IDLE thread body.
1245 *
1246 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1247 *         is TRUE.
1248 *
1249 * Port Specific Information:
1250 *
1251 * XXX document implementation including references if appropriate
1252 */
1253void *_CPU_Thread_Idle_body( uintptr_t ignored );
1254
1255/**
1256 * @ingroup CPUContext
1257 *
1258 * This routine switches from the run context to the heir context.
1259 *
1260 * @param[in] run points to the context of the currently executing task
1261 * @param[in] heir points to the context of the heir task
1262 *
1263 * Port Specific Information:
1264 *
1265 * XXX document implementation including references if appropriate
1266 */
1267void _CPU_Context_switch(
1268  Context_Control  *run,
1269  Context_Control  *heir
1270);
1271
1272/**
1273 * @ingroup CPUContext
1274 *
1275 * This routine is generally used only to restart self in an
1276 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1277 *
1278 * @param[in] new_context points to the context to be restored.
1279 *
1280 * NOTE: May be unnecessary to reload some registers.
1281 *
1282 * Port Specific Information:
1283 *
1284 * XXX document implementation including references if appropriate
1285 */
1286void _CPU_Context_restore(
1287  Context_Control *new_context
1288) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
1289
1290/**
1291 * @ingroup CPUContext
1292 *
1293 * This routine saves the floating point context passed to it.
1294 *
1295 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1296 * point context area
1297 *
1298 * @return on output @a *fp_context_ptr will contain the address that
1299 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1300 *
1301 * Port Specific Information:
1302 *
1303 * XXX document implementation including references if appropriate
1304 */
1305void _CPU_Context_save_fp(
1306  Context_Control_fp **fp_context_ptr
1307);
1308
1309/**
1310 * @ingroup CPUContext
1311 *
1312 * This routine restores the floating point context passed to it.
1313 *
1314 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1315 * point context area to restore
1316 *
1317 * @return on output @a *fp_context_ptr will contain the address that
1318 * should be used with @ref _CPU_Context_save_fp to save this context.
1319 *
1320 * Port Specific Information:
1321 *
1322 * XXX document implementation including references if appropriate
1323 */
1324void _CPU_Context_restore_fp(
1325  Context_Control_fp **fp_context_ptr
1326);
1327
1328/**
1329 * @ingroup CPUContext
1330 *
1331 * @brief Clobbers all volatile registers with values derived from the pattern
1332 * parameter.
1333 *
1334 * This function is used only in test sptests/spcontext01.
1335 *
1336 * @param[in] pattern Pattern used to generate distinct register values.
1337 *
1338 * @see _CPU_Context_validate().
1339 */
1340void _CPU_Context_volatile_clobber( uintptr_t pattern );
1341
1342/**
1343 * @ingroup CPUContext
1344 *
1345 * @brief Initializes and validates the CPU context with values derived from
1346 * the pattern parameter.
1347 *
1348 * This function will not return if the CPU context remains consistent.  In
1349 * case this function returns the CPU port is broken.
1350 *
1351 * This function is used only in test sptests/spcontext01.
1352 *
1353 * @param[in] pattern Pattern used to generate distinct register values.
1354 *
1355 * @see _CPU_Context_volatile_clobber().
1356 */
1357void _CPU_Context_validate( uintptr_t pattern );
1358
1359/**
1360 * @brief The set of registers that specifies the complete processor state.
1361 *
1362 * The CPU exception frame may be available in fatal error conditions like for
1363 * example illegal opcodes, instruction fetch errors, or data access errors.
1364 *
1365 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1366 * rtems_exception_frame_print().
1367 */
1368typedef struct {
1369  uint32_t processor_state_register;
1370  uint32_t integer_registers [1];
1371  double float_registers [1];
1372} CPU_Exception_frame;
1373
1374/**
1375 * @brief Prints the exception frame via printk().
1376 *
1377 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1378 */
1379void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1380
1381/**
1382 * @ingroup CPUEndian
1383 *
1384 * The following routine swaps the endian format of an unsigned int.
1385 * It must be static because it is referenced indirectly.
1386 *
1387 * This version will work on any processor, but if there is a better
1388 * way for your CPU PLEASE use it.  The most common way to do this is to:
1389 *
1390 *    swap least significant two bytes with 16-bit rotate
1391 *    swap upper and lower 16-bits
1392 *    swap most significant two bytes with 16-bit rotate
1393 *
1394 * Some CPUs have special instructions which swap a 32-bit quantity in
1395 * a single instruction (e.g. i486).  It is probably best to avoid
1396 * an "endian swapping control bit" in the CPU.  One good reason is
1397 * that interrupts would probably have to be disabled to ensure that
1398 * an interrupt does not try to access the same "chunk" with the wrong
1399 * endian.  Another good reason is that on some CPUs, the endian bit
1400 * endianness for ALL fetches -- both code and data -- so the code
1401 * will be fetched incorrectly.
1402 *
1403 * @param[in] value is the value to be swapped
1404 * @return the value after being endian swapped
1405 *
1406 * Port Specific Information:
1407 *
1408 * XXX document implementation including references if appropriate
1409 */
1410static inline uint32_t CPU_swap_u32(
1411  uint32_t value
1412)
1413{
1414  uint32_t byte1, byte2, byte3, byte4, swapped;
1415
1416  byte4 = (value >> 24) & 0xff;
1417  byte3 = (value >> 16) & 0xff;
1418  byte2 = (value >> 8)  & 0xff;
1419  byte1 =  value        & 0xff;
1420
1421  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1422  return swapped;
1423}
1424
1425/**
1426 * @ingroup CPUEndian
1427 *
1428 * This routine swaps a 16 bir quantity.
1429 *
1430 * @param[in] value is the value to be swapped
1431 * @return the value after being endian swapped
1432 */
1433#define CPU_swap_u16( value ) \
1434  (((value&0xff) << 8) | ((value >> 8)&0xff))
1435
1436/**
1437 * @brief Unsigned integer type for CPU counter values.
1438 */
1439typedef uint32_t CPU_Counter_ticks;
1440
1441/**
1442 * @brief Returns the current CPU counter value.
1443 *
1444 * A CPU counter is some free-running counter.  It ticks usually with a
1445 * frequency close to the CPU or system bus clock.  The board support package
1446 * must ensure that this function works before the RTEMS initialization.
1447 * Otherwise invalid profiling statistics will be gathered.
1448 *
1449 * @return The current CPU counter value.
1450 */
1451CPU_Counter_ticks _CPU_Counter_read( void );
1452
1453/**
1454 * @brief Returns the difference between the second and first CPU counter
1455 * value.
1456 *
1457 * This operation may be carried out as a modulo operation depending on the
1458 * range of the CPU counter device.
1459 *
1460 * @param[in] second The second CPU counter value.
1461 * @param[in] first The first CPU counter value.
1462 *
1463 * @return Returns second minus first modulo counter period.
1464 */
1465CPU_Counter_ticks _CPU_Counter_difference(
1466  CPU_Counter_ticks second,
1467  CPU_Counter_ticks first
1468);
1469
1470/**
1471 * @brief Special register pointing to the per-CPU control of the current
1472 * processor.
1473 *
1474 * This is optional.  Not every CPU port needs this.  It is only an optional
1475 * optimization variant.
1476 */
1477register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" );
1478
1479/**
1480 * @brief Optional method to obtain the per-CPU control of the current processor.
1481 *
1482 * This is optional.  Not every CPU port needs this.  It is only an optional
1483 * optimization variant.  In case this macro is undefined, the default
1484 * implementation using the current processor index will be used.
1485 */
1486#define _CPU_Get_current_per_CPU_control() ( _CPU_Per_CPU_current )
1487
1488#ifdef RTEMS_SMP
1489  /**
1490   * @brief Performs CPU specific SMP initialization in the context of the boot
1491   * processor.
1492   *
1493   * This function is invoked on the boot processor during system
1494   * initialization.  All interrupt stacks are allocated at this point in case
1495   * the CPU port allocates the interrupt stacks.  This function is called
1496   * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
1497   * used.
1498   *
1499   * @return The count of physically or virtually available processors.
1500   * Depending on the configuration the application may use not all processors.
1501   */
1502  uint32_t _CPU_SMP_Initialize( void );
1503
1504  /**
1505   * @brief Starts a processor specified by its index.
1506   *
1507   * This function is invoked on the boot processor during system
1508   * initialization.
1509   *
1510   * This function will be called after _CPU_SMP_Initialize().
1511   *
1512   * @param[in] cpu_index The processor index.
1513   *
1514   * @retval true Successful operation.
1515   * @retval false Unable to start this processor.
1516   */
1517  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1518
1519  /**
1520   * @brief Performs final steps of CPU specific SMP initialization in the
1521   * context of the boot processor.
1522   *
1523   * This function is invoked on the boot processor during system
1524   * initialization.
1525   *
1526   * This function will be called after all processors requested by the
1527   * application have been started.
1528   *
1529   * @param[in] cpu_count The minimum value of the count of processors
1530   * requested by the application configuration and the count of physically or
1531   * virtually available processors.
1532   */
1533  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1534
1535  /**
1536   * @brief Returns the index of the current processor.
1537   *
1538   * An architecture specific method must be used to obtain the index of the
1539   * current processor in the system.  The set of processor indices is the
1540   * range of integers starting with zero up to the processor count minus one.
1541   */
1542  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1543  {
1544    return 123;
1545  }
1546
1547  /**
1548   * @brief Sends an inter-processor interrupt to the specified target
1549   * processor.
1550   *
1551   * This operation is undefined for target processor indices out of range.
1552   *
1553   * @param[in] target_processor_index The target processor index.
1554   */
1555  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1556
1557  /**
1558   * @brief Broadcasts a processor event.
1559   *
1560   * Some architectures provide a low-level synchronization primitive for
1561   * processors in a multi-processor environment.  Processors waiting for this
1562   * event may go into a low-power state and stop generating system bus
1563   * transactions.  This function must ensure that preceding store operations
1564   * can be observed by other processors.
1565   *
1566   * @see _CPU_SMP_Processor_event_receive().
1567   */
1568  static inline void _CPU_SMP_Processor_event_broadcast( void )
1569  {
1570    __asm__ volatile ( "" : : : "memory" );
1571  }
1572
1573  /**
1574   * @brief Receives a processor event.
1575   *
1576   * This function will wait for the processor event and may wait forever if no
1577   * such event arrives.
1578   *
1579   * @see _CPU_SMP_Processor_event_broadcast().
1580   */
1581  static inline void _CPU_SMP_Processor_event_receive( void )
1582  {
1583    __asm__ volatile ( "" : : : "memory" );
1584  }
1585#endif
1586
1587#ifdef __cplusplus
1588}
1589#endif
1590
1591#endif
Note: See TracBrowser for help on using the repository browser.