1 | /** |
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2 | * @file rtems/score/cpu.h |
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3 | * |
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4 | * @brief NO_CPU Department Source |
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5 | * |
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6 | * This include file contains information pertaining to the NO_CPU |
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7 | * processor. |
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8 | */ |
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9 | |
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10 | /* |
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11 | * This include file contains information pertaining to the XXX |
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12 | * processor. |
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13 | * |
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14 | * @note This file is part of a porting template that is intended |
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15 | * to be used as the starting point when porting RTEMS to a new |
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16 | * CPU family. The following needs to be done when using this as |
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17 | * the starting point for a new port: |
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18 | * |
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19 | * + Anywhere there is an XXX, it should be replaced |
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20 | * with information about the CPU family being ported to. |
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21 | * |
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22 | * + At the end of each comment section, there is a heading which |
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23 | * says "Port Specific Information:". When porting to RTEMS, |
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24 | * add CPU family specific information in this section |
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25 | */ |
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26 | |
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27 | /* |
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28 | * COPYRIGHT (c) 1989-2008. |
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29 | * On-Line Applications Research Corporation (OAR). |
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30 | * |
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31 | * The license and distribution terms for this file may be |
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32 | * found in the file LICENSE in this distribution or at |
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33 | * http://www.rtems.org/license/LICENSE. |
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34 | */ |
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35 | |
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36 | #ifndef _RTEMS_SCORE_CPU_H |
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37 | #define _RTEMS_SCORE_CPU_H |
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38 | |
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39 | #ifdef __cplusplus |
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40 | extern "C" { |
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41 | #endif |
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42 | |
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43 | #include <rtems/score/types.h> |
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44 | #include <rtems/score/no_cpu.h> |
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45 | |
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46 | /* conditional compilation parameters */ |
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47 | |
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48 | /** |
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49 | * Should the calls to @ref _Thread_Enable_dispatch be inlined? |
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50 | * |
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51 | * If TRUE, then they are inlined. |
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52 | * If FALSE, then a subroutine call is made. |
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53 | * |
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54 | * This conditional is an example of the classic trade-off of size |
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55 | * versus speed. Inlining the call (TRUE) typically increases the |
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56 | * size of RTEMS while speeding up the enabling of dispatching. |
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57 | * |
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58 | * NOTE: In general, the @ref _Thread_Dispatch_disable_level will |
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59 | * only be 0 or 1 unless you are in an interrupt handler and that |
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60 | * interrupt handler invokes the executive.] When not inlined |
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61 | * something calls @ref _Thread_Enable_dispatch which in turns calls |
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62 | * @ref _Thread_Dispatch. If the enable dispatch is inlined, then |
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63 | * one subroutine call is avoided entirely. |
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64 | * |
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65 | * Port Specific Information: |
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66 | * |
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67 | * XXX document implementation including references if appropriate |
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68 | */ |
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69 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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70 | |
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71 | /** |
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72 | * Does RTEMS manage a dedicated interrupt stack in software? |
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73 | * |
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74 | * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. |
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75 | * If FALSE, nothing is done. |
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76 | * |
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77 | * If the CPU supports a dedicated interrupt stack in hardware, |
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78 | * then it is generally the responsibility of the BSP to allocate it |
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79 | * and set it up. |
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80 | * |
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81 | * If the CPU does not support a dedicated interrupt stack, then |
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82 | * the porter has two options: (1) execute interrupts on the |
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83 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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84 | * interrupt stack. |
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85 | * |
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86 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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87 | * |
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88 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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89 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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90 | * possible that both are FALSE for a particular CPU. Although it |
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91 | * is unclear what that would imply about the interrupt processing |
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92 | * procedure on that CPU. |
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93 | * |
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94 | * Port Specific Information: |
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95 | * |
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96 | * XXX document implementation including references if appropriate |
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97 | */ |
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98 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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99 | |
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100 | /** |
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101 | * Does the CPU follow the simple vectored interrupt model? |
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102 | * |
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103 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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104 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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105 | * table |
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106 | * |
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107 | * Port Specific Information: |
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108 | * |
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109 | * XXX document implementation including references if appropriate |
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110 | */ |
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111 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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112 | |
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113 | /** |
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114 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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115 | * |
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116 | * If TRUE, then it must be installed during initialization. |
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117 | * If FALSE, then no installation is performed. |
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118 | * |
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119 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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120 | * |
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121 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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122 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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123 | * possible that both are FALSE for a particular CPU. Although it |
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124 | * is unclear what that would imply about the interrupt processing |
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125 | * procedure on that CPU. |
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126 | * |
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127 | * Port Specific Information: |
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128 | * |
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129 | * XXX document implementation including references if appropriate |
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130 | */ |
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131 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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132 | |
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133 | /** |
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134 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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135 | * |
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136 | * If TRUE, then the memory is allocated during initialization. |
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137 | * If FALSE, then the memory is allocated during initialization. |
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138 | * |
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139 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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140 | * |
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141 | * Port Specific Information: |
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142 | * |
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143 | * XXX document implementation including references if appropriate |
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144 | */ |
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145 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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146 | |
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147 | /** |
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148 | * Does the RTEMS invoke the user's ISR with the vector number and |
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149 | * a pointer to the saved interrupt frame (1) or just the vector |
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150 | * number (0)? |
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151 | * |
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152 | * Port Specific Information: |
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153 | * |
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154 | * XXX document implementation including references if appropriate |
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155 | */ |
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156 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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157 | |
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158 | /** |
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159 | * @def CPU_HARDWARE_FP |
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160 | * |
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161 | * Does the CPU have hardware floating point? |
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162 | * |
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163 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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164 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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165 | * |
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166 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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167 | * the answer is TRUE. |
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168 | * |
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169 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
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170 | * It indicates whether or not this CPU model has FP support. For |
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171 | * example, it would be possible to have an i386_nofp CPU model |
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172 | * which set this to false to indicate that you have an i386 without |
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173 | * an i387 and wish to leave floating point support out of RTEMS. |
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174 | */ |
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175 | |
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176 | /** |
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177 | * @def CPU_SOFTWARE_FP |
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178 | * |
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179 | * Does the CPU have no hardware floating point and GCC provides a |
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180 | * software floating point implementation which must be context |
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181 | * switched? |
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182 | * |
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183 | * This feature conditional is used to indicate whether or not there |
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184 | * is software implemented floating point that must be context |
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185 | * switched. The determination of whether or not this applies |
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186 | * is very tool specific and the state saved/restored is also |
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187 | * compiler specific. |
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188 | * |
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189 | * Port Specific Information: |
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190 | * |
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191 | * XXX document implementation including references if appropriate |
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192 | */ |
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193 | #if ( NO_CPU_HAS_FPU == 1 ) |
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194 | #define CPU_HARDWARE_FP TRUE |
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195 | #else |
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196 | #define CPU_HARDWARE_FP FALSE |
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197 | #endif |
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198 | #define CPU_SOFTWARE_FP FALSE |
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199 | |
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200 | /** |
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201 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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202 | * |
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203 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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204 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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205 | * |
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206 | * So far, the only CPUs in which this option has been used are the |
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207 | * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and |
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208 | * gcc both implicitly used the floating point registers to perform |
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209 | * integer multiplies. Similarly, the PowerPC port of gcc has been |
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210 | * seen to allocate floating point local variables and touch the FPU |
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211 | * even when the flow through a subroutine (like vfprintf()) might |
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212 | * not use floating point formats. |
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213 | * |
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214 | * If a function which you would not think utilize the FP unit DOES, |
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215 | * then one can not easily predict which tasks will use the FP hardware. |
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216 | * In this case, this option should be TRUE. |
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217 | * |
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218 | * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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219 | * |
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220 | * Port Specific Information: |
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221 | * |
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222 | * XXX document implementation including references if appropriate |
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223 | */ |
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224 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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225 | |
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226 | /** |
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227 | * Should the IDLE task have a floating point context? |
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228 | * |
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229 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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230 | * and it has a floating point context which is switched in and out. |
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231 | * If FALSE, then the IDLE task does not have a floating point context. |
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232 | * |
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233 | * Setting this to TRUE negatively impacts the time required to preempt |
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234 | * the IDLE task from an interrupt because the floating point context |
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235 | * must be saved as part of the preemption. |
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236 | * |
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237 | * Port Specific Information: |
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238 | * |
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239 | * XXX document implementation including references if appropriate |
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240 | */ |
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241 | #define CPU_IDLE_TASK_IS_FP FALSE |
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242 | |
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243 | /** |
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244 | * Should the saving of the floating point registers be deferred |
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245 | * until a context switch is made to another different floating point |
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246 | * task? |
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247 | * |
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248 | * If TRUE, then the floating point context will not be stored until |
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249 | * necessary. It will remain in the floating point registers and not |
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250 | * disturned until another floating point task is switched to. |
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251 | * |
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252 | * If FALSE, then the floating point context is saved when a floating |
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253 | * point task is switched out and restored when the next floating point |
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254 | * task is restored. The state of the floating point registers between |
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255 | * those two operations is not specified. |
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256 | * |
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257 | * If the floating point context does NOT have to be saved as part of |
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258 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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259 | * |
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260 | * Setting this flag to TRUE results in using a different algorithm |
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261 | * for deciding when to save and restore the floating point context. |
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262 | * The deferred FP switch algorithm minimizes the number of times |
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263 | * the FP context is saved and restored. The FP context is not saved |
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264 | * until a context switch is made to another, different FP task. |
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265 | * Thus in a system with only one FP task, the FP context will never |
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266 | * be saved or restored. |
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267 | * |
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268 | * Port Specific Information: |
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269 | * |
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270 | * XXX document implementation including references if appropriate |
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271 | */ |
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272 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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273 | |
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274 | /** |
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275 | * Does this port provide a CPU dependent IDLE task implementation? |
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276 | * |
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277 | * If TRUE, then the routine @ref _CPU_Thread_Idle_body |
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278 | * must be provided and is the default IDLE thread body instead of |
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279 | * @ref _CPU_Thread_Idle_body. |
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280 | * |
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281 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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282 | * not provide one. |
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283 | * |
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284 | * This is intended to allow for supporting processors which have |
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285 | * a low power or idle mode. When the IDLE thread is executed, then |
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286 | * the CPU can be powered down. |
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287 | * |
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288 | * The order of precedence for selecting the IDLE thread body is: |
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289 | * |
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290 | * -# BSP provided |
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291 | * -# CPU dependent (if provided) |
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292 | * -# generic (if no BSP and no CPU dependent) |
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293 | * |
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294 | * Port Specific Information: |
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295 | * |
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296 | * XXX document implementation including references if appropriate |
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297 | */ |
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298 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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299 | |
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300 | /** |
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301 | * Does the stack grow up (toward higher addresses) or down |
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302 | * (toward lower addresses)? |
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303 | * |
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304 | * If TRUE, then the grows upward. |
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305 | * If FALSE, then the grows toward smaller addresses. |
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306 | * |
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307 | * Port Specific Information: |
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308 | * |
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309 | * XXX document implementation including references if appropriate |
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310 | */ |
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311 | #define CPU_STACK_GROWS_UP TRUE |
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312 | |
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313 | /** |
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314 | * The following is the variable attribute used to force alignment |
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315 | * of critical RTEMS structures. On some processors it may make |
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316 | * sense to have these aligned on tighter boundaries than |
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317 | * the minimum requirements of the compiler in order to have as |
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318 | * much of the critical data area as possible in a cache line. |
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319 | * |
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320 | * The placement of this macro in the declaration of the variables |
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321 | * is based on the syntactically requirements of the GNU C |
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322 | * "__attribute__" extension. For example with GNU C, use |
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323 | * the following to force a structures to a 32 byte boundary. |
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324 | * |
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325 | * __attribute__ ((aligned (32))) |
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326 | * |
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327 | * NOTE: Currently only the Priority Bit Map table uses this feature. |
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328 | * To benefit from using this, the data must be heavily |
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329 | * used so it will stay in the cache and used frequently enough |
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330 | * in the executive to justify turning this on. |
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331 | * |
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332 | * Port Specific Information: |
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333 | * |
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334 | * XXX document implementation including references if appropriate |
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335 | */ |
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336 | #define CPU_STRUCTURE_ALIGNMENT |
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337 | |
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338 | /** |
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339 | * @defgroup CPUEndian Processor Dependent Endianness Support |
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340 | * |
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341 | * This group assists in issues related to processor endianness. |
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342 | * |
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343 | */ |
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344 | /**@{**/ |
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345 | |
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346 | /** |
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347 | * Define what is required to specify how the network to host conversion |
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348 | * routines are handled. |
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349 | * |
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350 | * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the |
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351 | * same values. |
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352 | * |
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353 | * @see CPU_LITTLE_ENDIAN |
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354 | * |
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355 | * Port Specific Information: |
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356 | * |
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357 | * XXX document implementation including references if appropriate |
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358 | */ |
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359 | #define CPU_BIG_ENDIAN TRUE |
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360 | |
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361 | /** |
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362 | * Define what is required to specify how the network to host conversion |
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363 | * routines are handled. |
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364 | * |
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365 | * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the |
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366 | * same values. |
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367 | * |
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368 | * @see CPU_BIG_ENDIAN |
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369 | * |
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370 | * Port Specific Information: |
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371 | * |
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372 | * XXX document implementation including references if appropriate |
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373 | */ |
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374 | #define CPU_LITTLE_ENDIAN FALSE |
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375 | |
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376 | /** @} */ |
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377 | |
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378 | /** |
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379 | * @ingroup CPUInterrupt |
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380 | * |
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381 | * The following defines the number of bits actually used in the |
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382 | * interrupt field of the task mode. How those bits map to the |
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383 | * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. |
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384 | * |
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385 | * Port Specific Information: |
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386 | * |
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387 | * XXX document implementation including references if appropriate |
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388 | */ |
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389 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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390 | |
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391 | /** |
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392 | * @brief The size of the CPU specific per-CPU control. |
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393 | * |
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394 | * This define must be visible to assember files since it is used to derive |
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395 | * structure offsets. |
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396 | */ |
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397 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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398 | |
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399 | /* |
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400 | * Processor defined structures required for cpukit/score. |
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401 | * |
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402 | * Port Specific Information: |
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403 | * |
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404 | * XXX document implementation including references if appropriate |
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405 | */ |
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406 | |
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407 | /* may need to put some structures here. */ |
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408 | |
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409 | /** |
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410 | * @brief The CPU specific per-CPU control. |
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411 | * |
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412 | * The CPU port can place here all state information that must be available and |
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413 | * maintained for each CPU in the system. |
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414 | */ |
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415 | typedef struct { |
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416 | /* CPU specific per-CPU state */ |
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417 | } CPU_Per_CPU_control; |
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418 | |
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419 | /** |
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420 | * @defgroup CPUContext Processor Dependent Context Management |
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421 | * |
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422 | * From the highest level viewpoint, there are 2 types of context to save. |
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423 | * |
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424 | * -# Interrupt registers to save |
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425 | * -# Task level registers to save |
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426 | * |
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427 | * Since RTEMS handles integer and floating point contexts separately, this |
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428 | * means we have the following 3 context items: |
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429 | * |
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430 | * -# task level context stuff:: Context_Control |
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431 | * -# floating point task stuff:: Context_Control_fp |
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432 | * -# special interrupt level context :: CPU_Interrupt_frame |
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433 | * |
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434 | * On some processors, it is cost-effective to save only the callee |
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435 | * preserved registers during a task context switch. This means |
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436 | * that the ISR code needs to save those registers which do not |
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437 | * persist across function calls. It is not mandatory to make this |
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438 | * distinctions between the caller/callee saves registers for the |
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439 | * purpose of minimizing context saved during task switch and on interrupts. |
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440 | * If the cost of saving extra registers is minimal, simplicity is the |
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441 | * choice. Save the same context on interrupt entry as for tasks in |
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442 | * this case. |
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443 | * |
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444 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
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445 | * care should be used in designing the context area. |
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446 | * |
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447 | * On some CPUs with hardware floating point support, the Context_Control_fp |
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448 | * structure will not be used or it simply consist of an array of a |
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449 | * fixed number of bytes. This is done when the floating point context |
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450 | * is dumped by a "FP save context" type instruction and the format |
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451 | * is not really defined by the CPU. In this case, there is no need |
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452 | * to figure out the exact format -- only the size. Of course, although |
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453 | * this is enough information for RTEMS, it is probably not enough for |
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454 | * a debugger such as gdb. But that is another problem. |
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455 | * |
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456 | * Port Specific Information: |
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457 | * |
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458 | * XXX document implementation including references if appropriate |
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459 | * |
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460 | */ |
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461 | /**@{**/ |
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462 | |
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463 | /** |
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464 | * @ingroup Management |
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465 | * This defines the minimal set of integer and processor state registers |
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466 | * that must be saved during a voluntary context switch from one thread |
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467 | * to another. |
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468 | */ |
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469 | typedef struct { |
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470 | /** |
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471 | * This field is a hint that a port will have a number of integer |
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472 | * registers that need to be saved at a context switch. |
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473 | */ |
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474 | uint32_t some_integer_register; |
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475 | /** |
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476 | * This field is a hint that a port will have a number of system |
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477 | * registers that need to be saved at a context switch. |
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478 | */ |
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479 | uint32_t some_system_register; |
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480 | |
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481 | /** |
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482 | * This field is a hint that a port will have a register that |
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483 | * is the stack pointer. |
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484 | */ |
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485 | uint32_t stack_pointer; |
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486 | |
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487 | #ifdef RTEMS_SMP |
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488 | /** |
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489 | * @brief On SMP configurations the thread context must contain a boolean |
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490 | * indicator to signal if this context is executing on a processor. |
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491 | * |
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492 | * This field must be updated during a context switch. The context switch |
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493 | * to the heir must wait until the heir context indicates that it is no |
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494 | * longer executing on a processor. This indicator must be updated using |
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495 | * an atomic test and set operation to ensure that at most one processor |
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496 | * uses the heir context at the same time. The context switch must also |
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497 | * check for a potential new heir thread for this processor in case the |
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498 | * heir context is not immediately available. Update the executing thread |
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499 | * for this processor only if necessary to avoid a cache line |
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500 | * monopolization. |
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501 | * |
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502 | * @code |
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503 | * void _CPU_Context_switch( |
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504 | * Context_Control *executing_context, |
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505 | * Context_Control *heir_context |
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506 | * ) |
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507 | * { |
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508 | * save( executing_context ); |
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509 | * |
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510 | * executing_context->is_executing = false; |
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511 | * memory_barrier(); |
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512 | * |
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513 | * if ( test_and_set( &heir_context->is_executing ) ) { |
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514 | * do { |
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515 | * Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot(); |
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516 | * Thread_Control *executing = cpu_self->executing; |
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517 | * Thread_Control *heir = cpu_self->heir; |
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518 | * |
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519 | * if ( heir != executing ) { |
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520 | * cpu_self->executing = heir; |
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521 | * heir_context = (Context_Control *) |
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522 | * ((uintptr_t) heir + (uintptr_t) executing_context |
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523 | * - (uintptr_t) executing) |
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524 | * } |
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525 | * } while ( test_and_set( &heir_context->is_executing ) ); |
---|
526 | * } |
---|
527 | * |
---|
528 | * restore( heir_context ); |
---|
529 | * } |
---|
530 | * @endcode |
---|
531 | */ |
---|
532 | volatile bool is_executing; |
---|
533 | #endif |
---|
534 | } Context_Control; |
---|
535 | |
---|
536 | /** |
---|
537 | * @ingroup Management |
---|
538 | * |
---|
539 | * This macro returns the stack pointer associated with @a _context. |
---|
540 | * |
---|
541 | * @param[in] _context is the thread context area to access |
---|
542 | * |
---|
543 | * @return This method returns the stack pointer. |
---|
544 | */ |
---|
545 | #define _CPU_Context_Get_SP( _context ) \ |
---|
546 | (_context)->stack_pointer |
---|
547 | |
---|
548 | /** |
---|
549 | * @ingroup Management |
---|
550 | * |
---|
551 | * This defines the complete set of floating point registers that must |
---|
552 | * be saved during any context switch from one thread to another. |
---|
553 | */ |
---|
554 | typedef struct { |
---|
555 | /** FPU registers are listed here */ |
---|
556 | double some_float_register; |
---|
557 | } Context_Control_fp; |
---|
558 | |
---|
559 | /** |
---|
560 | * @ingroup Management |
---|
561 | * |
---|
562 | * This defines the set of integer and processor state registers that must |
---|
563 | * be saved during an interrupt. This set does not include any which are |
---|
564 | * in @ref Context_Control. |
---|
565 | */ |
---|
566 | typedef struct { |
---|
567 | /** |
---|
568 | * This field is a hint that a port will have a number of integer |
---|
569 | * registers that need to be saved when an interrupt occurs or |
---|
570 | * when a context switch occurs at the end of an ISR. |
---|
571 | */ |
---|
572 | uint32_t special_interrupt_register; |
---|
573 | } CPU_Interrupt_frame; |
---|
574 | |
---|
575 | /** |
---|
576 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
577 | * to generate an "uninitialized" FP context. It is filled in by |
---|
578 | * @ref _CPU_Initialize and copied into the task's FP context area during |
---|
579 | * @ref _CPU_Context_Initialize. |
---|
580 | * |
---|
581 | * Port Specific Information: |
---|
582 | * |
---|
583 | * XXX document implementation including references if appropriate |
---|
584 | */ |
---|
585 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
586 | |
---|
587 | /** @} */ |
---|
588 | |
---|
589 | /** |
---|
590 | * @defgroup CPUInterrupt Processor Dependent Interrupt Management |
---|
591 | * |
---|
592 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
---|
593 | * This stack is allocated by the Interrupt Manager and the switch |
---|
594 | * is performed in @ref _ISR_Handler. These variables contain pointers |
---|
595 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
596 | * for the interrupt stack. Since it is unknown whether the stack |
---|
597 | * grows up or down (in general), this give the CPU dependent |
---|
598 | * code the option of picking the version it wants to use. |
---|
599 | * |
---|
600 | * NOTE: These two variables are required if the macro |
---|
601 | * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
---|
602 | * |
---|
603 | * Port Specific Information: |
---|
604 | * |
---|
605 | * XXX document implementation including references if appropriate |
---|
606 | */ |
---|
607 | |
---|
608 | /* |
---|
609 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
610 | * |
---|
611 | * Port Specific Information: |
---|
612 | * |
---|
613 | * XXX document implementation including references if appropriate |
---|
614 | */ |
---|
615 | |
---|
616 | /* XXX: if needed, put more variables here */ |
---|
617 | |
---|
618 | /** |
---|
619 | * @ingroup CPUContext |
---|
620 | * |
---|
621 | * The size of the floating point context area. On some CPUs this |
---|
622 | * will not be a "sizeof" because the format of the floating point |
---|
623 | * area is not defined -- only the size is. This is usually on |
---|
624 | * CPUs with a "floating point save context" instruction. |
---|
625 | * |
---|
626 | * Port Specific Information: |
---|
627 | * |
---|
628 | * XXX document implementation including references if appropriate |
---|
629 | */ |
---|
630 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
631 | |
---|
632 | /** |
---|
633 | * Amount of extra stack (above minimum stack size) required by |
---|
634 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
635 | * system this thread must exist and be able to process all directives. |
---|
636 | * |
---|
637 | * Port Specific Information: |
---|
638 | * |
---|
639 | * XXX document implementation including references if appropriate |
---|
640 | */ |
---|
641 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
642 | |
---|
643 | /** |
---|
644 | * @ingroup CPUInterrupt |
---|
645 | * |
---|
646 | * This defines the number of entries in the _ISR_Vector_table managed by RTEMS |
---|
647 | * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be a |
---|
648 | * compile-time constant. |
---|
649 | * |
---|
650 | * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to |
---|
651 | * FALSE. |
---|
652 | */ |
---|
653 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
---|
654 | |
---|
655 | /** |
---|
656 | * @ingroup CPUInterrupt |
---|
657 | * |
---|
658 | * This defines the highest interrupt vector number for this port in case |
---|
659 | * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE. It must be less than |
---|
660 | * CPU_INTERRUPT_NUMBER_OF_VECTORS. It may be not a compile-time constant. |
---|
661 | * |
---|
662 | * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to |
---|
663 | * FALSE. |
---|
664 | */ |
---|
665 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
666 | |
---|
667 | /** |
---|
668 | * @ingroup CPUInterrupt |
---|
669 | * |
---|
670 | * This is defined if the port has a special way to report the ISR nesting |
---|
671 | * level. Most ports maintain the variable @a _ISR_Nest_level. |
---|
672 | */ |
---|
673 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
674 | |
---|
675 | /** |
---|
676 | * @ingroup CPUContext |
---|
677 | * |
---|
678 | * Should be large enough to run all RTEMS tests. This ensures |
---|
679 | * that a "reasonable" small application should not have any problems. |
---|
680 | * |
---|
681 | * Port Specific Information: |
---|
682 | * |
---|
683 | * XXX document implementation including references if appropriate |
---|
684 | */ |
---|
685 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
686 | |
---|
687 | /** |
---|
688 | * Size of a pointer. |
---|
689 | * |
---|
690 | * This must be an integer literal that can be used by the assembler. This |
---|
691 | * value will be used to calculate offsets of structure members. These |
---|
692 | * offsets will be used in assembler code. |
---|
693 | */ |
---|
694 | #define CPU_SIZEOF_POINTER 4 |
---|
695 | |
---|
696 | /** |
---|
697 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
698 | * alignment does not take into account the requirements for the stack. It |
---|
699 | * must be a power of two greater than or equal to two. The power of two |
---|
700 | * requirement makes it possible to align values easily using simple bit |
---|
701 | * operations. |
---|
702 | * |
---|
703 | * Port Specific Information: |
---|
704 | * |
---|
705 | * XXX document implementation including references if appropriate |
---|
706 | */ |
---|
707 | #define CPU_ALIGNMENT 8 |
---|
708 | |
---|
709 | /** |
---|
710 | * This number corresponds to the byte alignment requirement for the |
---|
711 | * heap handler. This alignment requirement may be stricter than that |
---|
712 | * for the data types alignment specified by @ref CPU_ALIGNMENT. It is |
---|
713 | * common for the heap to follow the same alignment requirement as |
---|
714 | * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for |
---|
715 | * the heap, then this should be set to @ref CPU_ALIGNMENT. |
---|
716 | * |
---|
717 | * NOTE: It must be a power of two greater than or equal to two. The |
---|
718 | * requirement to be a multiple of two is because the heap uses the |
---|
719 | * least significant field of the front and back flags to indicate that |
---|
720 | * a block is in use or free. So you do not want any odd length blocks |
---|
721 | * really putting length data in that bit. |
---|
722 | * |
---|
723 | * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will |
---|
724 | * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that |
---|
725 | * elements allocated from the heap meet all restrictions. |
---|
726 | * |
---|
727 | * Port Specific Information: |
---|
728 | * |
---|
729 | * XXX document implementation including references if appropriate |
---|
730 | */ |
---|
731 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
732 | |
---|
733 | /** |
---|
734 | * This number corresponds to the byte alignment requirement for memory |
---|
735 | * buffers allocated by the partition manager. This alignment requirement |
---|
736 | * may be stricter than that for the data types alignment specified by |
---|
737 | * @ref CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
738 | * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is |
---|
739 | * strict enough for the partition, then this should be set to |
---|
740 | * @ref CPU_ALIGNMENT. |
---|
741 | * |
---|
742 | * NOTE: This does not have to be a power of 2. It does have to |
---|
743 | * be greater or equal to than @ref CPU_ALIGNMENT. |
---|
744 | * |
---|
745 | * Port Specific Information: |
---|
746 | * |
---|
747 | * XXX document implementation including references if appropriate |
---|
748 | */ |
---|
749 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
750 | |
---|
751 | /** |
---|
752 | * This number corresponds to the byte alignment requirement for the |
---|
753 | * stack. This alignment requirement may be stricter than that for the |
---|
754 | * data types alignment specified by @ref CPU_ALIGNMENT. If the |
---|
755 | * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be |
---|
756 | * set to 0. |
---|
757 | * |
---|
758 | * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. |
---|
759 | * |
---|
760 | * Port Specific Information: |
---|
761 | * |
---|
762 | * XXX document implementation including references if appropriate |
---|
763 | */ |
---|
764 | #define CPU_STACK_ALIGNMENT 0 |
---|
765 | |
---|
766 | /* |
---|
767 | * ISR handler macros |
---|
768 | */ |
---|
769 | |
---|
770 | /** |
---|
771 | * @ingroup CPUInterrupt |
---|
772 | * |
---|
773 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
774 | * |
---|
775 | * Port Specific Information: |
---|
776 | * |
---|
777 | * XXX document implementation including references if appropriate |
---|
778 | */ |
---|
779 | #define _CPU_Initialize_vectors() |
---|
780 | |
---|
781 | /** |
---|
782 | * @ingroup CPUInterrupt |
---|
783 | * |
---|
784 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
785 | * level is returned in @a _isr_cookie. |
---|
786 | * |
---|
787 | * @param[out] _isr_cookie will contain the previous level cookie |
---|
788 | * |
---|
789 | * Port Specific Information: |
---|
790 | * |
---|
791 | * XXX document implementation including references if appropriate |
---|
792 | */ |
---|
793 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
794 | { \ |
---|
795 | (_isr_cookie) = 0; /* do something to prevent warnings */ \ |
---|
796 | } |
---|
797 | |
---|
798 | /** |
---|
799 | * @ingroup CPUInterrupt |
---|
800 | * |
---|
801 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
802 | * This indicates the end of an RTEMS critical section. The parameter |
---|
803 | * @a _isr_cookie is not modified. |
---|
804 | * |
---|
805 | * @param[in] _isr_cookie contain the previous level cookie |
---|
806 | * |
---|
807 | * Port Specific Information: |
---|
808 | * |
---|
809 | * XXX document implementation including references if appropriate |
---|
810 | */ |
---|
811 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
812 | { \ |
---|
813 | } |
---|
814 | |
---|
815 | /** |
---|
816 | * @ingroup CPUInterrupt |
---|
817 | * |
---|
818 | * This temporarily restores the interrupt to @a _isr_cookie before immediately |
---|
819 | * disabling them again. This is used to divide long RTEMS critical |
---|
820 | * sections into two or more parts. The parameter @a _isr_cookie is not |
---|
821 | * modified. |
---|
822 | * |
---|
823 | * @param[in] _isr_cookie contain the previous level cookie |
---|
824 | * |
---|
825 | * Port Specific Information: |
---|
826 | * |
---|
827 | * XXX document implementation including references if appropriate |
---|
828 | */ |
---|
829 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
830 | { \ |
---|
831 | } |
---|
832 | |
---|
833 | /** |
---|
834 | * @ingroup CPUInterrupt |
---|
835 | * |
---|
836 | * This routine and @ref _CPU_ISR_Get_level |
---|
837 | * Map the interrupt level in task mode onto the hardware that the CPU |
---|
838 | * actually provides. Currently, interrupt levels which do not |
---|
839 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
840 | * it would be nice if these were "mapped" by the application |
---|
841 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
842 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
843 | * This could be used to manage a programmable interrupt controller |
---|
844 | * via the rtems_task_mode directive. |
---|
845 | * |
---|
846 | * Port Specific Information: |
---|
847 | * |
---|
848 | * XXX document implementation including references if appropriate |
---|
849 | */ |
---|
850 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
851 | { \ |
---|
852 | } |
---|
853 | |
---|
854 | /** |
---|
855 | * @ingroup CPUInterrupt |
---|
856 | * |
---|
857 | * Return the current interrupt disable level for this task in |
---|
858 | * the format used by the interrupt level portion of the task mode. |
---|
859 | * |
---|
860 | * NOTE: This routine usually must be implemented as a subroutine. |
---|
861 | * |
---|
862 | * Port Specific Information: |
---|
863 | * |
---|
864 | * XXX document implementation including references if appropriate |
---|
865 | */ |
---|
866 | uint32_t _CPU_ISR_Get_level( void ); |
---|
867 | |
---|
868 | /* end of ISR handler macros */ |
---|
869 | |
---|
870 | /* Context handler macros */ |
---|
871 | |
---|
872 | /** |
---|
873 | * @ingroup CPUContext |
---|
874 | * |
---|
875 | * Initialize the context to a state suitable for starting a |
---|
876 | * task after a context restore operation. Generally, this |
---|
877 | * involves: |
---|
878 | * |
---|
879 | * - setting a starting address |
---|
880 | * - preparing the stack |
---|
881 | * - preparing the stack and frame pointers |
---|
882 | * - setting the proper interrupt level in the context |
---|
883 | * - initializing the floating point context |
---|
884 | * |
---|
885 | * This routine generally does not set any unnecessary register |
---|
886 | * in the context. The state of the "general data" registers is |
---|
887 | * undefined at task start time. |
---|
888 | * |
---|
889 | * @param[in] _the_context is the context structure to be initialized |
---|
890 | * @param[in] _stack_base is the lowest physical address of this task's stack |
---|
891 | * @param[in] _size is the size of this task's stack |
---|
892 | * @param[in] _isr is the interrupt disable level |
---|
893 | * @param[in] _entry_point is the thread's entry point. This is |
---|
894 | * always @a _Thread_Handler |
---|
895 | * @param[in] _is_fp is TRUE if the thread is to be a floating |
---|
896 | * point thread. This is typically only used on CPUs where the |
---|
897 | * FPU may be easily disabled by software such as on the SPARC |
---|
898 | * where the PSR contains an enable FPU bit. |
---|
899 | * @param[in] _tls_area The thread-local storage (TLS) area. |
---|
900 | * |
---|
901 | * Port Specific Information: |
---|
902 | * |
---|
903 | * XXX document implementation including references if appropriate |
---|
904 | */ |
---|
905 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
906 | _isr, _entry_point, _is_fp, _tls_area ) \ |
---|
907 | { \ |
---|
908 | } |
---|
909 | |
---|
910 | /** |
---|
911 | * This routine is responsible for somehow restarting the currently |
---|
912 | * executing task. If you are lucky, then all that is necessary |
---|
913 | * is restoring the context. Otherwise, there will need to be |
---|
914 | * a special assembly routine which does something special in this |
---|
915 | * case. For many ports, simply adding a label to the restore path |
---|
916 | * of @ref _CPU_Context_switch will work. On other ports, it may be |
---|
917 | * possibly to load a few arguments and jump to the restore path. It will |
---|
918 | * not work if restarting self conflicts with the stack frame |
---|
919 | * assumptions of restoring a context. |
---|
920 | * |
---|
921 | * Port Specific Information: |
---|
922 | * |
---|
923 | * XXX document implementation including references if appropriate |
---|
924 | */ |
---|
925 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
926 | _CPU_Context_restore( (_the_context) ); |
---|
927 | |
---|
928 | /** |
---|
929 | * @ingroup CPUContext |
---|
930 | * |
---|
931 | * The purpose of this macro is to allow the initial pointer into |
---|
932 | * a floating point context area (used to save the floating point |
---|
933 | * context) to be at an arbitrary place in the floating point |
---|
934 | *context area. |
---|
935 | * |
---|
936 | * This is necessary because some FP units are designed to have |
---|
937 | * their context saved as a stack which grows into lower addresses. |
---|
938 | * Other FP units can be saved by simply moving registers into offsets |
---|
939 | * from the base of the context area. Finally some FP units provide |
---|
940 | * a "dump context" instruction which could fill in from high to low |
---|
941 | * or low to high based on the whim of the CPU designers. |
---|
942 | * |
---|
943 | * @param[in] _base is the lowest physical address of the floating point |
---|
944 | * context area |
---|
945 | * @param[in] _offset is the offset into the floating point area |
---|
946 | * |
---|
947 | * Port Specific Information: |
---|
948 | * |
---|
949 | * XXX document implementation including references if appropriate |
---|
950 | */ |
---|
951 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
952 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
953 | |
---|
954 | /** |
---|
955 | * This routine initializes the FP context area passed to it to. |
---|
956 | * There are a few standard ways in which to initialize the |
---|
957 | * floating point context. The code included for this macro assumes |
---|
958 | * that this is a CPU in which a "initial" FP context was saved into |
---|
959 | * @a _CPU_Null_fp_context and it simply copies it to the destination |
---|
960 | * context passed to it. |
---|
961 | * |
---|
962 | * Other floating point context save/restore models include: |
---|
963 | * -# not doing anything, and |
---|
964 | * -# putting a "null FP status word" in the correct place in the FP context. |
---|
965 | * |
---|
966 | * @param[in] _destination is the floating point context area |
---|
967 | * |
---|
968 | * Port Specific Information: |
---|
969 | * |
---|
970 | * XXX document implementation including references if appropriate |
---|
971 | */ |
---|
972 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
973 | { \ |
---|
974 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
975 | } |
---|
976 | |
---|
977 | /* end of Context handler macros */ |
---|
978 | |
---|
979 | /* Fatal Error manager macros */ |
---|
980 | |
---|
981 | /** |
---|
982 | * This routine copies _error into a known place -- typically a stack |
---|
983 | * location or a register, optionally disables interrupts, and |
---|
984 | * halts/stops the CPU. |
---|
985 | * |
---|
986 | * Port Specific Information: |
---|
987 | * |
---|
988 | * XXX document implementation including references if appropriate |
---|
989 | */ |
---|
990 | #define _CPU_Fatal_halt( _source, _error ) \ |
---|
991 | { \ |
---|
992 | } |
---|
993 | |
---|
994 | /* end of Fatal Error manager macros */ |
---|
995 | |
---|
996 | /* Bitfield handler macros */ |
---|
997 | |
---|
998 | /** |
---|
999 | * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation |
---|
1000 | * |
---|
1001 | * This set of routines are used to implement fast searches for |
---|
1002 | * the most important ready task. |
---|
1003 | * |
---|
1004 | */ |
---|
1005 | /**@{**/ |
---|
1006 | |
---|
1007 | /** |
---|
1008 | * This definition is set to TRUE if the port uses the generic bitfield |
---|
1009 | * manipulation implementation. |
---|
1010 | */ |
---|
1011 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
1012 | |
---|
1013 | /** |
---|
1014 | * This definition is set to TRUE if the port uses the data tables provided |
---|
1015 | * by the generic bitfield manipulation implementation. |
---|
1016 | * This can occur when actually using the generic bitfield manipulation |
---|
1017 | * implementation or when implementing the same algorithm in assembly |
---|
1018 | * language for improved performance. It is unlikely that a port will use |
---|
1019 | * the data if it has a bitfield scan instruction. |
---|
1020 | */ |
---|
1021 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
1022 | |
---|
1023 | /** |
---|
1024 | * This routine sets @a _output to the bit number of the first bit |
---|
1025 | * set in @a _value. @a _value is of CPU dependent type |
---|
1026 | * @a Priority_bit_map_Word. This type may be either 16 or 32 bits |
---|
1027 | * wide although only the 16 least significant bits will be used. |
---|
1028 | * |
---|
1029 | * There are a number of variables in using a "find first bit" type |
---|
1030 | * instruction. |
---|
1031 | * |
---|
1032 | * -# What happens when run on a value of zero? |
---|
1033 | * -# Bits may be numbered from MSB to LSB or vice-versa. |
---|
1034 | * -# The numbering may be zero or one based. |
---|
1035 | * -# The "find first bit" instruction may search from MSB or LSB. |
---|
1036 | * |
---|
1037 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
1038 | * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and |
---|
1039 | * @ref _CPU_Priority_bits_index. These three form a set of routines |
---|
1040 | * which must logically operate together. Bits in the _value are |
---|
1041 | * set and cleared based on masks built by @ref _CPU_Priority_Mask. |
---|
1042 | * The basic major and minor values calculated by @ref _Priority_Major |
---|
1043 | * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index |
---|
1044 | * to properly range between the values returned by the "find first bit" |
---|
1045 | * instruction. This makes it possible for @ref _Priority_Get_highest to |
---|
1046 | * calculate the major and directly index into the minor table. |
---|
1047 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
1048 | * is the first bit found. |
---|
1049 | * |
---|
1050 | * This entire "find first bit" and mapping process depends heavily |
---|
1051 | * on the manner in which a priority is broken into a major and minor |
---|
1052 | * components with the major being the 4 MSB of a priority and minor |
---|
1053 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
1054 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
1055 | * to the lowest priority. |
---|
1056 | * |
---|
1057 | * If your CPU does not have a "find first bit" instruction, then |
---|
1058 | * there are ways to make do without it. Here are a handful of ways |
---|
1059 | * to implement this in software: |
---|
1060 | * |
---|
1061 | @verbatim |
---|
1062 | - a series of 16 bit test instructions |
---|
1063 | - a "binary search using if's" |
---|
1064 | - _number = 0 |
---|
1065 | if _value > 0x00ff |
---|
1066 | _value >>=8 |
---|
1067 | _number = 8; |
---|
1068 | |
---|
1069 | if _value > 0x0000f |
---|
1070 | _value >=8 |
---|
1071 | _number += 4 |
---|
1072 | |
---|
1073 | _number += bit_set_table[ _value ] |
---|
1074 | @endverbatim |
---|
1075 | |
---|
1076 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
1077 | * bit set |
---|
1078 | * |
---|
1079 | * @param[in] _value is the value to be scanned |
---|
1080 | * @param[in] _output is the first bit set |
---|
1081 | * |
---|
1082 | * Port Specific Information: |
---|
1083 | * |
---|
1084 | * XXX document implementation including references if appropriate |
---|
1085 | */ |
---|
1086 | |
---|
1087 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
1088 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
1089 | { \ |
---|
1090 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
1091 | } |
---|
1092 | #endif |
---|
1093 | |
---|
1094 | /** @} */ |
---|
1095 | |
---|
1096 | /* end of Bitfield handler macros */ |
---|
1097 | |
---|
1098 | /** |
---|
1099 | * This routine builds the mask which corresponds to the bit fields |
---|
1100 | * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion |
---|
1101 | * for that routine. |
---|
1102 | * |
---|
1103 | * Port Specific Information: |
---|
1104 | * |
---|
1105 | * XXX document implementation including references if appropriate |
---|
1106 | */ |
---|
1107 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
1108 | |
---|
1109 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
1110 | ( 1 << (_bit_number) ) |
---|
1111 | |
---|
1112 | #endif |
---|
1113 | |
---|
1114 | /** |
---|
1115 | * @ingroup CPUBitfield |
---|
1116 | * |
---|
1117 | * This routine translates the bit numbers returned by |
---|
1118 | * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as |
---|
1119 | * a major or minor component of a priority. See the discussion |
---|
1120 | * for that routine. |
---|
1121 | * |
---|
1122 | * @param[in] _priority is the major or minor number to translate |
---|
1123 | * |
---|
1124 | * Port Specific Information: |
---|
1125 | * |
---|
1126 | * XXX document implementation including references if appropriate |
---|
1127 | */ |
---|
1128 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
1129 | |
---|
1130 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
1131 | (_priority) |
---|
1132 | |
---|
1133 | #endif |
---|
1134 | |
---|
1135 | /* end of Priority handler macros */ |
---|
1136 | |
---|
1137 | /* functions */ |
---|
1138 | |
---|
1139 | /** |
---|
1140 | * This routine performs CPU dependent initialization. |
---|
1141 | * |
---|
1142 | * Port Specific Information: |
---|
1143 | * |
---|
1144 | * XXX document implementation including references if appropriate |
---|
1145 | */ |
---|
1146 | void _CPU_Initialize(void); |
---|
1147 | |
---|
1148 | /** |
---|
1149 | * @ingroup CPUInterrupt |
---|
1150 | * |
---|
1151 | * This routine installs a "raw" interrupt handler directly into the |
---|
1152 | * processor's vector table. |
---|
1153 | * |
---|
1154 | * @param[in] vector is the vector number |
---|
1155 | * @param[in] new_handler is the raw ISR handler to install |
---|
1156 | * @param[in] old_handler is the previously installed ISR Handler |
---|
1157 | * |
---|
1158 | * Port Specific Information: |
---|
1159 | * |
---|
1160 | * XXX document implementation including references if appropriate |
---|
1161 | */ |
---|
1162 | void _CPU_ISR_install_raw_handler( |
---|
1163 | uint32_t vector, |
---|
1164 | proc_ptr new_handler, |
---|
1165 | proc_ptr *old_handler |
---|
1166 | ); |
---|
1167 | |
---|
1168 | /** |
---|
1169 | * @ingroup CPUInterrupt |
---|
1170 | * |
---|
1171 | * This routine installs an interrupt vector. |
---|
1172 | * |
---|
1173 | * @param[in] vector is the vector number |
---|
1174 | * @param[in] new_handler is the RTEMS ISR handler to install |
---|
1175 | * @param[in] old_handler is the previously installed ISR Handler |
---|
1176 | * |
---|
1177 | * Port Specific Information: |
---|
1178 | * |
---|
1179 | * XXX document implementation including references if appropriate |
---|
1180 | */ |
---|
1181 | void _CPU_ISR_install_vector( |
---|
1182 | uint32_t vector, |
---|
1183 | proc_ptr new_handler, |
---|
1184 | proc_ptr *old_handler |
---|
1185 | ); |
---|
1186 | |
---|
1187 | /** |
---|
1188 | * @ingroup CPUInterrupt |
---|
1189 | * This routine installs the hardware interrupt stack pointer. |
---|
1190 | * |
---|
1191 | * NOTE: It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
1192 | * is TRUE. |
---|
1193 | * |
---|
1194 | * Port Specific Information: |
---|
1195 | * |
---|
1196 | * XXX document implementation including references if appropriate |
---|
1197 | */ |
---|
1198 | void _CPU_Install_interrupt_stack( void ); |
---|
1199 | |
---|
1200 | /** |
---|
1201 | * This routine is the CPU dependent IDLE thread body. |
---|
1202 | * |
---|
1203 | * NOTE: It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY |
---|
1204 | * is TRUE. |
---|
1205 | * |
---|
1206 | * Port Specific Information: |
---|
1207 | * |
---|
1208 | * XXX document implementation including references if appropriate |
---|
1209 | */ |
---|
1210 | void *_CPU_Thread_Idle_body( uintptr_t ignored ); |
---|
1211 | |
---|
1212 | /** |
---|
1213 | * @ingroup CPUContext |
---|
1214 | * |
---|
1215 | * This routine switches from the run context to the heir context. |
---|
1216 | * |
---|
1217 | * @param[in] run points to the context of the currently executing task |
---|
1218 | * @param[in] heir points to the context of the heir task |
---|
1219 | * |
---|
1220 | * Port Specific Information: |
---|
1221 | * |
---|
1222 | * XXX document implementation including references if appropriate |
---|
1223 | */ |
---|
1224 | void _CPU_Context_switch( |
---|
1225 | Context_Control *run, |
---|
1226 | Context_Control *heir |
---|
1227 | ); |
---|
1228 | |
---|
1229 | /** |
---|
1230 | * @ingroup CPUContext |
---|
1231 | * |
---|
1232 | * This routine is generally used only to restart self in an |
---|
1233 | * efficient manner. It may simply be a label in @ref _CPU_Context_switch. |
---|
1234 | * |
---|
1235 | * @param[in] new_context points to the context to be restored. |
---|
1236 | * |
---|
1237 | * NOTE: May be unnecessary to reload some registers. |
---|
1238 | * |
---|
1239 | * Port Specific Information: |
---|
1240 | * |
---|
1241 | * XXX document implementation including references if appropriate |
---|
1242 | */ |
---|
1243 | void _CPU_Context_restore( |
---|
1244 | Context_Control *new_context |
---|
1245 | ) RTEMS_NO_RETURN; |
---|
1246 | |
---|
1247 | /** |
---|
1248 | * @ingroup CPUContext |
---|
1249 | * |
---|
1250 | * This routine saves the floating point context passed to it. |
---|
1251 | * |
---|
1252 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
1253 | * point context area |
---|
1254 | * |
---|
1255 | * @return on output @a *fp_context_ptr will contain the address that |
---|
1256 | * should be used with @ref _CPU_Context_restore_fp to restore this context. |
---|
1257 | * |
---|
1258 | * Port Specific Information: |
---|
1259 | * |
---|
1260 | * XXX document implementation including references if appropriate |
---|
1261 | */ |
---|
1262 | void _CPU_Context_save_fp( |
---|
1263 | Context_Control_fp **fp_context_ptr |
---|
1264 | ); |
---|
1265 | |
---|
1266 | /** |
---|
1267 | * @ingroup CPUContext |
---|
1268 | * |
---|
1269 | * This routine restores the floating point context passed to it. |
---|
1270 | * |
---|
1271 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
1272 | * point context area to restore |
---|
1273 | * |
---|
1274 | * @return on output @a *fp_context_ptr will contain the address that |
---|
1275 | * should be used with @ref _CPU_Context_save_fp to save this context. |
---|
1276 | * |
---|
1277 | * Port Specific Information: |
---|
1278 | * |
---|
1279 | * XXX document implementation including references if appropriate |
---|
1280 | */ |
---|
1281 | void _CPU_Context_restore_fp( |
---|
1282 | Context_Control_fp **fp_context_ptr |
---|
1283 | ); |
---|
1284 | |
---|
1285 | /** |
---|
1286 | * @ingroup CPUContext |
---|
1287 | * |
---|
1288 | * @brief Clobbers all volatile registers with values derived from the pattern |
---|
1289 | * parameter. |
---|
1290 | * |
---|
1291 | * This function is used only in test sptests/spcontext01. |
---|
1292 | * |
---|
1293 | * @param[in] pattern Pattern used to generate distinct register values. |
---|
1294 | * |
---|
1295 | * @see _CPU_Context_validate(). |
---|
1296 | */ |
---|
1297 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
---|
1298 | |
---|
1299 | /** |
---|
1300 | * @ingroup CPUContext |
---|
1301 | * |
---|
1302 | * @brief Initializes and validates the CPU context with values derived from |
---|
1303 | * the pattern parameter. |
---|
1304 | * |
---|
1305 | * This function will not return if the CPU context remains consistent. In |
---|
1306 | * case this function returns the CPU port is broken. |
---|
1307 | * |
---|
1308 | * This function is used only in test sptests/spcontext01. |
---|
1309 | * |
---|
1310 | * @param[in] pattern Pattern used to generate distinct register values. |
---|
1311 | * |
---|
1312 | * @see _CPU_Context_volatile_clobber(). |
---|
1313 | */ |
---|
1314 | void _CPU_Context_validate( uintptr_t pattern ); |
---|
1315 | |
---|
1316 | /** |
---|
1317 | * @brief The set of registers that specifies the complete processor state. |
---|
1318 | * |
---|
1319 | * The CPU exception frame may be available in fatal error conditions like for |
---|
1320 | * example illegal opcodes, instruction fetch errors, or data access errors. |
---|
1321 | * |
---|
1322 | * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and |
---|
1323 | * rtems_exception_frame_print(). |
---|
1324 | */ |
---|
1325 | typedef struct { |
---|
1326 | uint32_t processor_state_register; |
---|
1327 | uint32_t integer_registers [1]; |
---|
1328 | double float_registers [1]; |
---|
1329 | } CPU_Exception_frame; |
---|
1330 | |
---|
1331 | /** |
---|
1332 | * @brief Prints the exception frame via printk(). |
---|
1333 | * |
---|
1334 | * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION. |
---|
1335 | */ |
---|
1336 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
---|
1337 | |
---|
1338 | /** |
---|
1339 | * @ingroup CPUEndian |
---|
1340 | * |
---|
1341 | * The following routine swaps the endian format of an unsigned int. |
---|
1342 | * It must be static because it is referenced indirectly. |
---|
1343 | * |
---|
1344 | * This version will work on any processor, but if there is a better |
---|
1345 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
1346 | * |
---|
1347 | * swap least significant two bytes with 16-bit rotate |
---|
1348 | * swap upper and lower 16-bits |
---|
1349 | * swap most significant two bytes with 16-bit rotate |
---|
1350 | * |
---|
1351 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
1352 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
1353 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
1354 | * that interrupts would probably have to be disabled to ensure that |
---|
1355 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
1356 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
1357 | * endianness for ALL fetches -- both code and data -- so the code |
---|
1358 | * will be fetched incorrectly. |
---|
1359 | * |
---|
1360 | * @param[in] value is the value to be swapped |
---|
1361 | * @return the value after being endian swapped |
---|
1362 | * |
---|
1363 | * Port Specific Information: |
---|
1364 | * |
---|
1365 | * XXX document implementation including references if appropriate |
---|
1366 | */ |
---|
1367 | static inline uint32_t CPU_swap_u32( |
---|
1368 | uint32_t value |
---|
1369 | ) |
---|
1370 | { |
---|
1371 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
1372 | |
---|
1373 | byte4 = (value >> 24) & 0xff; |
---|
1374 | byte3 = (value >> 16) & 0xff; |
---|
1375 | byte2 = (value >> 8) & 0xff; |
---|
1376 | byte1 = value & 0xff; |
---|
1377 | |
---|
1378 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
1379 | return swapped; |
---|
1380 | } |
---|
1381 | |
---|
1382 | /** |
---|
1383 | * @ingroup CPUEndian |
---|
1384 | * |
---|
1385 | * This routine swaps a 16 bir quantity. |
---|
1386 | * |
---|
1387 | * @param[in] value is the value to be swapped |
---|
1388 | * @return the value after being endian swapped |
---|
1389 | */ |
---|
1390 | #define CPU_swap_u16( value ) \ |
---|
1391 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
1392 | |
---|
1393 | /** |
---|
1394 | * @brief Unsigned integer type for CPU counter values. |
---|
1395 | */ |
---|
1396 | typedef uint32_t CPU_Counter_ticks; |
---|
1397 | |
---|
1398 | /** |
---|
1399 | * @brief Returns the current CPU counter value. |
---|
1400 | * |
---|
1401 | * A CPU counter is some free-running counter. It ticks usually with a |
---|
1402 | * frequency close to the CPU or system bus clock. The board support package |
---|
1403 | * must ensure that this function works before the RTEMS initialization. |
---|
1404 | * Otherwise invalid profiling statistics will be gathered. |
---|
1405 | * |
---|
1406 | * @return The current CPU counter value. |
---|
1407 | */ |
---|
1408 | CPU_Counter_ticks _CPU_Counter_read( void ); |
---|
1409 | |
---|
1410 | /** |
---|
1411 | * @brief Returns the difference between the second and first CPU counter |
---|
1412 | * value. |
---|
1413 | * |
---|
1414 | * This operation may be carried out as a modulo operation depending on the |
---|
1415 | * range of the CPU counter device. |
---|
1416 | * |
---|
1417 | * @param[in] second The second CPU counter value. |
---|
1418 | * @param[in] first The first CPU counter value. |
---|
1419 | * |
---|
1420 | * @return Returns second minus first modulo counter period. |
---|
1421 | */ |
---|
1422 | CPU_Counter_ticks _CPU_Counter_difference( |
---|
1423 | CPU_Counter_ticks second, |
---|
1424 | CPU_Counter_ticks first |
---|
1425 | ); |
---|
1426 | |
---|
1427 | /** |
---|
1428 | * @brief Special register pointing to the per-CPU control of the current |
---|
1429 | * processor. |
---|
1430 | * |
---|
1431 | * This is optional. Not every CPU port needs this. It is only an optional |
---|
1432 | * optimization variant. |
---|
1433 | */ |
---|
1434 | register struct Per_CPU_Control *_CPU_Per_CPU_current asm( "rX" ); |
---|
1435 | |
---|
1436 | /** |
---|
1437 | * @brief Optional method to obtain the per-CPU control of the current processor. |
---|
1438 | * |
---|
1439 | * This is optional. Not every CPU port needs this. It is only an optional |
---|
1440 | * optimization variant. In case this macro is undefined, the default |
---|
1441 | * implementation using the current processor index will be used. |
---|
1442 | */ |
---|
1443 | #define _CPU_Get_current_per_CPU_control() ( _CPU_Per_CPU_current ) |
---|
1444 | |
---|
1445 | #ifdef RTEMS_SMP |
---|
1446 | /** |
---|
1447 | * @brief Performs CPU specific SMP initialization in the context of the boot |
---|
1448 | * processor. |
---|
1449 | * |
---|
1450 | * This function is invoked on the boot processor during system |
---|
1451 | * initialization. All interrupt stacks are allocated at this point in case |
---|
1452 | * the CPU port allocates the interrupt stacks. This function is called |
---|
1453 | * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is |
---|
1454 | * used. |
---|
1455 | * |
---|
1456 | * @return The count of physically or virtually available processors. |
---|
1457 | * Depending on the configuration the application may use not all processors. |
---|
1458 | */ |
---|
1459 | uint32_t _CPU_SMP_Initialize( void ); |
---|
1460 | |
---|
1461 | /** |
---|
1462 | * @brief Starts a processor specified by its index. |
---|
1463 | * |
---|
1464 | * This function is invoked on the boot processor during system |
---|
1465 | * initialization. |
---|
1466 | * |
---|
1467 | * This function will be called after _CPU_SMP_Initialize(). |
---|
1468 | * |
---|
1469 | * @param[in] cpu_index The processor index. |
---|
1470 | * |
---|
1471 | * @retval true Successful operation. |
---|
1472 | * @retval false Unable to start this processor. |
---|
1473 | */ |
---|
1474 | bool _CPU_SMP_Start_processor( uint32_t cpu_index ); |
---|
1475 | |
---|
1476 | /** |
---|
1477 | * @brief Performs final steps of CPU specific SMP initialization in the |
---|
1478 | * context of the boot processor. |
---|
1479 | * |
---|
1480 | * This function is invoked on the boot processor during system |
---|
1481 | * initialization. |
---|
1482 | * |
---|
1483 | * This function will be called after all processors requested by the |
---|
1484 | * application have been started. |
---|
1485 | * |
---|
1486 | * @param[in] cpu_count The minimum value of the count of processors |
---|
1487 | * requested by the application configuration and the count of physically or |
---|
1488 | * virtually available processors. |
---|
1489 | */ |
---|
1490 | void _CPU_SMP_Finalize_initialization( uint32_t cpu_count ); |
---|
1491 | |
---|
1492 | /** |
---|
1493 | * @brief Prepares a CPU to start multitasking in terms of SMP. |
---|
1494 | * |
---|
1495 | * This function is invoked on all processors requested by the application |
---|
1496 | * during system initialization. |
---|
1497 | * |
---|
1498 | * This function will be called after all processors requested by the |
---|
1499 | * application have been started right before the context switch to the first |
---|
1500 | * thread takes place. |
---|
1501 | */ |
---|
1502 | void _CPU_SMP_Prepare_start_multitasking( void ); |
---|
1503 | |
---|
1504 | /** |
---|
1505 | * @brief Returns the index of the current processor. |
---|
1506 | * |
---|
1507 | * An architecture specific method must be used to obtain the index of the |
---|
1508 | * current processor in the system. The set of processor indices is the |
---|
1509 | * range of integers starting with zero up to the processor count minus one. |
---|
1510 | */ |
---|
1511 | static inline uint32_t _CPU_SMP_Get_current_processor( void ) |
---|
1512 | { |
---|
1513 | return 123; |
---|
1514 | } |
---|
1515 | |
---|
1516 | /** |
---|
1517 | * @brief Sends an inter-processor interrupt to the specified target |
---|
1518 | * processor. |
---|
1519 | * |
---|
1520 | * This interrupt send and the corresponding inter-processor interrupt must |
---|
1521 | * act as an release/acquire barrier so that all values written by the |
---|
1522 | * sending processor are visible to the target processor. |
---|
1523 | * |
---|
1524 | * This operation is undefined for target processor indices out of range. |
---|
1525 | * |
---|
1526 | * @param[in] target_processor_index The target processor index. |
---|
1527 | */ |
---|
1528 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ); |
---|
1529 | |
---|
1530 | /** |
---|
1531 | * @brief Broadcasts a processor event. |
---|
1532 | * |
---|
1533 | * Some architectures provide a low-level synchronization primitive for |
---|
1534 | * processors in a multi-processor environment. Processors waiting for this |
---|
1535 | * event may go into a low-power state and stop generating system bus |
---|
1536 | * transactions. This function must ensure that preceding store operations |
---|
1537 | * can be observed by other processors. |
---|
1538 | * |
---|
1539 | * @see _CPU_SMP_Processor_event_receive(). |
---|
1540 | */ |
---|
1541 | static inline void _CPU_SMP_Processor_event_broadcast( void ) |
---|
1542 | { |
---|
1543 | __asm__ volatile ( "" : : : "memory" ); |
---|
1544 | } |
---|
1545 | |
---|
1546 | /** |
---|
1547 | * @brief Receives a processor event. |
---|
1548 | * |
---|
1549 | * This function will wait for the processor event and may wait forever if no |
---|
1550 | * such event arrives. |
---|
1551 | * |
---|
1552 | * @see _CPU_SMP_Processor_event_broadcast(). |
---|
1553 | */ |
---|
1554 | static inline void _CPU_SMP_Processor_event_receive( void ) |
---|
1555 | { |
---|
1556 | __asm__ volatile ( "" : : : "memory" ); |
---|
1557 | } |
---|
1558 | |
---|
1559 | /** |
---|
1560 | * @brief Gets the is executing indicator of the thread context. |
---|
1561 | * |
---|
1562 | * @param[in] context The context. |
---|
1563 | */ |
---|
1564 | static inline bool _CPU_Context_Get_is_executing( |
---|
1565 | const Context_Control *context |
---|
1566 | ) |
---|
1567 | { |
---|
1568 | return context->is_executing; |
---|
1569 | } |
---|
1570 | |
---|
1571 | /** |
---|
1572 | * @brief Sets the is executing indicator of the thread context. |
---|
1573 | * |
---|
1574 | * @param[in] context The context. |
---|
1575 | * @param[in] is_executing The new value for the is executing indicator. |
---|
1576 | */ |
---|
1577 | static inline void _CPU_Context_Set_is_executing( |
---|
1578 | Context_Control *context, |
---|
1579 | bool is_executing |
---|
1580 | ) |
---|
1581 | { |
---|
1582 | context->is_executing = is_executing; |
---|
1583 | } |
---|
1584 | #endif |
---|
1585 | |
---|
1586 | #ifdef __cplusplus |
---|
1587 | } |
---|
1588 | #endif |
---|
1589 | |
---|
1590 | #endif |
---|