[77d3533f] | 1 | /** |
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| 2 | * @file rtems/score/cpu.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[7908ba5b] | 6 | * This include file contains information pertaining to the XXX |
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| 7 | * processor. |
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| 8 | * |
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[baff4da] | 9 | * @note This file is part of a porting template that is intended |
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| 10 | * to be used as the starting point when porting RTEMS to a new |
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| 11 | * CPU family. The following needs to be done when using this as |
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| 12 | * the starting point for a new port: |
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| 13 | * |
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| 14 | * + Anywhere there is an XXX, it should be replaced |
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| 15 | * with information about the CPU family being ported to. |
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| 16 | * |
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| 17 | * + At the end of each comment section, there is a heading which |
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| 18 | * says "Port Specific Information:". When porting to RTEMS, |
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| 19 | * add CPU family specific information in this section |
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| 20 | */ |
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| 21 | |
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[95e7637] | 22 | /* |
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| 23 | * COPYRIGHT (c) 1989-2008. |
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[7908ba5b] | 24 | * On-Line Applications Research Corporation (OAR). |
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| 25 | * |
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| 26 | * The license and distribution terms for this file may be |
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| 27 | * found in the file LICENSE in this distribution or at |
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[f226687] | 28 | * http://www.rtems.com/license/LICENSE. |
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[7908ba5b] | 29 | * |
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| 30 | * $Id$ |
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| 31 | */ |
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| 32 | |
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[7f70d1b7] | 33 | #ifndef _RTEMS_SCORE_CPU_H |
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| 34 | #define _RTEMS_SCORE_CPU_H |
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[7908ba5b] | 35 | |
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| 36 | #ifdef __cplusplus |
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| 37 | extern "C" { |
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| 38 | #endif |
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| 39 | |
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| 40 | #include <rtems/score/no_cpu.h> /* pick up machine definitions */ |
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| 41 | #ifndef ASM |
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[14c8ef9] | 42 | #include <rtems/score/types.h> |
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[7908ba5b] | 43 | #endif |
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| 44 | |
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| 45 | /* conditional compilation parameters */ |
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| 46 | |
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[baff4da] | 47 | /** |
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| 48 | * Should the calls to @ref _Thread_Enable_dispatch be inlined? |
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[7908ba5b] | 49 | * |
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| 50 | * If TRUE, then they are inlined. |
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| 51 | * If FALSE, then a subroutine call is made. |
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| 52 | * |
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[baff4da] | 53 | * This conditional is an example of the classic trade-off of size |
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[7908ba5b] | 54 | * versus speed. Inlining the call (TRUE) typically increases the |
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| 55 | * size of RTEMS while speeding up the enabling of dispatching. |
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[baff4da] | 56 | * |
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| 57 | * @note In general, the @ref _Thread_Dispatch_disable_level will |
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[7908ba5b] | 58 | * only be 0 or 1 unless you are in an interrupt handler and that |
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| 59 | * interrupt handler invokes the executive.] When not inlined |
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[baff4da] | 60 | * something calls @ref _Thread_Enable_dispatch which in turns calls |
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| 61 | * @ref _Thread_Dispatch. If the enable dispatch is inlined, then |
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| 62 | * one subroutine call is avoided entirely. |
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[df49c60] | 63 | * |
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[baff4da] | 64 | * Port Specific Information: |
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[df49c60] | 65 | * |
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| 66 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 67 | */ |
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| 68 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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| 69 | |
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[baff4da] | 70 | /** |
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[7908ba5b] | 71 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
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| 72 | * be unrolled one time? In unrolled each iteration of the loop examines |
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| 73 | * two "nodes" on the chain being searched. Otherwise, only one node |
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| 74 | * is examined per iteration. |
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| 75 | * |
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| 76 | * If TRUE, then the loops are unrolled. |
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| 77 | * If FALSE, then the loops are not unrolled. |
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| 78 | * |
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| 79 | * The primary factor in making this decision is the cost of disabling |
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| 80 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
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| 81 | * body of the loop. On some CPUs, the flash is more expensive than |
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| 82 | * one iteration of the loop body. In this case, it might be desirable |
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| 83 | * to unroll the loop. It is important to note that on some CPUs, this |
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| 84 | * code is the longest interrupt disable period in RTEMS. So it is |
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| 85 | * necessary to strike a balance when setting this parameter. |
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[df49c60] | 86 | * |
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[baff4da] | 87 | * Port Specific Information: |
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[df49c60] | 88 | * |
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| 89 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 90 | */ |
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| 91 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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| 92 | |
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[baff4da] | 93 | /** |
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[7908ba5b] | 94 | * Does RTEMS manage a dedicated interrupt stack in software? |
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| 95 | * |
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[baff4da] | 96 | * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. |
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[7908ba5b] | 97 | * If FALSE, nothing is done. |
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| 98 | * |
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| 99 | * If the CPU supports a dedicated interrupt stack in hardware, |
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| 100 | * then it is generally the responsibility of the BSP to allocate it |
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| 101 | * and set it up. |
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| 102 | * |
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| 103 | * If the CPU does not support a dedicated interrupt stack, then |
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| 104 | * the porter has two options: (1) execute interrupts on the |
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| 105 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
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| 106 | * interrupt stack. |
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| 107 | * |
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[baff4da] | 108 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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[7908ba5b] | 109 | * |
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[baff4da] | 110 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 111 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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[7908ba5b] | 112 | * possible that both are FALSE for a particular CPU. Although it |
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| 113 | * is unclear what that would imply about the interrupt processing |
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| 114 | * procedure on that CPU. |
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[df49c60] | 115 | * |
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[baff4da] | 116 | * Port Specific Information: |
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[df49c60] | 117 | * |
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| 118 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 119 | */ |
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| 120 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
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| 121 | |
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[2fd427c] | 122 | /** |
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| 123 | * Does the CPU follow the simple vectored interrupt model? |
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| 124 | * |
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| 125 | * If TRUE, then RTEMS allocates the vector table it internally manages. |
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| 126 | * If FALSE, then the BSP is assumed to allocate and manage the vector |
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| 127 | * table |
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| 128 | * |
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| 129 | * Port Specific Information: |
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| 130 | * |
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| 131 | * XXX document implementation including references if appropriate |
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| 132 | */ |
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| 133 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 134 | |
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[baff4da] | 135 | /** |
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[7908ba5b] | 136 | * Does this CPU have hardware support for a dedicated interrupt stack? |
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| 137 | * |
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| 138 | * If TRUE, then it must be installed during initialization. |
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| 139 | * If FALSE, then no installation is performed. |
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| 140 | * |
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[baff4da] | 141 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
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[7908ba5b] | 142 | * |
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[baff4da] | 143 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
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| 144 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
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[7908ba5b] | 145 | * possible that both are FALSE for a particular CPU. Although it |
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| 146 | * is unclear what that would imply about the interrupt processing |
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| 147 | * procedure on that CPU. |
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[df49c60] | 148 | * |
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[baff4da] | 149 | * Port Specific Information: |
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[df49c60] | 150 | * |
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| 151 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 152 | */ |
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| 153 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
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| 154 | |
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[baff4da] | 155 | /** |
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[7908ba5b] | 156 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
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| 157 | * |
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| 158 | * If TRUE, then the memory is allocated during initialization. |
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| 159 | * If FALSE, then the memory is allocated during initialization. |
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| 160 | * |
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[22b3bed] | 161 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
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[df49c60] | 162 | * |
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[baff4da] | 163 | * Port Specific Information: |
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[df49c60] | 164 | * |
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| 165 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 166 | */ |
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| 167 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 168 | |
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[baff4da] | 169 | /** |
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[7908ba5b] | 170 | * Does the RTEMS invoke the user's ISR with the vector number and |
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| 171 | * a pointer to the saved interrupt frame (1) or just the vector |
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| 172 | * number (0)? |
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[df49c60] | 173 | * |
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[baff4da] | 174 | * Port Specific Information: |
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[df49c60] | 175 | * |
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| 176 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 177 | */ |
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| 178 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
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| 179 | |
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[baff4da] | 180 | /** |
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| 181 | * @def CPU_HARDWARE_FP |
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| 182 | * |
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[7908ba5b] | 183 | * Does the CPU have hardware floating point? |
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| 184 | * |
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[22b3bed] | 185 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
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| 186 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
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[7908ba5b] | 187 | * |
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| 188 | * If there is a FP coprocessor such as the i387 or mc68881, then |
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| 189 | * the answer is TRUE. |
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| 190 | * |
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| 191 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
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| 192 | * It indicates whether or not this CPU model has FP support. For |
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| 193 | * example, it would be possible to have an i386_nofp CPU model |
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| 194 | * which set this to false to indicate that you have an i386 without |
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| 195 | * an i387 and wish to leave floating point support out of RTEMS. |
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[baff4da] | 196 | */ |
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| 197 | |
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| 198 | /** |
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| 199 | * @def CPU_SOFTWARE_FP |
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| 200 | * |
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| 201 | * Does the CPU have no hardware floating point and GCC provides a |
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| 202 | * software floating point implementation which must be context |
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| 203 | * switched? |
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[df49c60] | 204 | * |
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[baff4da] | 205 | * This feature conditional is used to indicate whether or not there |
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[df49c60] | 206 | * is software implemented floating point that must be context |
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| 207 | * switched. The determination of whether or not this applies |
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| 208 | * is very tool specific and the state saved/restored is also |
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| 209 | * compiler specific. |
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| 210 | * |
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[baff4da] | 211 | * Port Specific Information: |
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[df49c60] | 212 | * |
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| 213 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 214 | */ |
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| 215 | #if ( NO_CPU_HAS_FPU == 1 ) |
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| 216 | #define CPU_HARDWARE_FP TRUE |
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| 217 | #else |
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| 218 | #define CPU_HARDWARE_FP FALSE |
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| 219 | #endif |
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[df49c60] | 220 | #define CPU_SOFTWARE_FP FALSE |
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[7908ba5b] | 221 | |
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[baff4da] | 222 | /** |
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[7908ba5b] | 223 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
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| 224 | * |
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[22b3bed] | 225 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
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| 226 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
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[7908ba5b] | 227 | * |
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[3b1c100] | 228 | * So far, the only CPUs in which this option has been used are the |
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| 229 | * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and |
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| 230 | * gcc both implicitly used the floating point registers to perform |
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| 231 | * integer multiplies. Similarly, the PowerPC port of gcc has been |
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| 232 | * seen to allocate floating point local variables and touch the FPU |
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| 233 | * even when the flow through a subroutine (like vfprintf()) might |
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| 234 | * not use floating point formats. |
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| 235 | * |
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| 236 | * If a function which you would not think utilize the FP unit DOES, |
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[7908ba5b] | 237 | * then one can not easily predict which tasks will use the FP hardware. |
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| 238 | * In this case, this option should be TRUE. |
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| 239 | * |
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[baff4da] | 240 | * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
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[df49c60] | 241 | * |
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[baff4da] | 242 | * Port Specific Information: |
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[df49c60] | 243 | * |
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| 244 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 245 | */ |
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| 246 | #define CPU_ALL_TASKS_ARE_FP TRUE |
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| 247 | |
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[baff4da] | 248 | /** |
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[7908ba5b] | 249 | * Should the IDLE task have a floating point context? |
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| 250 | * |
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[22b3bed] | 251 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
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[7908ba5b] | 252 | * and it has a floating point context which is switched in and out. |
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| 253 | * If FALSE, then the IDLE task does not have a floating point context. |
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| 254 | * |
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| 255 | * Setting this to TRUE negatively impacts the time required to preempt |
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| 256 | * the IDLE task from an interrupt because the floating point context |
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| 257 | * must be saved as part of the preemption. |
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[df49c60] | 258 | * |
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[baff4da] | 259 | * Port Specific Information: |
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[df49c60] | 260 | * |
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| 261 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 262 | */ |
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| 263 | #define CPU_IDLE_TASK_IS_FP FALSE |
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| 264 | |
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[baff4da] | 265 | /** |
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[7908ba5b] | 266 | * Should the saving of the floating point registers be deferred |
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| 267 | * until a context switch is made to another different floating point |
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| 268 | * task? |
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| 269 | * |
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| 270 | * If TRUE, then the floating point context will not be stored until |
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| 271 | * necessary. It will remain in the floating point registers and not |
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| 272 | * disturned until another floating point task is switched to. |
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| 273 | * |
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| 274 | * If FALSE, then the floating point context is saved when a floating |
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| 275 | * point task is switched out and restored when the next floating point |
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| 276 | * task is restored. The state of the floating point registers between |
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| 277 | * those two operations is not specified. |
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| 278 | * |
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| 279 | * If the floating point context does NOT have to be saved as part of |
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| 280 | * interrupt dispatching, then it should be safe to set this to TRUE. |
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| 281 | * |
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| 282 | * Setting this flag to TRUE results in using a different algorithm |
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| 283 | * for deciding when to save and restore the floating point context. |
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| 284 | * The deferred FP switch algorithm minimizes the number of times |
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| 285 | * the FP context is saved and restored. The FP context is not saved |
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| 286 | * until a context switch is made to another, different FP task. |
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| 287 | * Thus in a system with only one FP task, the FP context will never |
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| 288 | * be saved or restored. |
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[df49c60] | 289 | * |
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[baff4da] | 290 | * Port Specific Information: |
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[df49c60] | 291 | * |
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| 292 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 293 | */ |
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| 294 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
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| 295 | |
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[baff4da] | 296 | /** |
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[7908ba5b] | 297 | * Does this port provide a CPU dependent IDLE task implementation? |
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| 298 | * |
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[baff4da] | 299 | * If TRUE, then the routine @ref _CPU_Thread_Idle_body |
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[7908ba5b] | 300 | * must be provided and is the default IDLE thread body instead of |
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[baff4da] | 301 | * @ref _CPU_Thread_Idle_body. |
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[7908ba5b] | 302 | * |
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| 303 | * If FALSE, then use the generic IDLE thread body if the BSP does |
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| 304 | * not provide one. |
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| 305 | * |
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| 306 | * This is intended to allow for supporting processors which have |
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| 307 | * a low power or idle mode. When the IDLE thread is executed, then |
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| 308 | * the CPU can be powered down. |
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| 309 | * |
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| 310 | * The order of precedence for selecting the IDLE thread body is: |
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| 311 | * |
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[baff4da] | 312 | * -# BSP provided |
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| 313 | * -# CPU dependent (if provided) |
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| 314 | * -# generic (if no BSP and no CPU dependent) |
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[df49c60] | 315 | * |
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[baff4da] | 316 | * Port Specific Information: |
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[df49c60] | 317 | * |
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| 318 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 319 | */ |
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| 320 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
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| 321 | |
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[baff4da] | 322 | /** |
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[7908ba5b] | 323 | * Does the stack grow up (toward higher addresses) or down |
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| 324 | * (toward lower addresses)? |
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| 325 | * |
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| 326 | * If TRUE, then the grows upward. |
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| 327 | * If FALSE, then the grows toward smaller addresses. |
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[df49c60] | 328 | * |
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[baff4da] | 329 | * Port Specific Information: |
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[df49c60] | 330 | * |
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| 331 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 332 | */ |
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| 333 | #define CPU_STACK_GROWS_UP TRUE |
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| 334 | |
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[baff4da] | 335 | /** |
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[7908ba5b] | 336 | * The following is the variable attribute used to force alignment |
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| 337 | * of critical RTEMS structures. On some processors it may make |
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| 338 | * sense to have these aligned on tighter boundaries than |
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| 339 | * the minimum requirements of the compiler in order to have as |
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| 340 | * much of the critical data area as possible in a cache line. |
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| 341 | * |
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| 342 | * The placement of this macro in the declaration of the variables |
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| 343 | * is based on the syntactically requirements of the GNU C |
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| 344 | * "__attribute__" extension. For example with GNU C, use |
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| 345 | * the following to force a structures to a 32 byte boundary. |
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| 346 | * |
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| 347 | * __attribute__ ((aligned (32))) |
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| 348 | * |
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[baff4da] | 349 | * @note Currently only the Priority Bit Map table uses this feature. |
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| 350 | * To benefit from using this, the data must be heavily |
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| 351 | * used so it will stay in the cache and used frequently enough |
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| 352 | * in the executive to justify turning this on. |
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[df49c60] | 353 | * |
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[baff4da] | 354 | * Port Specific Information: |
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[df49c60] | 355 | * |
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| 356 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 357 | */ |
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| 358 | #define CPU_STRUCTURE_ALIGNMENT |
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| 359 | |
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[baff4da] | 360 | /** |
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| 361 | * @defgroup CPUEndian Processor Dependent Endianness Support |
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| 362 | * |
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| 363 | * This group assists in issues related to processor endianness. |
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| 364 | */ |
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| 365 | |
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| 366 | /** |
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| 367 | * @ingroup CPUEndian |
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[7908ba5b] | 368 | * Define what is required to specify how the network to host conversion |
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| 369 | * routines are handled. |
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[df49c60] | 370 | * |
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[baff4da] | 371 | * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the |
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| 372 | * same values. |
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| 373 | * |
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| 374 | * @see CPU_LITTLE_ENDIAN |
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| 375 | * |
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| 376 | * Port Specific Information: |
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[df49c60] | 377 | * |
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| 378 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 379 | */ |
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| 380 | #define CPU_BIG_ENDIAN TRUE |
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[baff4da] | 381 | |
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| 382 | /** |
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| 383 | * @ingroup CPUEndian |
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| 384 | * Define what is required to specify how the network to host conversion |
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| 385 | * routines are handled. |
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| 386 | * |
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| 387 | * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the |
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| 388 | * same values. |
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| 389 | * |
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| 390 | * @see CPU_BIG_ENDIAN |
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| 391 | * |
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| 392 | * Port Specific Information: |
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| 393 | * |
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| 394 | * XXX document implementation including references if appropriate |
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| 395 | */ |
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[7908ba5b] | 396 | #define CPU_LITTLE_ENDIAN FALSE |
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| 397 | |
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[baff4da] | 398 | /** |
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| 399 | * @ingroup CPUInterrupt |
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[7908ba5b] | 400 | * The following defines the number of bits actually used in the |
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| 401 | * interrupt field of the task mode. How those bits map to the |
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[baff4da] | 402 | * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. |
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[df49c60] | 403 | * |
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[baff4da] | 404 | * Port Specific Information: |
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[df49c60] | 405 | * |
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| 406 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 407 | */ |
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| 408 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
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| 409 | |
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| 410 | /* |
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[90550fe] | 411 | * Processor defined structures required for cpukit/score. |
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[df49c60] | 412 | * |
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[baff4da] | 413 | * Port Specific Information: |
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[df49c60] | 414 | * |
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| 415 | * XXX document implementation including references if appropriate |
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[7908ba5b] | 416 | */ |
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| 417 | |
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| 418 | /* may need to put some structures here. */ |
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| 419 | |
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[baff4da] | 420 | /** |
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| 421 | * @defgroup CPUContext Processor Dependent Context Management |
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[7908ba5b] | 422 | * |
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[baff4da] | 423 | * From the highest level viewpoint, there are 2 types of context to save. |
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[7908ba5b] | 424 | * |
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[baff4da] | 425 | * -# Interrupt registers to save |
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| 426 | * -# Task level registers to save |
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| 427 | * |
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| 428 | * Since RTEMS handles integer and floating point contexts separately, this |
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| 429 | * means we have the following 3 context items: |
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| 430 | * |
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| 431 | * -# task level context stuff:: Context_Control |
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| 432 | * -# floating point task stuff:: Context_Control_fp |
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| 433 | * -# special interrupt level context :: CPU_Interrupt_frame |
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[7908ba5b] | 434 | * |
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| 435 | * On some processors, it is cost-effective to save only the callee |
---|
| 436 | * preserved registers during a task context switch. This means |
---|
| 437 | * that the ISR code needs to save those registers which do not |
---|
| 438 | * persist across function calls. It is not mandatory to make this |
---|
| 439 | * distinctions between the caller/callee saves registers for the |
---|
| 440 | * purpose of minimizing context saved during task switch and on interrupts. |
---|
| 441 | * If the cost of saving extra registers is minimal, simplicity is the |
---|
| 442 | * choice. Save the same context on interrupt entry as for tasks in |
---|
| 443 | * this case. |
---|
| 444 | * |
---|
| 445 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
---|
| 446 | * care should be used in designing the context area. |
---|
| 447 | * |
---|
| 448 | * On some CPUs with hardware floating point support, the Context_Control_fp |
---|
| 449 | * structure will not be used or it simply consist of an array of a |
---|
| 450 | * fixed number of bytes. This is done when the floating point context |
---|
| 451 | * is dumped by a "FP save context" type instruction and the format |
---|
| 452 | * is not really defined by the CPU. In this case, there is no need |
---|
| 453 | * to figure out the exact format -- only the size. Of course, although |
---|
| 454 | * this is enough information for RTEMS, it is probably not enough for |
---|
| 455 | * a debugger such as gdb. But that is another problem. |
---|
[df49c60] | 456 | * |
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[baff4da] | 457 | * Port Specific Information: |
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[df49c60] | 458 | * |
---|
| 459 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 460 | */ |
---|
| 461 | |
---|
[baff4da] | 462 | /** |
---|
| 463 | * @ingroup CPUContext Management |
---|
| 464 | * This defines the minimal set of integer and processor state registers |
---|
| 465 | * that must be saved during a voluntary context switch from one thread |
---|
| 466 | * to another. |
---|
| 467 | */ |
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[7908ba5b] | 468 | typedef struct { |
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[baff4da] | 469 | /** This field is a hint that a port will have a number of integer |
---|
| 470 | * registers that need to be saved at a context switch. |
---|
| 471 | */ |
---|
[c346f33d] | 472 | uint32_t some_integer_register; |
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[baff4da] | 473 | /** This field is a hint that a port will have a number of system |
---|
| 474 | * registers that need to be saved at a context switch. |
---|
| 475 | */ |
---|
[c346f33d] | 476 | uint32_t some_system_register; |
---|
[0ca6d0d9] | 477 | |
---|
| 478 | /** This field is a hint that a port will have a register that |
---|
| 479 | * is the stack pointer. |
---|
| 480 | */ |
---|
| 481 | uint32_t stack_pointer; |
---|
[7908ba5b] | 482 | } Context_Control; |
---|
| 483 | |
---|
[95e7637] | 484 | /** |
---|
| 485 | * @ingroup CPUContext Management |
---|
| 486 | * |
---|
| 487 | * This macro returns the stack pointer associated with @a _context. |
---|
| 488 | * |
---|
| 489 | * @param[in] _context is the thread context area to access |
---|
| 490 | * |
---|
| 491 | * @return This method returns the stack pointer. |
---|
| 492 | */ |
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[0ca6d0d9] | 493 | #define _CPU_Context_Get_SP( _context ) \ |
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| 494 | (_context)->stack_pointer |
---|
| 495 | |
---|
[baff4da] | 496 | /** |
---|
| 497 | * @ingroup CPUContext Management |
---|
| 498 | * This defines the complete set of floating point registers that must |
---|
| 499 | * be saved during any context switch from one thread to another. |
---|
| 500 | */ |
---|
[7908ba5b] | 501 | typedef struct { |
---|
[22b3bed] | 502 | /** FPU registers are listed here */ |
---|
[7908ba5b] | 503 | double some_float_register; |
---|
| 504 | } Context_Control_fp; |
---|
| 505 | |
---|
[baff4da] | 506 | /** |
---|
| 507 | * @ingroup CPUContext Management |
---|
| 508 | * This defines the set of integer and processor state registers that must |
---|
| 509 | * be saved during an interrupt. This set does not include any which are |
---|
| 510 | * in @ref Context_Control. |
---|
| 511 | */ |
---|
[7908ba5b] | 512 | typedef struct { |
---|
[baff4da] | 513 | /** This field is a hint that a port will have a number of integer |
---|
| 514 | * registers that need to be saved when an interrupt occurs or |
---|
| 515 | * when a context switch occurs at the end of an ISR. |
---|
| 516 | */ |
---|
[c346f33d] | 517 | uint32_t special_interrupt_register; |
---|
[7908ba5b] | 518 | } CPU_Interrupt_frame; |
---|
| 519 | |
---|
[baff4da] | 520 | /** |
---|
[7908ba5b] | 521 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 522 | * to generate an "uninitialized" FP context. It is filled in by |
---|
[baff4da] | 523 | * @ref _CPU_Initialize and copied into the task's FP context area during |
---|
| 524 | * @ref _CPU_Context_Initialize. |
---|
[df49c60] | 525 | * |
---|
[baff4da] | 526 | * Port Specific Information: |
---|
[df49c60] | 527 | * |
---|
| 528 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 529 | */ |
---|
| 530 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
| 531 | |
---|
[baff4da] | 532 | /** |
---|
| 533 | * @defgroup CPUInterrupt Processor Dependent Interrupt Management |
---|
| 534 | * |
---|
[7908ba5b] | 535 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
---|
| 536 | * This stack is allocated by the Interrupt Manager and the switch |
---|
[baff4da] | 537 | * is performed in @ref _ISR_Handler. These variables contain pointers |
---|
[7908ba5b] | 538 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
| 539 | * for the interrupt stack. Since it is unknown whether the stack |
---|
| 540 | * grows up or down (in general), this give the CPU dependent |
---|
| 541 | * code the option of picking the version it wants to use. |
---|
| 542 | * |
---|
[baff4da] | 543 | * @note These two variables are required if the macro |
---|
| 544 | * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
---|
[df49c60] | 545 | * |
---|
[baff4da] | 546 | * Port Specific Information: |
---|
[df49c60] | 547 | * |
---|
| 548 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 549 | */ |
---|
| 550 | |
---|
[baff4da] | 551 | /** |
---|
| 552 | * @ingroup CPUInterrupt |
---|
| 553 | * This variable points to the lowest physical address of the interrupt |
---|
| 554 | * stack. |
---|
| 555 | */ |
---|
[7908ba5b] | 556 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
[baff4da] | 557 | |
---|
| 558 | /** |
---|
| 559 | * @ingroup CPUInterrupt |
---|
| 560 | * This variable points to the lowest physical address of the interrupt |
---|
| 561 | * stack. |
---|
| 562 | */ |
---|
[7908ba5b] | 563 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
| 564 | |
---|
[baff4da] | 565 | /** |
---|
| 566 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 567 | * With some compilation systems, it is difficult if not impossible to |
---|
| 568 | * call a high-level language routine from assembly language. This |
---|
| 569 | * is especially true of commercial Ada compilers and name mangling |
---|
| 570 | * C++ ones. This variable can be optionally defined by the CPU porter |
---|
[baff4da] | 571 | * and contains the address of the routine @ref _Thread_Dispatch. This |
---|
[7908ba5b] | 572 | * can make it easier to invoke that routine at the end of the interrupt |
---|
| 573 | * sequence (if a dispatch is necessary). |
---|
[df49c60] | 574 | * |
---|
[baff4da] | 575 | * Port Specific Information: |
---|
[df49c60] | 576 | * |
---|
| 577 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 578 | */ |
---|
[3d0e458] | 579 | SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(void); |
---|
[7908ba5b] | 580 | |
---|
| 581 | /* |
---|
| 582 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
[df49c60] | 583 | * |
---|
[baff4da] | 584 | * Port Specific Information: |
---|
[df49c60] | 585 | * |
---|
| 586 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 587 | */ |
---|
| 588 | |
---|
| 589 | /* XXX: if needed, put more variables here */ |
---|
| 590 | |
---|
[baff4da] | 591 | /** |
---|
| 592 | * @ingroup CPUContext |
---|
[7908ba5b] | 593 | * The size of the floating point context area. On some CPUs this |
---|
| 594 | * will not be a "sizeof" because the format of the floating point |
---|
| 595 | * area is not defined -- only the size is. This is usually on |
---|
| 596 | * CPUs with a "floating point save context" instruction. |
---|
[df49c60] | 597 | * |
---|
[baff4da] | 598 | * Port Specific Information: |
---|
[df49c60] | 599 | * |
---|
| 600 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 601 | */ |
---|
| 602 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 603 | |
---|
[baff4da] | 604 | /** |
---|
[7908ba5b] | 605 | * Amount of extra stack (above minimum stack size) required by |
---|
| 606 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 607 | * system this thread must exist and be able to process all directives. |
---|
[df49c60] | 608 | * |
---|
[baff4da] | 609 | * Port Specific Information: |
---|
[df49c60] | 610 | * |
---|
| 611 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 612 | */ |
---|
| 613 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 614 | |
---|
[baff4da] | 615 | /** |
---|
| 616 | * @ingroup CPUInterrupt |
---|
| 617 | * This defines the number of entries in the @ref _ISR_Vector_table managed |
---|
[7908ba5b] | 618 | * by RTEMS. |
---|
[df49c60] | 619 | * |
---|
[baff4da] | 620 | * Port Specific Information: |
---|
[df49c60] | 621 | * |
---|
| 622 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 623 | */ |
---|
| 624 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
---|
[baff4da] | 625 | |
---|
| 626 | /** |
---|
| 627 | * @ingroup CPUInterrupt |
---|
| 628 | * This defines the highest interrupt vector number for this port. |
---|
| 629 | */ |
---|
[7908ba5b] | 630 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
| 631 | |
---|
[baff4da] | 632 | /** |
---|
| 633 | * @ingroup CPUInterrupt |
---|
[4db30283] | 634 | * This is defined if the port has a special way to report the ISR nesting |
---|
[baff4da] | 635 | * level. Most ports maintain the variable @a _ISR_Nest_level. |
---|
[4db30283] | 636 | */ |
---|
| 637 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 638 | |
---|
[baff4da] | 639 | /** |
---|
| 640 | * @ingroup CPUContext |
---|
| 641 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[7908ba5b] | 642 | * that a "reasonable" small application should not have any problems. |
---|
[df49c60] | 643 | * |
---|
[baff4da] | 644 | * Port Specific Information: |
---|
[df49c60] | 645 | * |
---|
| 646 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 647 | */ |
---|
| 648 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
| 649 | |
---|
[baff4da] | 650 | /** |
---|
[7908ba5b] | 651 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 652 | * alignment does not take into account the requirements for the stack. |
---|
[df49c60] | 653 | * |
---|
[baff4da] | 654 | * Port Specific Information: |
---|
[df49c60] | 655 | * |
---|
| 656 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 657 | */ |
---|
| 658 | #define CPU_ALIGNMENT 8 |
---|
| 659 | |
---|
[baff4da] | 660 | /** |
---|
[7908ba5b] | 661 | * This number corresponds to the byte alignment requirement for the |
---|
| 662 | * heap handler. This alignment requirement may be stricter than that |
---|
[baff4da] | 663 | * for the data types alignment specified by @ref CPU_ALIGNMENT. It is |
---|
[7908ba5b] | 664 | * common for the heap to follow the same alignment requirement as |
---|
[baff4da] | 665 | * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for |
---|
| 666 | * the heap, then this should be set to @ref CPU_ALIGNMENT. |
---|
[7908ba5b] | 667 | * |
---|
[baff4da] | 668 | * @note This does not have to be a power of 2 although it should be |
---|
[df49c60] | 669 | * a multiple of 2 greater than or equal to 2. The requirement |
---|
| 670 | * to be a multiple of 2 is because the heap uses the least |
---|
| 671 | * significant field of the front and back flags to indicate |
---|
| 672 | * that a block is in use or free. So you do not want any odd |
---|
| 673 | * length blocks really putting length data in that bit. |
---|
| 674 | * |
---|
[baff4da] | 675 | * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will |
---|
| 676 | * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that |
---|
[df49c60] | 677 | * elements allocated from the heap meet all restrictions. |
---|
| 678 | * |
---|
[baff4da] | 679 | * Port Specific Information: |
---|
[df49c60] | 680 | * |
---|
| 681 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 682 | */ |
---|
| 683 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 684 | |
---|
[baff4da] | 685 | /** |
---|
[7908ba5b] | 686 | * This number corresponds to the byte alignment requirement for memory |
---|
| 687 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 688 | * may be stricter than that for the data types alignment specified by |
---|
[baff4da] | 689 | * @ref CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 690 | * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is |
---|
| 691 | * strict enough for the partition, then this should be set to |
---|
| 692 | * @ref CPU_ALIGNMENT. |
---|
[7908ba5b] | 693 | * |
---|
[baff4da] | 694 | * @note This does not have to be a power of 2. It does have to |
---|
| 695 | * be greater or equal to than @ref CPU_ALIGNMENT. |
---|
[df49c60] | 696 | * |
---|
[baff4da] | 697 | * Port Specific Information: |
---|
[df49c60] | 698 | * |
---|
| 699 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 700 | */ |
---|
| 701 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 702 | |
---|
[baff4da] | 703 | /** |
---|
[7908ba5b] | 704 | * This number corresponds to the byte alignment requirement for the |
---|
| 705 | * stack. This alignment requirement may be stricter than that for the |
---|
[baff4da] | 706 | * data types alignment specified by @ref CPU_ALIGNMENT. If the |
---|
| 707 | * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be |
---|
| 708 | * set to 0. |
---|
[7908ba5b] | 709 | * |
---|
[baff4da] | 710 | * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. |
---|
[df49c60] | 711 | * |
---|
[baff4da] | 712 | * Port Specific Information: |
---|
[df49c60] | 713 | * |
---|
| 714 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 715 | */ |
---|
| 716 | #define CPU_STACK_ALIGNMENT 0 |
---|
| 717 | |
---|
[d6ea098] | 718 | /* |
---|
| 719 | * ISR handler macros |
---|
| 720 | */ |
---|
| 721 | |
---|
[baff4da] | 722 | /** |
---|
| 723 | * @ingroup CPUInterrupt |
---|
[d6ea098] | 724 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
| 725 | * |
---|
[baff4da] | 726 | * Port Specific Information: |
---|
[d6ea098] | 727 | * |
---|
| 728 | * XXX document implementation including references if appropriate |
---|
| 729 | */ |
---|
| 730 | #define _CPU_Initialize_vectors() |
---|
[7908ba5b] | 731 | |
---|
[baff4da] | 732 | /** |
---|
| 733 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 734 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
[baff4da] | 735 | * level is returned in @a _isr_cookie. |
---|
| 736 | * |
---|
[22b3bed] | 737 | * @param[out] _isr_cookie will contain the previous level cookie |
---|
[df49c60] | 738 | * |
---|
[baff4da] | 739 | * Port Specific Information: |
---|
[df49c60] | 740 | * |
---|
| 741 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 742 | */ |
---|
| 743 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 744 | { \ |
---|
| 745 | (_isr_cookie) = 0; /* do something to prevent warnings */ \ |
---|
| 746 | } |
---|
| 747 | |
---|
[baff4da] | 748 | /** |
---|
| 749 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 750 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 751 | * This indicates the end of an RTEMS critical section. The parameter |
---|
[baff4da] | 752 | * @a _isr_cookie is not modified. |
---|
| 753 | * |
---|
[22b3bed] | 754 | * @param[in] _isr_cookie contain the previous level cookie |
---|
[df49c60] | 755 | * |
---|
[baff4da] | 756 | * Port Specific Information: |
---|
[df49c60] | 757 | * |
---|
| 758 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 759 | */ |
---|
| 760 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 761 | { \ |
---|
| 762 | } |
---|
| 763 | |
---|
[baff4da] | 764 | /** |
---|
| 765 | * @ingroup CPUInterrupt |
---|
| 766 | * This temporarily restores the interrupt to @a _isr_cookie before immediately |
---|
[7908ba5b] | 767 | * disabling them again. This is used to divide long RTEMS critical |
---|
[baff4da] | 768 | * sections into two or more parts. The parameter @a _isr_cookie is not |
---|
| 769 | * modified. |
---|
| 770 | * |
---|
[22b3bed] | 771 | * @param[in] _isr_cookie contain the previous level cookie |
---|
[df49c60] | 772 | * |
---|
[baff4da] | 773 | * Port Specific Information: |
---|
[df49c60] | 774 | * |
---|
| 775 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 776 | */ |
---|
| 777 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 778 | { \ |
---|
| 779 | } |
---|
| 780 | |
---|
[baff4da] | 781 | /** |
---|
| 782 | * @ingroup CPUInterrupt |
---|
| 783 | * |
---|
| 784 | * This routine and @ref _CPU_ISR_Get_level |
---|
| 785 | * Map the interrupt level in task mode onto the hardware that the CPU |
---|
[7908ba5b] | 786 | * actually provides. Currently, interrupt levels which do not |
---|
| 787 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 788 | * it would be nice if these were "mapped" by the application |
---|
| 789 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 790 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 791 | * This could be used to manage a programmable interrupt controller |
---|
| 792 | * via the rtems_task_mode directive. |
---|
| 793 | * |
---|
[baff4da] | 794 | * Port Specific Information: |
---|
[df49c60] | 795 | * |
---|
| 796 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 797 | */ |
---|
| 798 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
| 799 | { \ |
---|
| 800 | } |
---|
| 801 | |
---|
[baff4da] | 802 | /** |
---|
| 803 | * @ingroup CPUInterrupt |
---|
| 804 | * Return the current interrupt disable level for this task in |
---|
| 805 | * the format used by the interrupt level portion of the task mode. |
---|
| 806 | * |
---|
| 807 | * @note This routine usually must be implemented as a subroutine. |
---|
| 808 | * |
---|
| 809 | * Port Specific Information: |
---|
| 810 | * |
---|
| 811 | * XXX document implementation including references if appropriate |
---|
| 812 | */ |
---|
[c346f33d] | 813 | uint32_t _CPU_ISR_Get_level( void ); |
---|
[7908ba5b] | 814 | |
---|
| 815 | /* end of ISR handler macros */ |
---|
| 816 | |
---|
| 817 | /* Context handler macros */ |
---|
| 818 | |
---|
[baff4da] | 819 | /** |
---|
| 820 | * @ingroup CPUContext |
---|
[7908ba5b] | 821 | * Initialize the context to a state suitable for starting a |
---|
| 822 | * task after a context restore operation. Generally, this |
---|
| 823 | * involves: |
---|
| 824 | * |
---|
| 825 | * - setting a starting address |
---|
| 826 | * - preparing the stack |
---|
| 827 | * - preparing the stack and frame pointers |
---|
| 828 | * - setting the proper interrupt level in the context |
---|
| 829 | * - initializing the floating point context |
---|
| 830 | * |
---|
| 831 | * This routine generally does not set any unnecessary register |
---|
| 832 | * in the context. The state of the "general data" registers is |
---|
| 833 | * undefined at task start time. |
---|
| 834 | * |
---|
[22b3bed] | 835 | * @param[in] _the_context is the context structure to be initialized |
---|
| 836 | * @param[in] _stack_base is the lowest physical address of this task's stack |
---|
| 837 | * @param[in] _size is the size of this task's stack |
---|
| 838 | * @param[in] _isr is the interrupt disable level |
---|
| 839 | * @param[in] _entry_point is the thread's entry point. This is |
---|
[baff4da] | 840 | * always @a _Thread_Handler |
---|
[22b3bed] | 841 | * @param[in] _is_fp is TRUE if the thread is to be a floating |
---|
[7908ba5b] | 842 | * point thread. This is typically only used on CPUs where the |
---|
| 843 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 844 | * where the PSR contains an enable FPU bit. |
---|
[df49c60] | 845 | * |
---|
[baff4da] | 846 | * Port Specific Information: |
---|
[df49c60] | 847 | * |
---|
| 848 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 849 | */ |
---|
| 850 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
| 851 | _isr, _entry_point, _is_fp ) \ |
---|
| 852 | { \ |
---|
| 853 | } |
---|
| 854 | |
---|
[22b3bed] | 855 | /** |
---|
[7908ba5b] | 856 | * This routine is responsible for somehow restarting the currently |
---|
| 857 | * executing task. If you are lucky, then all that is necessary |
---|
| 858 | * is restoring the context. Otherwise, there will need to be |
---|
| 859 | * a special assembly routine which does something special in this |
---|
[22b3bed] | 860 | * case. For many ports, simply adding a label to the restore path |
---|
| 861 | * of @ref _CPU_Context_switch will work. On other ports, it may be |
---|
| 862 | * possibly to load a few arguments and jump to the restore path. It will |
---|
[7908ba5b] | 863 | * not work if restarting self conflicts with the stack frame |
---|
| 864 | * assumptions of restoring a context. |
---|
[df49c60] | 865 | * |
---|
[baff4da] | 866 | * Port Specific Information: |
---|
[df49c60] | 867 | * |
---|
| 868 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 869 | */ |
---|
| 870 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 871 | _CPU_Context_restore( (_the_context) ); |
---|
| 872 | |
---|
[baff4da] | 873 | /** |
---|
| 874 | * @ingroup CPUContext |
---|
[7908ba5b] | 875 | * The purpose of this macro is to allow the initial pointer into |
---|
| 876 | * a floating point context area (used to save the floating point |
---|
| 877 | * context) to be at an arbitrary place in the floating point |
---|
| 878 | * context area. |
---|
| 879 | * |
---|
| 880 | * This is necessary because some FP units are designed to have |
---|
| 881 | * their context saved as a stack which grows into lower addresses. |
---|
| 882 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 883 | * from the base of the context area. Finally some FP units provide |
---|
| 884 | * a "dump context" instruction which could fill in from high to low |
---|
| 885 | * or low to high based on the whim of the CPU designers. |
---|
[df49c60] | 886 | * |
---|
[22b3bed] | 887 | * @param[in] _base is the lowest physical address of the floating point |
---|
[baff4da] | 888 | * context area |
---|
[22b3bed] | 889 | * @param[in] _offset is the offset into the floating point area |
---|
[baff4da] | 890 | * |
---|
| 891 | * Port Specific Information: |
---|
[df49c60] | 892 | * |
---|
| 893 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 894 | */ |
---|
| 895 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 896 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 897 | |
---|
[baff4da] | 898 | /** |
---|
[7908ba5b] | 899 | * This routine initializes the FP context area passed to it to. |
---|
| 900 | * There are a few standard ways in which to initialize the |
---|
| 901 | * floating point context. The code included for this macro assumes |
---|
| 902 | * that this is a CPU in which a "initial" FP context was saved into |
---|
[baff4da] | 903 | * @a _CPU_Null_fp_context and it simply copies it to the destination |
---|
[7908ba5b] | 904 | * context passed to it. |
---|
| 905 | * |
---|
[baff4da] | 906 | * Other floating point context save/restore models include: |
---|
| 907 | * -# not doing anything, and |
---|
| 908 | * -# putting a "null FP status word" in the correct place in the FP context. |
---|
[df49c60] | 909 | * |
---|
[22b3bed] | 910 | * @param[in] _destination is the floating point context area |
---|
[baff4da] | 911 | * |
---|
| 912 | * Port Specific Information: |
---|
[df49c60] | 913 | * |
---|
| 914 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 915 | */ |
---|
| 916 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 917 | { \ |
---|
[b60dc893] | 918 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
[7908ba5b] | 919 | } |
---|
| 920 | |
---|
| 921 | /* end of Context handler macros */ |
---|
| 922 | |
---|
| 923 | /* Fatal Error manager macros */ |
---|
| 924 | |
---|
[baff4da] | 925 | /** |
---|
[7908ba5b] | 926 | * This routine copies _error into a known place -- typically a stack |
---|
| 927 | * location or a register, optionally disables interrupts, and |
---|
| 928 | * halts/stops the CPU. |
---|
[df49c60] | 929 | * |
---|
[baff4da] | 930 | * Port Specific Information: |
---|
[df49c60] | 931 | * |
---|
| 932 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 933 | */ |
---|
| 934 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 935 | { \ |
---|
| 936 | } |
---|
| 937 | |
---|
| 938 | /* end of Fatal Error manager macros */ |
---|
| 939 | |
---|
| 940 | /* Bitfield handler macros */ |
---|
| 941 | |
---|
[baff4da] | 942 | /** |
---|
| 943 | * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation |
---|
| 944 | * |
---|
| 945 | * This set of routines are used to implement fast searches for |
---|
| 946 | * the most important ready task. |
---|
| 947 | */ |
---|
| 948 | |
---|
| 949 | /** |
---|
| 950 | * @ingroup CPUBitfield |
---|
| 951 | * This definition is set to TRUE if the port uses the generic bitfield |
---|
| 952 | * manipulation implementation. |
---|
| 953 | */ |
---|
| 954 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 955 | |
---|
| 956 | /** |
---|
| 957 | * @ingroup CPUBitfield |
---|
| 958 | * This definition is set to TRUE if the port uses the data tables provided |
---|
| 959 | * by the generic bitfield manipulation implementation. |
---|
| 960 | * This can occur when actually using the generic bitfield manipulation |
---|
| 961 | * implementation or when implementing the same algorithm in assembly |
---|
| 962 | * language for improved performance. It is unlikely that a port will use |
---|
| 963 | * the data if it has a bitfield scan instruction. |
---|
| 964 | */ |
---|
| 965 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 966 | |
---|
| 967 | /** |
---|
| 968 | * @ingroup CPUBitfield |
---|
| 969 | * This routine sets @a _output to the bit number of the first bit |
---|
| 970 | * set in @a _value. @a _value is of CPU dependent type |
---|
| 971 | * @a Priority_Bit_map_control. This type may be either 16 or 32 bits |
---|
| 972 | * wide although only the 16 least significant bits will be used. |
---|
[7908ba5b] | 973 | * |
---|
| 974 | * There are a number of variables in using a "find first bit" type |
---|
| 975 | * instruction. |
---|
| 976 | * |
---|
[baff4da] | 977 | * -# What happens when run on a value of zero? |
---|
| 978 | * -# Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 979 | * -# The numbering may be zero or one based. |
---|
| 980 | * -# The "find first bit" instruction may search from MSB or LSB. |
---|
[7908ba5b] | 981 | * |
---|
| 982 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
[baff4da] | 983 | * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and |
---|
| 984 | * @ref _CPU_Priority_bits_index. These three form a set of routines |
---|
[7908ba5b] | 985 | * which must logically operate together. Bits in the _value are |
---|
[baff4da] | 986 | * set and cleared based on masks built by @ref _CPU_Priority_Mask. |
---|
| 987 | * The basic major and minor values calculated by @ref _Priority_Major |
---|
| 988 | * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index |
---|
[7908ba5b] | 989 | * to properly range between the values returned by the "find first bit" |
---|
[baff4da] | 990 | * instruction. This makes it possible for @ref _Priority_Get_highest to |
---|
[7908ba5b] | 991 | * calculate the major and directly index into the minor table. |
---|
| 992 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 993 | * is the first bit found. |
---|
| 994 | * |
---|
| 995 | * This entire "find first bit" and mapping process depends heavily |
---|
| 996 | * on the manner in which a priority is broken into a major and minor |
---|
| 997 | * components with the major being the 4 MSB of a priority and minor |
---|
| 998 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 999 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 1000 | * to the lowest priority. |
---|
| 1001 | * |
---|
| 1002 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 1003 | * there are ways to make do without it. Here are a handful of ways |
---|
| 1004 | * to implement this in software: |
---|
| 1005 | * |
---|
[baff4da] | 1006 | @verbatim |
---|
| 1007 | - a series of 16 bit test instructions |
---|
| 1008 | - a "binary search using if's" |
---|
| 1009 | - _number = 0 |
---|
| 1010 | if _value > 0x00ff |
---|
| 1011 | _value >>=8 |
---|
| 1012 | _number = 8; |
---|
| 1013 | |
---|
| 1014 | if _value > 0x0000f |
---|
| 1015 | _value >=8 |
---|
| 1016 | _number += 4 |
---|
| 1017 | |
---|
| 1018 | _number += bit_set_table[ _value ] |
---|
| 1019 | @endverbatim |
---|
| 1020 | |
---|
[7908ba5b] | 1021 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 1022 | * bit set |
---|
[df49c60] | 1023 | * |
---|
[22b3bed] | 1024 | * @param[in] _value is the value to be scanned |
---|
| 1025 | * @param[in] _output is the first bit set |
---|
[baff4da] | 1026 | * |
---|
| 1027 | * Port Specific Information: |
---|
[df49c60] | 1028 | * |
---|
| 1029 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1030 | */ |
---|
| 1031 | |
---|
| 1032 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1033 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 1034 | { \ |
---|
| 1035 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
| 1036 | } |
---|
| 1037 | #endif |
---|
| 1038 | |
---|
| 1039 | /* end of Bitfield handler macros */ |
---|
| 1040 | |
---|
[baff4da] | 1041 | /** |
---|
[7908ba5b] | 1042 | * This routine builds the mask which corresponds to the bit fields |
---|
[baff4da] | 1043 | * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion |
---|
[7908ba5b] | 1044 | * for that routine. |
---|
[df49c60] | 1045 | * |
---|
[baff4da] | 1046 | * Port Specific Information: |
---|
[df49c60] | 1047 | * |
---|
| 1048 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1049 | */ |
---|
| 1050 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1051 | |
---|
| 1052 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 1053 | ( 1 << (_bit_number) ) |
---|
| 1054 | |
---|
| 1055 | #endif |
---|
| 1056 | |
---|
[baff4da] | 1057 | /** |
---|
| 1058 | * @ingroup CPUBitfield |
---|
[7908ba5b] | 1059 | * This routine translates the bit numbers returned by |
---|
[baff4da] | 1060 | * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as |
---|
[7908ba5b] | 1061 | * a major or minor component of a priority. See the discussion |
---|
| 1062 | * for that routine. |
---|
[df49c60] | 1063 | * |
---|
[22b3bed] | 1064 | * @param[in] _priority is the major or minor number to translate |
---|
[baff4da] | 1065 | * |
---|
| 1066 | * Port Specific Information: |
---|
[df49c60] | 1067 | * |
---|
| 1068 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1069 | */ |
---|
| 1070 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1071 | |
---|
| 1072 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 1073 | (_priority) |
---|
| 1074 | |
---|
| 1075 | #endif |
---|
| 1076 | |
---|
| 1077 | /* end of Priority handler macros */ |
---|
| 1078 | |
---|
| 1079 | /* functions */ |
---|
| 1080 | |
---|
[baff4da] | 1081 | /** |
---|
[7908ba5b] | 1082 | * This routine performs CPU dependent initialization. |
---|
[df49c60] | 1083 | * |
---|
[22b3bed] | 1084 | * @param[in] thread_dispatch is the address of @ref _Thread_Dispatch |
---|
[baff4da] | 1085 | * |
---|
| 1086 | * Port Specific Information: |
---|
[df49c60] | 1087 | * |
---|
| 1088 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1089 | */ |
---|
| 1090 | void _CPU_Initialize( |
---|
| 1091 | void (*thread_dispatch) |
---|
| 1092 | ); |
---|
| 1093 | |
---|
[baff4da] | 1094 | /** |
---|
| 1095 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 1096 | * This routine installs a "raw" interrupt handler directly into the |
---|
| 1097 | * processor's vector table. |
---|
[df49c60] | 1098 | * |
---|
[22b3bed] | 1099 | * @param[in] vector is the vector number |
---|
| 1100 | * @param[in] new_handler is the raw ISR handler to install |
---|
| 1101 | * @param[in] old_handler is the previously installed ISR Handler |
---|
[baff4da] | 1102 | * |
---|
| 1103 | * Port Specific Information: |
---|
[df49c60] | 1104 | * |
---|
| 1105 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1106 | */ |
---|
| 1107 | void _CPU_ISR_install_raw_handler( |
---|
[c346f33d] | 1108 | uint32_t vector, |
---|
[7908ba5b] | 1109 | proc_ptr new_handler, |
---|
| 1110 | proc_ptr *old_handler |
---|
| 1111 | ); |
---|
| 1112 | |
---|
[baff4da] | 1113 | /** |
---|
| 1114 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 1115 | * This routine installs an interrupt vector. |
---|
[df49c60] | 1116 | * |
---|
[22b3bed] | 1117 | * @param[in] vector is the vector number |
---|
| 1118 | * @param[in] new_handler is the RTEMS ISR handler to install |
---|
| 1119 | * @param[in] old_handler is the previously installed ISR Handler |
---|
[baff4da] | 1120 | * |
---|
| 1121 | * Port Specific Information: |
---|
[df49c60] | 1122 | * |
---|
| 1123 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1124 | */ |
---|
| 1125 | void _CPU_ISR_install_vector( |
---|
[c346f33d] | 1126 | uint32_t vector, |
---|
[7908ba5b] | 1127 | proc_ptr new_handler, |
---|
| 1128 | proc_ptr *old_handler |
---|
| 1129 | ); |
---|
| 1130 | |
---|
[baff4da] | 1131 | /** |
---|
| 1132 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 1133 | * This routine installs the hardware interrupt stack pointer. |
---|
| 1134 | * |
---|
[baff4da] | 1135 | * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
[7908ba5b] | 1136 | * is TRUE. |
---|
[df49c60] | 1137 | * |
---|
[baff4da] | 1138 | * Port Specific Information: |
---|
[df49c60] | 1139 | * |
---|
| 1140 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1141 | */ |
---|
| 1142 | void _CPU_Install_interrupt_stack( void ); |
---|
| 1143 | |
---|
[baff4da] | 1144 | /** |
---|
[7908ba5b] | 1145 | * This routine is the CPU dependent IDLE thread body. |
---|
| 1146 | * |
---|
[baff4da] | 1147 | * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY |
---|
[7908ba5b] | 1148 | * is TRUE. |
---|
[df49c60] | 1149 | * |
---|
[baff4da] | 1150 | * Port Specific Information: |
---|
[df49c60] | 1151 | * |
---|
| 1152 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1153 | */ |
---|
[3c87adba] | 1154 | void *_CPU_Thread_Idle_body( uint32_t ); |
---|
[7908ba5b] | 1155 | |
---|
[baff4da] | 1156 | /** |
---|
| 1157 | * @ingroup CPUContext |
---|
[7908ba5b] | 1158 | * This routine switches from the run context to the heir context. |
---|
[df49c60] | 1159 | * |
---|
[22b3bed] | 1160 | * @param[in] run points to the context of the currently executing task |
---|
| 1161 | * @param[in] heir points to the context of the heir task |
---|
[baff4da] | 1162 | * |
---|
| 1163 | * Port Specific Information: |
---|
[df49c60] | 1164 | * |
---|
| 1165 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1166 | */ |
---|
| 1167 | void _CPU_Context_switch( |
---|
| 1168 | Context_Control *run, |
---|
| 1169 | Context_Control *heir |
---|
| 1170 | ); |
---|
| 1171 | |
---|
[baff4da] | 1172 | /** |
---|
| 1173 | * @ingroup CPUContext |
---|
[7908ba5b] | 1174 | * This routine is generally used only to restart self in an |
---|
[baff4da] | 1175 | * efficient manner. It may simply be a label in @ref _CPU_Context_switch. |
---|
[7908ba5b] | 1176 | * |
---|
[22b3bed] | 1177 | * @param[in] new_context points to the context to be restored. |
---|
[df49c60] | 1178 | * |
---|
[baff4da] | 1179 | * @note May be unnecessary to reload some registers. |
---|
| 1180 | * |
---|
| 1181 | * Port Specific Information: |
---|
[df49c60] | 1182 | * |
---|
| 1183 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1184 | */ |
---|
| 1185 | void _CPU_Context_restore( |
---|
| 1186 | Context_Control *new_context |
---|
| 1187 | ); |
---|
| 1188 | |
---|
[baff4da] | 1189 | /** |
---|
| 1190 | * @ingroup CPUContext |
---|
[7908ba5b] | 1191 | * This routine saves the floating point context passed to it. |
---|
[df49c60] | 1192 | * |
---|
[22b3bed] | 1193 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
[baff4da] | 1194 | * point context area |
---|
| 1195 | * |
---|
| 1196 | * @return on output @a *fp_context_ptr will contain the address that |
---|
| 1197 | * should be used with @ref _CPU_Context_restore_fp to restore this context. |
---|
| 1198 | * |
---|
| 1199 | * Port Specific Information: |
---|
[df49c60] | 1200 | * |
---|
| 1201 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1202 | */ |
---|
| 1203 | void _CPU_Context_save_fp( |
---|
[b60dc893] | 1204 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1205 | ); |
---|
| 1206 | |
---|
[baff4da] | 1207 | /** |
---|
| 1208 | * @ingroup CPUContext |
---|
[7908ba5b] | 1209 | * This routine restores the floating point context passed to it. |
---|
[df49c60] | 1210 | * |
---|
[22b3bed] | 1211 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
[baff4da] | 1212 | * point context area to restore |
---|
| 1213 | * |
---|
| 1214 | * @return on output @a *fp_context_ptr will contain the address that |
---|
| 1215 | * should be used with @ref _CPU_Context_save_fp to save this context. |
---|
| 1216 | * |
---|
| 1217 | * Port Specific Information: |
---|
[df49c60] | 1218 | * |
---|
| 1219 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1220 | */ |
---|
| 1221 | void _CPU_Context_restore_fp( |
---|
[b60dc893] | 1222 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1223 | ); |
---|
| 1224 | |
---|
[baff4da] | 1225 | /** |
---|
| 1226 | * @ingroup CPUEndian |
---|
| 1227 | * The following routine swaps the endian format of an unsigned int. |
---|
[7908ba5b] | 1228 | * It must be static because it is referenced indirectly. |
---|
| 1229 | * |
---|
| 1230 | * This version will work on any processor, but if there is a better |
---|
| 1231 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 1232 | * |
---|
| 1233 | * swap least significant two bytes with 16-bit rotate |
---|
| 1234 | * swap upper and lower 16-bits |
---|
| 1235 | * swap most significant two bytes with 16-bit rotate |
---|
| 1236 | * |
---|
| 1237 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 1238 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 1239 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[22b3bed] | 1240 | * that interrupts would probably have to be disabled to ensure that |
---|
[7908ba5b] | 1241 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 1242 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 1243 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 1244 | * will be fetched incorrectly. |
---|
[df49c60] | 1245 | * |
---|
[22b3bed] | 1246 | * @param[in] value is the value to be swapped |
---|
[baff4da] | 1247 | * @return the value after being endian swapped |
---|
| 1248 | * |
---|
| 1249 | * Port Specific Information: |
---|
[df49c60] | 1250 | * |
---|
| 1251 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1252 | */ |
---|
[ec8973ed] | 1253 | static inline uint32_t CPU_swap_u32( |
---|
| 1254 | uint32_t value |
---|
[7908ba5b] | 1255 | ) |
---|
| 1256 | { |
---|
[5c5d438] | 1257 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[7908ba5b] | 1258 | |
---|
| 1259 | byte4 = (value >> 24) & 0xff; |
---|
| 1260 | byte3 = (value >> 16) & 0xff; |
---|
| 1261 | byte2 = (value >> 8) & 0xff; |
---|
| 1262 | byte1 = value & 0xff; |
---|
| 1263 | |
---|
| 1264 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
[5c5d438] | 1265 | return swapped; |
---|
[7908ba5b] | 1266 | } |
---|
| 1267 | |
---|
[baff4da] | 1268 | /** |
---|
| 1269 | * @ingroup CPUEndian |
---|
| 1270 | * This routine swaps a 16 bir quantity. |
---|
| 1271 | * |
---|
[22b3bed] | 1272 | * @param[in] value is the value to be swapped |
---|
[baff4da] | 1273 | * @return the value after being endian swapped |
---|
| 1274 | */ |
---|
[7908ba5b] | 1275 | #define CPU_swap_u16( value ) \ |
---|
| 1276 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 1277 | |
---|
| 1278 | #ifdef __cplusplus |
---|
| 1279 | } |
---|
| 1280 | #endif |
---|
| 1281 | |
---|
| 1282 | #endif |
---|