[77d3533f] | 1 | /** |
---|
| 2 | * @file rtems/score/cpu.h |
---|
| 3 | */ |
---|
| 4 | |
---|
| 5 | /* |
---|
[7908ba5b] | 6 | * This include file contains information pertaining to the XXX |
---|
| 7 | * processor. |
---|
| 8 | * |
---|
[baff4da] | 9 | * @note This file is part of a porting template that is intended |
---|
| 10 | * to be used as the starting point when porting RTEMS to a new |
---|
| 11 | * CPU family. The following needs to be done when using this as |
---|
| 12 | * the starting point for a new port: |
---|
| 13 | * |
---|
| 14 | * + Anywhere there is an XXX, it should be replaced |
---|
| 15 | * with information about the CPU family being ported to. |
---|
| 16 | * |
---|
| 17 | * + At the end of each comment section, there is a heading which |
---|
| 18 | * says "Port Specific Information:". When porting to RTEMS, |
---|
| 19 | * add CPU family specific information in this section |
---|
| 20 | */ |
---|
| 21 | |
---|
[22b3bed] | 22 | /* COPYRIGHT (c) 1989-2006. |
---|
[7908ba5b] | 23 | * On-Line Applications Research Corporation (OAR). |
---|
| 24 | * |
---|
| 25 | * The license and distribution terms for this file may be |
---|
| 26 | * found in the file LICENSE in this distribution or at |
---|
[f226687] | 27 | * http://www.rtems.com/license/LICENSE. |
---|
[7908ba5b] | 28 | * |
---|
| 29 | * $Id$ |
---|
| 30 | */ |
---|
| 31 | |
---|
[7f70d1b7] | 32 | #ifndef _RTEMS_SCORE_CPU_H |
---|
| 33 | #define _RTEMS_SCORE_CPU_H |
---|
[7908ba5b] | 34 | |
---|
| 35 | #ifdef __cplusplus |
---|
| 36 | extern "C" { |
---|
| 37 | #endif |
---|
| 38 | |
---|
| 39 | #include <rtems/score/no_cpu.h> /* pick up machine definitions */ |
---|
| 40 | #ifndef ASM |
---|
[14c8ef9] | 41 | #include <rtems/score/types.h> |
---|
[7908ba5b] | 42 | #endif |
---|
| 43 | |
---|
| 44 | /* conditional compilation parameters */ |
---|
| 45 | |
---|
[baff4da] | 46 | /** |
---|
| 47 | * Should the calls to @ref _Thread_Enable_dispatch be inlined? |
---|
[7908ba5b] | 48 | * |
---|
| 49 | * If TRUE, then they are inlined. |
---|
| 50 | * If FALSE, then a subroutine call is made. |
---|
| 51 | * |
---|
[baff4da] | 52 | * This conditional is an example of the classic trade-off of size |
---|
[7908ba5b] | 53 | * versus speed. Inlining the call (TRUE) typically increases the |
---|
| 54 | * size of RTEMS while speeding up the enabling of dispatching. |
---|
[baff4da] | 55 | * |
---|
| 56 | * @note In general, the @ref _Thread_Dispatch_disable_level will |
---|
[7908ba5b] | 57 | * only be 0 or 1 unless you are in an interrupt handler and that |
---|
| 58 | * interrupt handler invokes the executive.] When not inlined |
---|
[baff4da] | 59 | * something calls @ref _Thread_Enable_dispatch which in turns calls |
---|
| 60 | * @ref _Thread_Dispatch. If the enable dispatch is inlined, then |
---|
| 61 | * one subroutine call is avoided entirely. |
---|
[df49c60] | 62 | * |
---|
[baff4da] | 63 | * Port Specific Information: |
---|
[df49c60] | 64 | * |
---|
| 65 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 66 | */ |
---|
| 67 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
---|
| 68 | |
---|
[baff4da] | 69 | /** |
---|
[7908ba5b] | 70 | * Should the body of the search loops in _Thread_queue_Enqueue_priority |
---|
| 71 | * be unrolled one time? In unrolled each iteration of the loop examines |
---|
| 72 | * two "nodes" on the chain being searched. Otherwise, only one node |
---|
| 73 | * is examined per iteration. |
---|
| 74 | * |
---|
| 75 | * If TRUE, then the loops are unrolled. |
---|
| 76 | * If FALSE, then the loops are not unrolled. |
---|
| 77 | * |
---|
| 78 | * The primary factor in making this decision is the cost of disabling |
---|
| 79 | * and enabling interrupts (_ISR_Flash) versus the cost of rest of the |
---|
| 80 | * body of the loop. On some CPUs, the flash is more expensive than |
---|
| 81 | * one iteration of the loop body. In this case, it might be desirable |
---|
| 82 | * to unroll the loop. It is important to note that on some CPUs, this |
---|
| 83 | * code is the longest interrupt disable period in RTEMS. So it is |
---|
| 84 | * necessary to strike a balance when setting this parameter. |
---|
[df49c60] | 85 | * |
---|
[baff4da] | 86 | * Port Specific Information: |
---|
[df49c60] | 87 | * |
---|
| 88 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 89 | */ |
---|
| 90 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
---|
| 91 | |
---|
[baff4da] | 92 | /** |
---|
[7908ba5b] | 93 | * Does RTEMS manage a dedicated interrupt stack in software? |
---|
| 94 | * |
---|
[baff4da] | 95 | * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization. |
---|
[7908ba5b] | 96 | * If FALSE, nothing is done. |
---|
| 97 | * |
---|
| 98 | * If the CPU supports a dedicated interrupt stack in hardware, |
---|
| 99 | * then it is generally the responsibility of the BSP to allocate it |
---|
| 100 | * and set it up. |
---|
| 101 | * |
---|
| 102 | * If the CPU does not support a dedicated interrupt stack, then |
---|
| 103 | * the porter has two options: (1) execute interrupts on the |
---|
| 104 | * stack of the interrupted task, and (2) have RTEMS manage a dedicated |
---|
| 105 | * interrupt stack. |
---|
| 106 | * |
---|
[baff4da] | 107 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
[7908ba5b] | 108 | * |
---|
[baff4da] | 109 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 110 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
[7908ba5b] | 111 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 112 | * is unclear what that would imply about the interrupt processing |
---|
| 113 | * procedure on that CPU. |
---|
[df49c60] | 114 | * |
---|
[baff4da] | 115 | * Port Specific Information: |
---|
[df49c60] | 116 | * |
---|
| 117 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 118 | */ |
---|
| 119 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE |
---|
| 120 | |
---|
[baff4da] | 121 | /** |
---|
[7908ba5b] | 122 | * Does this CPU have hardware support for a dedicated interrupt stack? |
---|
| 123 | * |
---|
| 124 | * If TRUE, then it must be installed during initialization. |
---|
| 125 | * If FALSE, then no installation is performed. |
---|
| 126 | * |
---|
[baff4da] | 127 | * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE. |
---|
[7908ba5b] | 128 | * |
---|
[baff4da] | 129 | * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and |
---|
| 130 | * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE. It is |
---|
[7908ba5b] | 131 | * possible that both are FALSE for a particular CPU. Although it |
---|
| 132 | * is unclear what that would imply about the interrupt processing |
---|
| 133 | * procedure on that CPU. |
---|
[df49c60] | 134 | * |
---|
[baff4da] | 135 | * Port Specific Information: |
---|
[df49c60] | 136 | * |
---|
| 137 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 138 | */ |
---|
| 139 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE |
---|
| 140 | |
---|
[baff4da] | 141 | /** |
---|
[7908ba5b] | 142 | * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager? |
---|
| 143 | * |
---|
| 144 | * If TRUE, then the memory is allocated during initialization. |
---|
| 145 | * If FALSE, then the memory is allocated during initialization. |
---|
| 146 | * |
---|
[22b3bed] | 147 | * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE. |
---|
[df49c60] | 148 | * |
---|
[baff4da] | 149 | * Port Specific Information: |
---|
[df49c60] | 150 | * |
---|
| 151 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 152 | */ |
---|
| 153 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
---|
| 154 | |
---|
[baff4da] | 155 | /** |
---|
[7908ba5b] | 156 | * Does the RTEMS invoke the user's ISR with the vector number and |
---|
| 157 | * a pointer to the saved interrupt frame (1) or just the vector |
---|
| 158 | * number (0)? |
---|
[df49c60] | 159 | * |
---|
[baff4da] | 160 | * Port Specific Information: |
---|
[df49c60] | 161 | * |
---|
| 162 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 163 | */ |
---|
| 164 | #define CPU_ISR_PASSES_FRAME_POINTER 0 |
---|
| 165 | |
---|
[baff4da] | 166 | /** |
---|
| 167 | * @def CPU_HARDWARE_FP |
---|
| 168 | * |
---|
[7908ba5b] | 169 | * Does the CPU have hardware floating point? |
---|
| 170 | * |
---|
[22b3bed] | 171 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported. |
---|
| 172 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored. |
---|
[7908ba5b] | 173 | * |
---|
| 174 | * If there is a FP coprocessor such as the i387 or mc68881, then |
---|
| 175 | * the answer is TRUE. |
---|
| 176 | * |
---|
| 177 | * The macro name "NO_CPU_HAS_FPU" should be made CPU specific. |
---|
| 178 | * It indicates whether or not this CPU model has FP support. For |
---|
| 179 | * example, it would be possible to have an i386_nofp CPU model |
---|
| 180 | * which set this to false to indicate that you have an i386 without |
---|
| 181 | * an i387 and wish to leave floating point support out of RTEMS. |
---|
[baff4da] | 182 | */ |
---|
| 183 | |
---|
| 184 | /** |
---|
| 185 | * @def CPU_SOFTWARE_FP |
---|
| 186 | * |
---|
| 187 | * Does the CPU have no hardware floating point and GCC provides a |
---|
| 188 | * software floating point implementation which must be context |
---|
| 189 | * switched? |
---|
[df49c60] | 190 | * |
---|
[baff4da] | 191 | * This feature conditional is used to indicate whether or not there |
---|
[df49c60] | 192 | * is software implemented floating point that must be context |
---|
| 193 | * switched. The determination of whether or not this applies |
---|
| 194 | * is very tool specific and the state saved/restored is also |
---|
| 195 | * compiler specific. |
---|
| 196 | * |
---|
[baff4da] | 197 | * Port Specific Information: |
---|
[df49c60] | 198 | * |
---|
| 199 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 200 | */ |
---|
| 201 | #if ( NO_CPU_HAS_FPU == 1 ) |
---|
| 202 | #define CPU_HARDWARE_FP TRUE |
---|
| 203 | #else |
---|
| 204 | #define CPU_HARDWARE_FP FALSE |
---|
| 205 | #endif |
---|
[df49c60] | 206 | #define CPU_SOFTWARE_FP FALSE |
---|
[7908ba5b] | 207 | |
---|
[baff4da] | 208 | /** |
---|
[7908ba5b] | 209 | * Are all tasks RTEMS_FLOATING_POINT tasks implicitly? |
---|
| 210 | * |
---|
[22b3bed] | 211 | * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed. |
---|
| 212 | * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed. |
---|
[7908ba5b] | 213 | * |
---|
[3b1c100] | 214 | * So far, the only CPUs in which this option has been used are the |
---|
| 215 | * HP PA-RISC and PowerPC. On the PA-RISC, The HP C compiler and |
---|
| 216 | * gcc both implicitly used the floating point registers to perform |
---|
| 217 | * integer multiplies. Similarly, the PowerPC port of gcc has been |
---|
| 218 | * seen to allocate floating point local variables and touch the FPU |
---|
| 219 | * even when the flow through a subroutine (like vfprintf()) might |
---|
| 220 | * not use floating point formats. |
---|
| 221 | * |
---|
| 222 | * If a function which you would not think utilize the FP unit DOES, |
---|
[7908ba5b] | 223 | * then one can not easily predict which tasks will use the FP hardware. |
---|
| 224 | * In this case, this option should be TRUE. |
---|
| 225 | * |
---|
[baff4da] | 226 | * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well. |
---|
[df49c60] | 227 | * |
---|
[baff4da] | 228 | * Port Specific Information: |
---|
[df49c60] | 229 | * |
---|
| 230 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 231 | */ |
---|
| 232 | #define CPU_ALL_TASKS_ARE_FP TRUE |
---|
| 233 | |
---|
[baff4da] | 234 | /** |
---|
[7908ba5b] | 235 | * Should the IDLE task have a floating point context? |
---|
| 236 | * |
---|
[22b3bed] | 237 | * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task |
---|
[7908ba5b] | 238 | * and it has a floating point context which is switched in and out. |
---|
| 239 | * If FALSE, then the IDLE task does not have a floating point context. |
---|
| 240 | * |
---|
| 241 | * Setting this to TRUE negatively impacts the time required to preempt |
---|
| 242 | * the IDLE task from an interrupt because the floating point context |
---|
| 243 | * must be saved as part of the preemption. |
---|
[df49c60] | 244 | * |
---|
[baff4da] | 245 | * Port Specific Information: |
---|
[df49c60] | 246 | * |
---|
| 247 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 248 | */ |
---|
| 249 | #define CPU_IDLE_TASK_IS_FP FALSE |
---|
| 250 | |
---|
[baff4da] | 251 | /** |
---|
[7908ba5b] | 252 | * Should the saving of the floating point registers be deferred |
---|
| 253 | * until a context switch is made to another different floating point |
---|
| 254 | * task? |
---|
| 255 | * |
---|
| 256 | * If TRUE, then the floating point context will not be stored until |
---|
| 257 | * necessary. It will remain in the floating point registers and not |
---|
| 258 | * disturned until another floating point task is switched to. |
---|
| 259 | * |
---|
| 260 | * If FALSE, then the floating point context is saved when a floating |
---|
| 261 | * point task is switched out and restored when the next floating point |
---|
| 262 | * task is restored. The state of the floating point registers between |
---|
| 263 | * those two operations is not specified. |
---|
| 264 | * |
---|
| 265 | * If the floating point context does NOT have to be saved as part of |
---|
| 266 | * interrupt dispatching, then it should be safe to set this to TRUE. |
---|
| 267 | * |
---|
| 268 | * Setting this flag to TRUE results in using a different algorithm |
---|
| 269 | * for deciding when to save and restore the floating point context. |
---|
| 270 | * The deferred FP switch algorithm minimizes the number of times |
---|
| 271 | * the FP context is saved and restored. The FP context is not saved |
---|
| 272 | * until a context switch is made to another, different FP task. |
---|
| 273 | * Thus in a system with only one FP task, the FP context will never |
---|
| 274 | * be saved or restored. |
---|
[df49c60] | 275 | * |
---|
[baff4da] | 276 | * Port Specific Information: |
---|
[df49c60] | 277 | * |
---|
| 278 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 279 | */ |
---|
| 280 | #define CPU_USE_DEFERRED_FP_SWITCH TRUE |
---|
| 281 | |
---|
[baff4da] | 282 | /** |
---|
[7908ba5b] | 283 | * Does this port provide a CPU dependent IDLE task implementation? |
---|
| 284 | * |
---|
[baff4da] | 285 | * If TRUE, then the routine @ref _CPU_Thread_Idle_body |
---|
[7908ba5b] | 286 | * must be provided and is the default IDLE thread body instead of |
---|
[baff4da] | 287 | * @ref _CPU_Thread_Idle_body. |
---|
[7908ba5b] | 288 | * |
---|
| 289 | * If FALSE, then use the generic IDLE thread body if the BSP does |
---|
| 290 | * not provide one. |
---|
| 291 | * |
---|
| 292 | * This is intended to allow for supporting processors which have |
---|
| 293 | * a low power or idle mode. When the IDLE thread is executed, then |
---|
| 294 | * the CPU can be powered down. |
---|
| 295 | * |
---|
| 296 | * The order of precedence for selecting the IDLE thread body is: |
---|
| 297 | * |
---|
[baff4da] | 298 | * -# BSP provided |
---|
| 299 | * -# CPU dependent (if provided) |
---|
| 300 | * -# generic (if no BSP and no CPU dependent) |
---|
[df49c60] | 301 | * |
---|
[baff4da] | 302 | * Port Specific Information: |
---|
[df49c60] | 303 | * |
---|
| 304 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 305 | */ |
---|
| 306 | #define CPU_PROVIDES_IDLE_THREAD_BODY TRUE |
---|
| 307 | |
---|
[baff4da] | 308 | /** |
---|
[7908ba5b] | 309 | * Does the stack grow up (toward higher addresses) or down |
---|
| 310 | * (toward lower addresses)? |
---|
| 311 | * |
---|
| 312 | * If TRUE, then the grows upward. |
---|
| 313 | * If FALSE, then the grows toward smaller addresses. |
---|
[df49c60] | 314 | * |
---|
[baff4da] | 315 | * Port Specific Information: |
---|
[df49c60] | 316 | * |
---|
| 317 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 318 | */ |
---|
| 319 | #define CPU_STACK_GROWS_UP TRUE |
---|
| 320 | |
---|
[baff4da] | 321 | /** |
---|
[7908ba5b] | 322 | * The following is the variable attribute used to force alignment |
---|
| 323 | * of critical RTEMS structures. On some processors it may make |
---|
| 324 | * sense to have these aligned on tighter boundaries than |
---|
| 325 | * the minimum requirements of the compiler in order to have as |
---|
| 326 | * much of the critical data area as possible in a cache line. |
---|
| 327 | * |
---|
| 328 | * The placement of this macro in the declaration of the variables |
---|
| 329 | * is based on the syntactically requirements of the GNU C |
---|
| 330 | * "__attribute__" extension. For example with GNU C, use |
---|
| 331 | * the following to force a structures to a 32 byte boundary. |
---|
| 332 | * |
---|
| 333 | * __attribute__ ((aligned (32))) |
---|
| 334 | * |
---|
[baff4da] | 335 | * @note Currently only the Priority Bit Map table uses this feature. |
---|
| 336 | * To benefit from using this, the data must be heavily |
---|
| 337 | * used so it will stay in the cache and used frequently enough |
---|
| 338 | * in the executive to justify turning this on. |
---|
[df49c60] | 339 | * |
---|
[baff4da] | 340 | * Port Specific Information: |
---|
[df49c60] | 341 | * |
---|
| 342 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 343 | */ |
---|
| 344 | #define CPU_STRUCTURE_ALIGNMENT |
---|
| 345 | |
---|
[baff4da] | 346 | /** |
---|
| 347 | * @defgroup CPUEndian Processor Dependent Endianness Support |
---|
| 348 | * |
---|
| 349 | * This group assists in issues related to processor endianness. |
---|
| 350 | */ |
---|
| 351 | |
---|
| 352 | /** |
---|
| 353 | * @ingroup CPUEndian |
---|
[7908ba5b] | 354 | * Define what is required to specify how the network to host conversion |
---|
| 355 | * routines are handled. |
---|
[df49c60] | 356 | * |
---|
[baff4da] | 357 | * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the |
---|
| 358 | * same values. |
---|
| 359 | * |
---|
| 360 | * @see CPU_LITTLE_ENDIAN |
---|
| 361 | * |
---|
| 362 | * Port Specific Information: |
---|
[df49c60] | 363 | * |
---|
| 364 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 365 | */ |
---|
| 366 | #define CPU_BIG_ENDIAN TRUE |
---|
[baff4da] | 367 | |
---|
| 368 | /** |
---|
| 369 | * @ingroup CPUEndian |
---|
| 370 | * Define what is required to specify how the network to host conversion |
---|
| 371 | * routines are handled. |
---|
| 372 | * |
---|
| 373 | * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the |
---|
| 374 | * same values. |
---|
| 375 | * |
---|
| 376 | * @see CPU_BIG_ENDIAN |
---|
| 377 | * |
---|
| 378 | * Port Specific Information: |
---|
| 379 | * |
---|
| 380 | * XXX document implementation including references if appropriate |
---|
| 381 | */ |
---|
[7908ba5b] | 382 | #define CPU_LITTLE_ENDIAN FALSE |
---|
| 383 | |
---|
[baff4da] | 384 | /** |
---|
| 385 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 386 | * The following defines the number of bits actually used in the |
---|
| 387 | * interrupt field of the task mode. How those bits map to the |
---|
[baff4da] | 388 | * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level. |
---|
[df49c60] | 389 | * |
---|
[baff4da] | 390 | * Port Specific Information: |
---|
[df49c60] | 391 | * |
---|
| 392 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 393 | */ |
---|
| 394 | #define CPU_MODES_INTERRUPT_MASK 0x00000001 |
---|
| 395 | |
---|
| 396 | /* |
---|
[90550fe] | 397 | * Processor defined structures required for cpukit/score. |
---|
[df49c60] | 398 | * |
---|
[baff4da] | 399 | * Port Specific Information: |
---|
[df49c60] | 400 | * |
---|
| 401 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 402 | */ |
---|
| 403 | |
---|
| 404 | /* may need to put some structures here. */ |
---|
| 405 | |
---|
[baff4da] | 406 | /** |
---|
| 407 | * @defgroup CPUContext Processor Dependent Context Management |
---|
[7908ba5b] | 408 | * |
---|
[baff4da] | 409 | * From the highest level viewpoint, there are 2 types of context to save. |
---|
[7908ba5b] | 410 | * |
---|
[baff4da] | 411 | * -# Interrupt registers to save |
---|
| 412 | * -# Task level registers to save |
---|
| 413 | * |
---|
| 414 | * Since RTEMS handles integer and floating point contexts separately, this |
---|
| 415 | * means we have the following 3 context items: |
---|
| 416 | * |
---|
| 417 | * -# task level context stuff:: Context_Control |
---|
| 418 | * -# floating point task stuff:: Context_Control_fp |
---|
| 419 | * -# special interrupt level context :: CPU_Interrupt_frame |
---|
[7908ba5b] | 420 | * |
---|
| 421 | * On some processors, it is cost-effective to save only the callee |
---|
| 422 | * preserved registers during a task context switch. This means |
---|
| 423 | * that the ISR code needs to save those registers which do not |
---|
| 424 | * persist across function calls. It is not mandatory to make this |
---|
| 425 | * distinctions between the caller/callee saves registers for the |
---|
| 426 | * purpose of minimizing context saved during task switch and on interrupts. |
---|
| 427 | * If the cost of saving extra registers is minimal, simplicity is the |
---|
| 428 | * choice. Save the same context on interrupt entry as for tasks in |
---|
| 429 | * this case. |
---|
| 430 | * |
---|
| 431 | * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then |
---|
| 432 | * care should be used in designing the context area. |
---|
| 433 | * |
---|
| 434 | * On some CPUs with hardware floating point support, the Context_Control_fp |
---|
| 435 | * structure will not be used or it simply consist of an array of a |
---|
| 436 | * fixed number of bytes. This is done when the floating point context |
---|
| 437 | * is dumped by a "FP save context" type instruction and the format |
---|
| 438 | * is not really defined by the CPU. In this case, there is no need |
---|
| 439 | * to figure out the exact format -- only the size. Of course, although |
---|
| 440 | * this is enough information for RTEMS, it is probably not enough for |
---|
| 441 | * a debugger such as gdb. But that is another problem. |
---|
[df49c60] | 442 | * |
---|
[baff4da] | 443 | * Port Specific Information: |
---|
[df49c60] | 444 | * |
---|
| 445 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 446 | */ |
---|
| 447 | |
---|
[baff4da] | 448 | /** |
---|
| 449 | * @ingroup CPUContext Management |
---|
| 450 | * This defines the minimal set of integer and processor state registers |
---|
| 451 | * that must be saved during a voluntary context switch from one thread |
---|
| 452 | * to another. |
---|
| 453 | */ |
---|
[7908ba5b] | 454 | typedef struct { |
---|
[baff4da] | 455 | /** This field is a hint that a port will have a number of integer |
---|
| 456 | * registers that need to be saved at a context switch. |
---|
| 457 | */ |
---|
[c346f33d] | 458 | uint32_t some_integer_register; |
---|
[baff4da] | 459 | /** This field is a hint that a port will have a number of system |
---|
| 460 | * registers that need to be saved at a context switch. |
---|
| 461 | */ |
---|
[c346f33d] | 462 | uint32_t some_system_register; |
---|
[0ca6d0d9] | 463 | |
---|
| 464 | /** This field is a hint that a port will have a register that |
---|
| 465 | * is the stack pointer. |
---|
| 466 | */ |
---|
| 467 | uint32_t stack_pointer; |
---|
[7908ba5b] | 468 | } Context_Control; |
---|
| 469 | |
---|
[0ca6d0d9] | 470 | #define _CPU_Context_Get_SP( _context ) \ |
---|
| 471 | (_context)->stack_pointer |
---|
| 472 | |
---|
[baff4da] | 473 | /** |
---|
| 474 | * @ingroup CPUContext Management |
---|
| 475 | * This defines the complete set of floating point registers that must |
---|
| 476 | * be saved during any context switch from one thread to another. |
---|
| 477 | */ |
---|
[7908ba5b] | 478 | typedef struct { |
---|
[22b3bed] | 479 | /** FPU registers are listed here */ |
---|
[7908ba5b] | 480 | double some_float_register; |
---|
| 481 | } Context_Control_fp; |
---|
| 482 | |
---|
[baff4da] | 483 | /** |
---|
| 484 | * @ingroup CPUContext Management |
---|
| 485 | * This defines the set of integer and processor state registers that must |
---|
| 486 | * be saved during an interrupt. This set does not include any which are |
---|
| 487 | * in @ref Context_Control. |
---|
| 488 | */ |
---|
[7908ba5b] | 489 | typedef struct { |
---|
[baff4da] | 490 | /** This field is a hint that a port will have a number of integer |
---|
| 491 | * registers that need to be saved when an interrupt occurs or |
---|
| 492 | * when a context switch occurs at the end of an ISR. |
---|
| 493 | */ |
---|
[c346f33d] | 494 | uint32_t special_interrupt_register; |
---|
[7908ba5b] | 495 | } CPU_Interrupt_frame; |
---|
| 496 | |
---|
[baff4da] | 497 | /** |
---|
[7908ba5b] | 498 | * This variable is optional. It is used on CPUs on which it is difficult |
---|
| 499 | * to generate an "uninitialized" FP context. It is filled in by |
---|
[baff4da] | 500 | * @ref _CPU_Initialize and copied into the task's FP context area during |
---|
| 501 | * @ref _CPU_Context_Initialize. |
---|
[df49c60] | 502 | * |
---|
[baff4da] | 503 | * Port Specific Information: |
---|
[df49c60] | 504 | * |
---|
| 505 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 506 | */ |
---|
| 507 | SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; |
---|
| 508 | |
---|
[baff4da] | 509 | /** |
---|
| 510 | * @defgroup CPUInterrupt Processor Dependent Interrupt Management |
---|
| 511 | * |
---|
[7908ba5b] | 512 | * On some CPUs, RTEMS supports a software managed interrupt stack. |
---|
| 513 | * This stack is allocated by the Interrupt Manager and the switch |
---|
[baff4da] | 514 | * is performed in @ref _ISR_Handler. These variables contain pointers |
---|
[7908ba5b] | 515 | * to the lowest and highest addresses in the chunk of memory allocated |
---|
| 516 | * for the interrupt stack. Since it is unknown whether the stack |
---|
| 517 | * grows up or down (in general), this give the CPU dependent |
---|
| 518 | * code the option of picking the version it wants to use. |
---|
| 519 | * |
---|
[baff4da] | 520 | * @note These two variables are required if the macro |
---|
| 521 | * @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE. |
---|
[df49c60] | 522 | * |
---|
[baff4da] | 523 | * Port Specific Information: |
---|
[df49c60] | 524 | * |
---|
| 525 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 526 | */ |
---|
| 527 | |
---|
[baff4da] | 528 | /** |
---|
| 529 | * @ingroup CPUInterrupt |
---|
| 530 | * This variable points to the lowest physical address of the interrupt |
---|
| 531 | * stack. |
---|
| 532 | */ |
---|
[7908ba5b] | 533 | SCORE_EXTERN void *_CPU_Interrupt_stack_low; |
---|
[baff4da] | 534 | |
---|
| 535 | /** |
---|
| 536 | * @ingroup CPUInterrupt |
---|
| 537 | * This variable points to the lowest physical address of the interrupt |
---|
| 538 | * stack. |
---|
| 539 | */ |
---|
[7908ba5b] | 540 | SCORE_EXTERN void *_CPU_Interrupt_stack_high; |
---|
| 541 | |
---|
[baff4da] | 542 | /** |
---|
| 543 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 544 | * With some compilation systems, it is difficult if not impossible to |
---|
| 545 | * call a high-level language routine from assembly language. This |
---|
| 546 | * is especially true of commercial Ada compilers and name mangling |
---|
| 547 | * C++ ones. This variable can be optionally defined by the CPU porter |
---|
[baff4da] | 548 | * and contains the address of the routine @ref _Thread_Dispatch. This |
---|
[7908ba5b] | 549 | * can make it easier to invoke that routine at the end of the interrupt |
---|
| 550 | * sequence (if a dispatch is necessary). |
---|
[df49c60] | 551 | * |
---|
[baff4da] | 552 | * Port Specific Information: |
---|
[df49c60] | 553 | * |
---|
| 554 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 555 | */ |
---|
| 556 | SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); |
---|
| 557 | |
---|
| 558 | /* |
---|
| 559 | * Nothing prevents the porter from declaring more CPU specific variables. |
---|
[df49c60] | 560 | * |
---|
[baff4da] | 561 | * Port Specific Information: |
---|
[df49c60] | 562 | * |
---|
| 563 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 564 | */ |
---|
| 565 | |
---|
| 566 | /* XXX: if needed, put more variables here */ |
---|
| 567 | |
---|
[baff4da] | 568 | /** |
---|
| 569 | * @ingroup CPUContext |
---|
[7908ba5b] | 570 | * The size of the floating point context area. On some CPUs this |
---|
| 571 | * will not be a "sizeof" because the format of the floating point |
---|
| 572 | * area is not defined -- only the size is. This is usually on |
---|
| 573 | * CPUs with a "floating point save context" instruction. |
---|
[df49c60] | 574 | * |
---|
[baff4da] | 575 | * Port Specific Information: |
---|
[df49c60] | 576 | * |
---|
| 577 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 578 | */ |
---|
| 579 | #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) |
---|
| 580 | |
---|
[baff4da] | 581 | /** |
---|
[7908ba5b] | 582 | * Amount of extra stack (above minimum stack size) required by |
---|
| 583 | * MPCI receive server thread. Remember that in a multiprocessor |
---|
| 584 | * system this thread must exist and be able to process all directives. |
---|
[df49c60] | 585 | * |
---|
[baff4da] | 586 | * Port Specific Information: |
---|
[df49c60] | 587 | * |
---|
| 588 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 589 | */ |
---|
| 590 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
---|
| 591 | |
---|
[baff4da] | 592 | /** |
---|
| 593 | * @ingroup CPUInterrupt |
---|
| 594 | * This defines the number of entries in the @ref _ISR_Vector_table managed |
---|
[7908ba5b] | 595 | * by RTEMS. |
---|
[df49c60] | 596 | * |
---|
[baff4da] | 597 | * Port Specific Information: |
---|
[df49c60] | 598 | * |
---|
| 599 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 600 | */ |
---|
| 601 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
---|
[baff4da] | 602 | |
---|
| 603 | /** |
---|
| 604 | * @ingroup CPUInterrupt |
---|
| 605 | * This defines the highest interrupt vector number for this port. |
---|
| 606 | */ |
---|
[7908ba5b] | 607 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
---|
| 608 | |
---|
[baff4da] | 609 | /** |
---|
| 610 | * @ingroup CPUInterrupt |
---|
[4db30283] | 611 | * This is defined if the port has a special way to report the ISR nesting |
---|
[baff4da] | 612 | * level. Most ports maintain the variable @a _ISR_Nest_level. |
---|
[4db30283] | 613 | */ |
---|
| 614 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE |
---|
| 615 | |
---|
[baff4da] | 616 | /** |
---|
| 617 | * @ingroup CPUContext |
---|
| 618 | * Should be large enough to run all RTEMS tests. This ensures |
---|
[7908ba5b] | 619 | * that a "reasonable" small application should not have any problems. |
---|
[df49c60] | 620 | * |
---|
[baff4da] | 621 | * Port Specific Information: |
---|
[df49c60] | 622 | * |
---|
| 623 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 624 | */ |
---|
| 625 | #define CPU_STACK_MINIMUM_SIZE (1024*4) |
---|
| 626 | |
---|
[baff4da] | 627 | /** |
---|
[7908ba5b] | 628 | * CPU's worst alignment requirement for data types on a byte boundary. This |
---|
| 629 | * alignment does not take into account the requirements for the stack. |
---|
[df49c60] | 630 | * |
---|
[baff4da] | 631 | * Port Specific Information: |
---|
[df49c60] | 632 | * |
---|
| 633 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 634 | */ |
---|
| 635 | #define CPU_ALIGNMENT 8 |
---|
| 636 | |
---|
[baff4da] | 637 | /** |
---|
[7908ba5b] | 638 | * This number corresponds to the byte alignment requirement for the |
---|
| 639 | * heap handler. This alignment requirement may be stricter than that |
---|
[baff4da] | 640 | * for the data types alignment specified by @ref CPU_ALIGNMENT. It is |
---|
[7908ba5b] | 641 | * common for the heap to follow the same alignment requirement as |
---|
[baff4da] | 642 | * @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is strict enough for |
---|
| 643 | * the heap, then this should be set to @ref CPU_ALIGNMENT. |
---|
[7908ba5b] | 644 | * |
---|
[baff4da] | 645 | * @note This does not have to be a power of 2 although it should be |
---|
[df49c60] | 646 | * a multiple of 2 greater than or equal to 2. The requirement |
---|
| 647 | * to be a multiple of 2 is because the heap uses the least |
---|
| 648 | * significant field of the front and back flags to indicate |
---|
| 649 | * that a block is in use or free. So you do not want any odd |
---|
| 650 | * length blocks really putting length data in that bit. |
---|
| 651 | * |
---|
[baff4da] | 652 | * On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will |
---|
| 653 | * have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that |
---|
[df49c60] | 654 | * elements allocated from the heap meet all restrictions. |
---|
| 655 | * |
---|
[baff4da] | 656 | * Port Specific Information: |
---|
[df49c60] | 657 | * |
---|
| 658 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 659 | */ |
---|
| 660 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
---|
| 661 | |
---|
[baff4da] | 662 | /** |
---|
[7908ba5b] | 663 | * This number corresponds to the byte alignment requirement for memory |
---|
| 664 | * buffers allocated by the partition manager. This alignment requirement |
---|
| 665 | * may be stricter than that for the data types alignment specified by |
---|
[baff4da] | 666 | * @ref CPU_ALIGNMENT. It is common for the partition to follow the same |
---|
| 667 | * alignment requirement as @ref CPU_ALIGNMENT. If the @ref CPU_ALIGNMENT is |
---|
| 668 | * strict enough for the partition, then this should be set to |
---|
| 669 | * @ref CPU_ALIGNMENT. |
---|
[7908ba5b] | 670 | * |
---|
[baff4da] | 671 | * @note This does not have to be a power of 2. It does have to |
---|
| 672 | * be greater or equal to than @ref CPU_ALIGNMENT. |
---|
[df49c60] | 673 | * |
---|
[baff4da] | 674 | * Port Specific Information: |
---|
[df49c60] | 675 | * |
---|
| 676 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 677 | */ |
---|
| 678 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
---|
| 679 | |
---|
[baff4da] | 680 | /** |
---|
[7908ba5b] | 681 | * This number corresponds to the byte alignment requirement for the |
---|
| 682 | * stack. This alignment requirement may be stricter than that for the |
---|
[baff4da] | 683 | * data types alignment specified by @ref CPU_ALIGNMENT. If the |
---|
| 684 | * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be |
---|
| 685 | * set to 0. |
---|
[7908ba5b] | 686 | * |
---|
[baff4da] | 687 | * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT. |
---|
[df49c60] | 688 | * |
---|
[baff4da] | 689 | * Port Specific Information: |
---|
[df49c60] | 690 | * |
---|
| 691 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 692 | */ |
---|
| 693 | #define CPU_STACK_ALIGNMENT 0 |
---|
| 694 | |
---|
[d6ea098] | 695 | /* |
---|
| 696 | * ISR handler macros |
---|
| 697 | */ |
---|
| 698 | |
---|
[baff4da] | 699 | /** |
---|
| 700 | * @ingroup CPUInterrupt |
---|
[d6ea098] | 701 | * Support routine to initialize the RTEMS vector table after it is allocated. |
---|
| 702 | * |
---|
[baff4da] | 703 | * Port Specific Information: |
---|
[d6ea098] | 704 | * |
---|
| 705 | * XXX document implementation including references if appropriate |
---|
| 706 | */ |
---|
| 707 | #define _CPU_Initialize_vectors() |
---|
[7908ba5b] | 708 | |
---|
[baff4da] | 709 | /** |
---|
| 710 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 711 | * Disable all interrupts for an RTEMS critical section. The previous |
---|
[baff4da] | 712 | * level is returned in @a _isr_cookie. |
---|
| 713 | * |
---|
[22b3bed] | 714 | * @param[out] _isr_cookie will contain the previous level cookie |
---|
[df49c60] | 715 | * |
---|
[baff4da] | 716 | * Port Specific Information: |
---|
[df49c60] | 717 | * |
---|
| 718 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 719 | */ |
---|
| 720 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
---|
| 721 | { \ |
---|
| 722 | (_isr_cookie) = 0; /* do something to prevent warnings */ \ |
---|
| 723 | } |
---|
| 724 | |
---|
[baff4da] | 725 | /** |
---|
| 726 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 727 | * Enable interrupts to the previous level (returned by _CPU_ISR_Disable). |
---|
| 728 | * This indicates the end of an RTEMS critical section. The parameter |
---|
[baff4da] | 729 | * @a _isr_cookie is not modified. |
---|
| 730 | * |
---|
[22b3bed] | 731 | * @param[in] _isr_cookie contain the previous level cookie |
---|
[df49c60] | 732 | * |
---|
[baff4da] | 733 | * Port Specific Information: |
---|
[df49c60] | 734 | * |
---|
| 735 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 736 | */ |
---|
| 737 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
---|
| 738 | { \ |
---|
| 739 | } |
---|
| 740 | |
---|
[baff4da] | 741 | /** |
---|
| 742 | * @ingroup CPUInterrupt |
---|
| 743 | * This temporarily restores the interrupt to @a _isr_cookie before immediately |
---|
[7908ba5b] | 744 | * disabling them again. This is used to divide long RTEMS critical |
---|
[baff4da] | 745 | * sections into two or more parts. The parameter @a _isr_cookie is not |
---|
| 746 | * modified. |
---|
| 747 | * |
---|
[22b3bed] | 748 | * @param[in] _isr_cookie contain the previous level cookie |
---|
[df49c60] | 749 | * |
---|
[baff4da] | 750 | * Port Specific Information: |
---|
[df49c60] | 751 | * |
---|
| 752 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 753 | */ |
---|
| 754 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
---|
| 755 | { \ |
---|
| 756 | } |
---|
| 757 | |
---|
[baff4da] | 758 | /** |
---|
| 759 | * @ingroup CPUInterrupt |
---|
| 760 | * |
---|
| 761 | * This routine and @ref _CPU_ISR_Get_level |
---|
| 762 | * Map the interrupt level in task mode onto the hardware that the CPU |
---|
[7908ba5b] | 763 | * actually provides. Currently, interrupt levels which do not |
---|
| 764 | * map onto the CPU in a generic fashion are undefined. Someday, |
---|
| 765 | * it would be nice if these were "mapped" by the application |
---|
| 766 | * via a callout. For example, m68k has 8 levels 0 - 7, levels |
---|
| 767 | * 8 - 255 would be available for bsp/application specific meaning. |
---|
| 768 | * This could be used to manage a programmable interrupt controller |
---|
| 769 | * via the rtems_task_mode directive. |
---|
| 770 | * |
---|
[baff4da] | 771 | * Port Specific Information: |
---|
[df49c60] | 772 | * |
---|
| 773 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 774 | */ |
---|
| 775 | #define _CPU_ISR_Set_level( new_level ) \ |
---|
| 776 | { \ |
---|
| 777 | } |
---|
| 778 | |
---|
[baff4da] | 779 | /** |
---|
| 780 | * @ingroup CPUInterrupt |
---|
| 781 | * Return the current interrupt disable level for this task in |
---|
| 782 | * the format used by the interrupt level portion of the task mode. |
---|
| 783 | * |
---|
| 784 | * @note This routine usually must be implemented as a subroutine. |
---|
| 785 | * |
---|
| 786 | * Port Specific Information: |
---|
| 787 | * |
---|
| 788 | * XXX document implementation including references if appropriate |
---|
| 789 | */ |
---|
[c346f33d] | 790 | uint32_t _CPU_ISR_Get_level( void ); |
---|
[7908ba5b] | 791 | |
---|
| 792 | /* end of ISR handler macros */ |
---|
| 793 | |
---|
| 794 | /* Context handler macros */ |
---|
| 795 | |
---|
[baff4da] | 796 | /** |
---|
| 797 | * @ingroup CPUContext |
---|
[7908ba5b] | 798 | * Initialize the context to a state suitable for starting a |
---|
| 799 | * task after a context restore operation. Generally, this |
---|
| 800 | * involves: |
---|
| 801 | * |
---|
| 802 | * - setting a starting address |
---|
| 803 | * - preparing the stack |
---|
| 804 | * - preparing the stack and frame pointers |
---|
| 805 | * - setting the proper interrupt level in the context |
---|
| 806 | * - initializing the floating point context |
---|
| 807 | * |
---|
| 808 | * This routine generally does not set any unnecessary register |
---|
| 809 | * in the context. The state of the "general data" registers is |
---|
| 810 | * undefined at task start time. |
---|
| 811 | * |
---|
[22b3bed] | 812 | * @param[in] _the_context is the context structure to be initialized |
---|
| 813 | * @param[in] _stack_base is the lowest physical address of this task's stack |
---|
| 814 | * @param[in] _size is the size of this task's stack |
---|
| 815 | * @param[in] _isr is the interrupt disable level |
---|
| 816 | * @param[in] _entry_point is the thread's entry point. This is |
---|
[baff4da] | 817 | * always @a _Thread_Handler |
---|
[22b3bed] | 818 | * @param[in] _is_fp is TRUE if the thread is to be a floating |
---|
[7908ba5b] | 819 | * point thread. This is typically only used on CPUs where the |
---|
| 820 | * FPU may be easily disabled by software such as on the SPARC |
---|
| 821 | * where the PSR contains an enable FPU bit. |
---|
[df49c60] | 822 | * |
---|
[baff4da] | 823 | * Port Specific Information: |
---|
[df49c60] | 824 | * |
---|
| 825 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 826 | */ |
---|
| 827 | #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \ |
---|
| 828 | _isr, _entry_point, _is_fp ) \ |
---|
| 829 | { \ |
---|
| 830 | } |
---|
| 831 | |
---|
[22b3bed] | 832 | /** |
---|
[7908ba5b] | 833 | * This routine is responsible for somehow restarting the currently |
---|
| 834 | * executing task. If you are lucky, then all that is necessary |
---|
| 835 | * is restoring the context. Otherwise, there will need to be |
---|
| 836 | * a special assembly routine which does something special in this |
---|
[22b3bed] | 837 | * case. For many ports, simply adding a label to the restore path |
---|
| 838 | * of @ref _CPU_Context_switch will work. On other ports, it may be |
---|
| 839 | * possibly to load a few arguments and jump to the restore path. It will |
---|
[7908ba5b] | 840 | * not work if restarting self conflicts with the stack frame |
---|
| 841 | * assumptions of restoring a context. |
---|
[df49c60] | 842 | * |
---|
[baff4da] | 843 | * Port Specific Information: |
---|
[df49c60] | 844 | * |
---|
| 845 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 846 | */ |
---|
| 847 | #define _CPU_Context_Restart_self( _the_context ) \ |
---|
| 848 | _CPU_Context_restore( (_the_context) ); |
---|
| 849 | |
---|
[baff4da] | 850 | /** |
---|
| 851 | * @ingroup CPUContext |
---|
[7908ba5b] | 852 | * The purpose of this macro is to allow the initial pointer into |
---|
| 853 | * a floating point context area (used to save the floating point |
---|
| 854 | * context) to be at an arbitrary place in the floating point |
---|
| 855 | * context area. |
---|
| 856 | * |
---|
| 857 | * This is necessary because some FP units are designed to have |
---|
| 858 | * their context saved as a stack which grows into lower addresses. |
---|
| 859 | * Other FP units can be saved by simply moving registers into offsets |
---|
| 860 | * from the base of the context area. Finally some FP units provide |
---|
| 861 | * a "dump context" instruction which could fill in from high to low |
---|
| 862 | * or low to high based on the whim of the CPU designers. |
---|
[df49c60] | 863 | * |
---|
[22b3bed] | 864 | * @param[in] _base is the lowest physical address of the floating point |
---|
[baff4da] | 865 | * context area |
---|
[22b3bed] | 866 | * @param[in] _offset is the offset into the floating point area |
---|
[baff4da] | 867 | * |
---|
| 868 | * Port Specific Information: |
---|
[df49c60] | 869 | * |
---|
| 870 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 871 | */ |
---|
| 872 | #define _CPU_Context_Fp_start( _base, _offset ) \ |
---|
| 873 | ( (void *) _Addresses_Add_offset( (_base), (_offset) ) ) |
---|
| 874 | |
---|
[baff4da] | 875 | /** |
---|
[7908ba5b] | 876 | * This routine initializes the FP context area passed to it to. |
---|
| 877 | * There are a few standard ways in which to initialize the |
---|
| 878 | * floating point context. The code included for this macro assumes |
---|
| 879 | * that this is a CPU in which a "initial" FP context was saved into |
---|
[baff4da] | 880 | * @a _CPU_Null_fp_context and it simply copies it to the destination |
---|
[7908ba5b] | 881 | * context passed to it. |
---|
| 882 | * |
---|
[baff4da] | 883 | * Other floating point context save/restore models include: |
---|
| 884 | * -# not doing anything, and |
---|
| 885 | * -# putting a "null FP status word" in the correct place in the FP context. |
---|
[df49c60] | 886 | * |
---|
[22b3bed] | 887 | * @param[in] _destination is the floating point context area |
---|
[baff4da] | 888 | * |
---|
| 889 | * Port Specific Information: |
---|
[df49c60] | 890 | * |
---|
| 891 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 892 | */ |
---|
| 893 | #define _CPU_Context_Initialize_fp( _destination ) \ |
---|
| 894 | { \ |
---|
[b60dc893] | 895 | *(*(_destination)) = _CPU_Null_fp_context; \ |
---|
[7908ba5b] | 896 | } |
---|
| 897 | |
---|
| 898 | /* end of Context handler macros */ |
---|
| 899 | |
---|
| 900 | /* Fatal Error manager macros */ |
---|
| 901 | |
---|
[baff4da] | 902 | /** |
---|
[7908ba5b] | 903 | * This routine copies _error into a known place -- typically a stack |
---|
| 904 | * location or a register, optionally disables interrupts, and |
---|
| 905 | * halts/stops the CPU. |
---|
[df49c60] | 906 | * |
---|
[baff4da] | 907 | * Port Specific Information: |
---|
[df49c60] | 908 | * |
---|
| 909 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 910 | */ |
---|
| 911 | #define _CPU_Fatal_halt( _error ) \ |
---|
| 912 | { \ |
---|
| 913 | } |
---|
| 914 | |
---|
| 915 | /* end of Fatal Error manager macros */ |
---|
| 916 | |
---|
| 917 | /* Bitfield handler macros */ |
---|
| 918 | |
---|
[baff4da] | 919 | /** |
---|
| 920 | * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation |
---|
| 921 | * |
---|
| 922 | * This set of routines are used to implement fast searches for |
---|
| 923 | * the most important ready task. |
---|
| 924 | */ |
---|
| 925 | |
---|
| 926 | /** |
---|
| 927 | * @ingroup CPUBitfield |
---|
| 928 | * This definition is set to TRUE if the port uses the generic bitfield |
---|
| 929 | * manipulation implementation. |
---|
| 930 | */ |
---|
| 931 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
---|
| 932 | |
---|
| 933 | /** |
---|
| 934 | * @ingroup CPUBitfield |
---|
| 935 | * This definition is set to TRUE if the port uses the data tables provided |
---|
| 936 | * by the generic bitfield manipulation implementation. |
---|
| 937 | * This can occur when actually using the generic bitfield manipulation |
---|
| 938 | * implementation or when implementing the same algorithm in assembly |
---|
| 939 | * language for improved performance. It is unlikely that a port will use |
---|
| 940 | * the data if it has a bitfield scan instruction. |
---|
| 941 | */ |
---|
| 942 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
---|
| 943 | |
---|
| 944 | /** |
---|
| 945 | * @ingroup CPUBitfield |
---|
| 946 | * This routine sets @a _output to the bit number of the first bit |
---|
| 947 | * set in @a _value. @a _value is of CPU dependent type |
---|
| 948 | * @a Priority_Bit_map_control. This type may be either 16 or 32 bits |
---|
| 949 | * wide although only the 16 least significant bits will be used. |
---|
[7908ba5b] | 950 | * |
---|
| 951 | * There are a number of variables in using a "find first bit" type |
---|
| 952 | * instruction. |
---|
| 953 | * |
---|
[baff4da] | 954 | * -# What happens when run on a value of zero? |
---|
| 955 | * -# Bits may be numbered from MSB to LSB or vice-versa. |
---|
| 956 | * -# The numbering may be zero or one based. |
---|
| 957 | * -# The "find first bit" instruction may search from MSB or LSB. |
---|
[7908ba5b] | 958 | * |
---|
| 959 | * RTEMS guarantees that (1) will never happen so it is not a concern. |
---|
[baff4da] | 960 | * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and |
---|
| 961 | * @ref _CPU_Priority_bits_index. These three form a set of routines |
---|
[7908ba5b] | 962 | * which must logically operate together. Bits in the _value are |
---|
[baff4da] | 963 | * set and cleared based on masks built by @ref _CPU_Priority_Mask. |
---|
| 964 | * The basic major and minor values calculated by @ref _Priority_Major |
---|
| 965 | * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index |
---|
[7908ba5b] | 966 | * to properly range between the values returned by the "find first bit" |
---|
[baff4da] | 967 | * instruction. This makes it possible for @ref _Priority_Get_highest to |
---|
[7908ba5b] | 968 | * calculate the major and directly index into the minor table. |
---|
| 969 | * This mapping is necessary to ensure that 0 (a high priority major/minor) |
---|
| 970 | * is the first bit found. |
---|
| 971 | * |
---|
| 972 | * This entire "find first bit" and mapping process depends heavily |
---|
| 973 | * on the manner in which a priority is broken into a major and minor |
---|
| 974 | * components with the major being the 4 MSB of a priority and minor |
---|
| 975 | * the 4 LSB. Thus (0 << 4) + 0 corresponds to priority 0 -- the highest |
---|
| 976 | * priority. And (15 << 4) + 14 corresponds to priority 254 -- the next |
---|
| 977 | * to the lowest priority. |
---|
| 978 | * |
---|
| 979 | * If your CPU does not have a "find first bit" instruction, then |
---|
| 980 | * there are ways to make do without it. Here are a handful of ways |
---|
| 981 | * to implement this in software: |
---|
| 982 | * |
---|
[baff4da] | 983 | @verbatim |
---|
| 984 | - a series of 16 bit test instructions |
---|
| 985 | - a "binary search using if's" |
---|
| 986 | - _number = 0 |
---|
| 987 | if _value > 0x00ff |
---|
| 988 | _value >>=8 |
---|
| 989 | _number = 8; |
---|
| 990 | |
---|
| 991 | if _value > 0x0000f |
---|
| 992 | _value >=8 |
---|
| 993 | _number += 4 |
---|
| 994 | |
---|
| 995 | _number += bit_set_table[ _value ] |
---|
| 996 | @endverbatim |
---|
| 997 | |
---|
[7908ba5b] | 998 | * where bit_set_table[ 16 ] has values which indicate the first |
---|
| 999 | * bit set |
---|
[df49c60] | 1000 | * |
---|
[22b3bed] | 1001 | * @param[in] _value is the value to be scanned |
---|
| 1002 | * @param[in] _output is the first bit set |
---|
[baff4da] | 1003 | * |
---|
| 1004 | * Port Specific Information: |
---|
[df49c60] | 1005 | * |
---|
| 1006 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1007 | */ |
---|
| 1008 | |
---|
| 1009 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1010 | #define _CPU_Bitfield_Find_first_bit( _value, _output ) \ |
---|
| 1011 | { \ |
---|
| 1012 | (_output) = 0; /* do something to prevent warnings */ \ |
---|
| 1013 | } |
---|
| 1014 | #endif |
---|
| 1015 | |
---|
| 1016 | /* end of Bitfield handler macros */ |
---|
| 1017 | |
---|
[baff4da] | 1018 | /** |
---|
[7908ba5b] | 1019 | * This routine builds the mask which corresponds to the bit fields |
---|
[baff4da] | 1020 | * as searched by @ref _CPU_Bitfield_Find_first_bit. See the discussion |
---|
[7908ba5b] | 1021 | * for that routine. |
---|
[df49c60] | 1022 | * |
---|
[baff4da] | 1023 | * Port Specific Information: |
---|
[df49c60] | 1024 | * |
---|
| 1025 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1026 | */ |
---|
| 1027 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1028 | |
---|
| 1029 | #define _CPU_Priority_Mask( _bit_number ) \ |
---|
| 1030 | ( 1 << (_bit_number) ) |
---|
| 1031 | |
---|
| 1032 | #endif |
---|
| 1033 | |
---|
[baff4da] | 1034 | /** |
---|
| 1035 | * @ingroup CPUBitfield |
---|
[7908ba5b] | 1036 | * This routine translates the bit numbers returned by |
---|
[baff4da] | 1037 | * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as |
---|
[7908ba5b] | 1038 | * a major or minor component of a priority. See the discussion |
---|
| 1039 | * for that routine. |
---|
[df49c60] | 1040 | * |
---|
[22b3bed] | 1041 | * @param[in] _priority is the major or minor number to translate |
---|
[baff4da] | 1042 | * |
---|
| 1043 | * Port Specific Information: |
---|
[df49c60] | 1044 | * |
---|
| 1045 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1046 | */ |
---|
| 1047 | #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE) |
---|
| 1048 | |
---|
| 1049 | #define _CPU_Priority_bits_index( _priority ) \ |
---|
| 1050 | (_priority) |
---|
| 1051 | |
---|
| 1052 | #endif |
---|
| 1053 | |
---|
| 1054 | /* end of Priority handler macros */ |
---|
| 1055 | |
---|
| 1056 | /* functions */ |
---|
| 1057 | |
---|
[baff4da] | 1058 | /** |
---|
[7908ba5b] | 1059 | * This routine performs CPU dependent initialization. |
---|
[df49c60] | 1060 | * |
---|
[22b3bed] | 1061 | * @param[in] thread_dispatch is the address of @ref _Thread_Dispatch |
---|
[baff4da] | 1062 | * |
---|
| 1063 | * Port Specific Information: |
---|
[df49c60] | 1064 | * |
---|
| 1065 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1066 | */ |
---|
| 1067 | void _CPU_Initialize( |
---|
| 1068 | void (*thread_dispatch) |
---|
| 1069 | ); |
---|
| 1070 | |
---|
[baff4da] | 1071 | /** |
---|
| 1072 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 1073 | * This routine installs a "raw" interrupt handler directly into the |
---|
| 1074 | * processor's vector table. |
---|
[df49c60] | 1075 | * |
---|
[22b3bed] | 1076 | * @param[in] vector is the vector number |
---|
| 1077 | * @param[in] new_handler is the raw ISR handler to install |
---|
| 1078 | * @param[in] old_handler is the previously installed ISR Handler |
---|
[baff4da] | 1079 | * |
---|
| 1080 | * Port Specific Information: |
---|
[df49c60] | 1081 | * |
---|
| 1082 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1083 | */ |
---|
| 1084 | void _CPU_ISR_install_raw_handler( |
---|
[c346f33d] | 1085 | uint32_t vector, |
---|
[7908ba5b] | 1086 | proc_ptr new_handler, |
---|
| 1087 | proc_ptr *old_handler |
---|
| 1088 | ); |
---|
| 1089 | |
---|
[baff4da] | 1090 | /** |
---|
| 1091 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 1092 | * This routine installs an interrupt vector. |
---|
[df49c60] | 1093 | * |
---|
[22b3bed] | 1094 | * @param[in] vector is the vector number |
---|
| 1095 | * @param[in] new_handler is the RTEMS ISR handler to install |
---|
| 1096 | * @param[in] old_handler is the previously installed ISR Handler |
---|
[baff4da] | 1097 | * |
---|
| 1098 | * Port Specific Information: |
---|
[df49c60] | 1099 | * |
---|
| 1100 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1101 | */ |
---|
| 1102 | void _CPU_ISR_install_vector( |
---|
[c346f33d] | 1103 | uint32_t vector, |
---|
[7908ba5b] | 1104 | proc_ptr new_handler, |
---|
| 1105 | proc_ptr *old_handler |
---|
| 1106 | ); |
---|
| 1107 | |
---|
[baff4da] | 1108 | /** |
---|
| 1109 | * @ingroup CPUInterrupt |
---|
[7908ba5b] | 1110 | * This routine installs the hardware interrupt stack pointer. |
---|
| 1111 | * |
---|
[baff4da] | 1112 | * @note It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK |
---|
[7908ba5b] | 1113 | * is TRUE. |
---|
[df49c60] | 1114 | * |
---|
[baff4da] | 1115 | * Port Specific Information: |
---|
[df49c60] | 1116 | * |
---|
| 1117 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1118 | */ |
---|
| 1119 | void _CPU_Install_interrupt_stack( void ); |
---|
| 1120 | |
---|
[baff4da] | 1121 | /** |
---|
[7908ba5b] | 1122 | * This routine is the CPU dependent IDLE thread body. |
---|
| 1123 | * |
---|
[baff4da] | 1124 | * @note It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY |
---|
[7908ba5b] | 1125 | * is TRUE. |
---|
[df49c60] | 1126 | * |
---|
[baff4da] | 1127 | * Port Specific Information: |
---|
[df49c60] | 1128 | * |
---|
| 1129 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1130 | */ |
---|
| 1131 | void _CPU_Thread_Idle_body( void ); |
---|
| 1132 | |
---|
[baff4da] | 1133 | /** |
---|
| 1134 | * @ingroup CPUContext |
---|
[7908ba5b] | 1135 | * This routine switches from the run context to the heir context. |
---|
[df49c60] | 1136 | * |
---|
[22b3bed] | 1137 | * @param[in] run points to the context of the currently executing task |
---|
| 1138 | * @param[in] heir points to the context of the heir task |
---|
[baff4da] | 1139 | * |
---|
| 1140 | * Port Specific Information: |
---|
[df49c60] | 1141 | * |
---|
| 1142 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1143 | */ |
---|
| 1144 | void _CPU_Context_switch( |
---|
| 1145 | Context_Control *run, |
---|
| 1146 | Context_Control *heir |
---|
| 1147 | ); |
---|
| 1148 | |
---|
[baff4da] | 1149 | /** |
---|
| 1150 | * @ingroup CPUContext |
---|
[7908ba5b] | 1151 | * This routine is generally used only to restart self in an |
---|
[baff4da] | 1152 | * efficient manner. It may simply be a label in @ref _CPU_Context_switch. |
---|
[7908ba5b] | 1153 | * |
---|
[22b3bed] | 1154 | * @param[in] new_context points to the context to be restored. |
---|
[df49c60] | 1155 | * |
---|
[baff4da] | 1156 | * @note May be unnecessary to reload some registers. |
---|
| 1157 | * |
---|
| 1158 | * Port Specific Information: |
---|
[df49c60] | 1159 | * |
---|
| 1160 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1161 | */ |
---|
| 1162 | void _CPU_Context_restore( |
---|
| 1163 | Context_Control *new_context |
---|
| 1164 | ); |
---|
| 1165 | |
---|
[baff4da] | 1166 | /** |
---|
| 1167 | * @ingroup CPUContext |
---|
[7908ba5b] | 1168 | * This routine saves the floating point context passed to it. |
---|
[df49c60] | 1169 | * |
---|
[22b3bed] | 1170 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
[baff4da] | 1171 | * point context area |
---|
| 1172 | * |
---|
| 1173 | * @return on output @a *fp_context_ptr will contain the address that |
---|
| 1174 | * should be used with @ref _CPU_Context_restore_fp to restore this context. |
---|
| 1175 | * |
---|
| 1176 | * Port Specific Information: |
---|
[df49c60] | 1177 | * |
---|
| 1178 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1179 | */ |
---|
| 1180 | void _CPU_Context_save_fp( |
---|
[b60dc893] | 1181 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1182 | ); |
---|
| 1183 | |
---|
[baff4da] | 1184 | /** |
---|
| 1185 | * @ingroup CPUContext |
---|
[7908ba5b] | 1186 | * This routine restores the floating point context passed to it. |
---|
[df49c60] | 1187 | * |
---|
[22b3bed] | 1188 | * @param[in] fp_context_ptr is a pointer to a pointer to a floating |
---|
[baff4da] | 1189 | * point context area to restore |
---|
| 1190 | * |
---|
| 1191 | * @return on output @a *fp_context_ptr will contain the address that |
---|
| 1192 | * should be used with @ref _CPU_Context_save_fp to save this context. |
---|
| 1193 | * |
---|
| 1194 | * Port Specific Information: |
---|
[df49c60] | 1195 | * |
---|
| 1196 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1197 | */ |
---|
| 1198 | void _CPU_Context_restore_fp( |
---|
[b60dc893] | 1199 | Context_Control_fp **fp_context_ptr |
---|
[7908ba5b] | 1200 | ); |
---|
| 1201 | |
---|
[baff4da] | 1202 | /** |
---|
| 1203 | * @ingroup CPUEndian |
---|
| 1204 | * The following routine swaps the endian format of an unsigned int. |
---|
[7908ba5b] | 1205 | * It must be static because it is referenced indirectly. |
---|
| 1206 | * |
---|
| 1207 | * This version will work on any processor, but if there is a better |
---|
| 1208 | * way for your CPU PLEASE use it. The most common way to do this is to: |
---|
| 1209 | * |
---|
| 1210 | * swap least significant two bytes with 16-bit rotate |
---|
| 1211 | * swap upper and lower 16-bits |
---|
| 1212 | * swap most significant two bytes with 16-bit rotate |
---|
| 1213 | * |
---|
| 1214 | * Some CPUs have special instructions which swap a 32-bit quantity in |
---|
| 1215 | * a single instruction (e.g. i486). It is probably best to avoid |
---|
| 1216 | * an "endian swapping control bit" in the CPU. One good reason is |
---|
[22b3bed] | 1217 | * that interrupts would probably have to be disabled to ensure that |
---|
[7908ba5b] | 1218 | * an interrupt does not try to access the same "chunk" with the wrong |
---|
| 1219 | * endian. Another good reason is that on some CPUs, the endian bit |
---|
| 1220 | * endianness for ALL fetches -- both code and data -- so the code |
---|
| 1221 | * will be fetched incorrectly. |
---|
[df49c60] | 1222 | * |
---|
[22b3bed] | 1223 | * @param[in] value is the value to be swapped |
---|
[baff4da] | 1224 | * @return the value after being endian swapped |
---|
| 1225 | * |
---|
| 1226 | * Port Specific Information: |
---|
[df49c60] | 1227 | * |
---|
| 1228 | * XXX document implementation including references if appropriate |
---|
[7908ba5b] | 1229 | */ |
---|
[ec8973ed] | 1230 | static inline uint32_t CPU_swap_u32( |
---|
| 1231 | uint32_t value |
---|
[7908ba5b] | 1232 | ) |
---|
| 1233 | { |
---|
[5c5d438] | 1234 | uint32_t byte1, byte2, byte3, byte4, swapped; |
---|
[7908ba5b] | 1235 | |
---|
| 1236 | byte4 = (value >> 24) & 0xff; |
---|
| 1237 | byte3 = (value >> 16) & 0xff; |
---|
| 1238 | byte2 = (value >> 8) & 0xff; |
---|
| 1239 | byte1 = value & 0xff; |
---|
| 1240 | |
---|
| 1241 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
---|
[5c5d438] | 1242 | return swapped; |
---|
[7908ba5b] | 1243 | } |
---|
| 1244 | |
---|
[baff4da] | 1245 | /** |
---|
| 1246 | * @ingroup CPUEndian |
---|
| 1247 | * This routine swaps a 16 bir quantity. |
---|
| 1248 | * |
---|
[22b3bed] | 1249 | * @param[in] value is the value to be swapped |
---|
[baff4da] | 1250 | * @return the value after being endian swapped |
---|
| 1251 | */ |
---|
[7908ba5b] | 1252 | #define CPU_swap_u16( value ) \ |
---|
| 1253 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
---|
| 1254 | |
---|
| 1255 | #ifdef __cplusplus |
---|
| 1256 | } |
---|
| 1257 | #endif |
---|
| 1258 | |
---|
| 1259 | #endif |
---|