source: rtems/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h @ e88abc0

5
Last change on this file since e88abc0 was e88abc0, checked in by Joel Sherrill <joel@…>, on 03/08/18 at 23:10:38

no_cpu/include/rtems/score/types.h: Eliminate this file

Updates #3327.

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1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief NO_CPU Department Source
5 *
6 * This include file contains information pertaining to the NO_CPU
7 * processor.
8 */
9
10/*
11 *  This include file contains information pertaining to the XXX
12 *  processor.
13 *
14 *  @note This file is part of a porting template that is intended
15 *  to be used as the starting point when porting RTEMS to a new
16 *  CPU family.  The following needs to be done when using this as
17 *  the starting point for a new port:
18 *
19 *  + Anywhere there is an XXX, it should be replaced
20 *    with information about the CPU family being ported to.
21 *
22 *  + At the end of each comment section, there is a heading which
23 *    says "Port Specific Information:".  When porting to RTEMS,
24 *    add CPU family specific information in this section
25 */
26
27/*
28 *  COPYRIGHT (c) 1989-2008.
29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.org/license/LICENSE.
34 */
35
36#ifndef _RTEMS_SCORE_CPU_H
37#define _RTEMS_SCORE_CPU_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/basedefs.h>
44#include <rtems/score/no_cpu.h>
45
46/* conditional compilation parameters */
47
48/**
49 * Does RTEMS manage a dedicated interrupt stack in software?
50 *
51 * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
52 * If FALSE, nothing is done.
53 *
54 * If the CPU supports a dedicated interrupt stack in hardware,
55 * then it is generally the responsibility of the BSP to allocate it
56 * and set it up.
57 *
58 * If the CPU does not support a dedicated interrupt stack, then
59 * the porter has two options: (1) execute interrupts on the
60 * stack of the interrupted task, and (2) have RTEMS manage a dedicated
61 * interrupt stack.
62 *
63 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
64 *
65 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
66 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
67 * possible that both are FALSE for a particular CPU.  Although it
68 * is unclear what that would imply about the interrupt processing
69 * procedure on that CPU.
70 *
71 * Port Specific Information:
72 *
73 * XXX document implementation including references if appropriate
74 */
75#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
76
77/**
78 * Does the CPU follow the simple vectored interrupt model?
79 *
80 * If TRUE, then RTEMS allocates the vector table it internally manages.
81 * If FALSE, then the BSP is assumed to allocate and manage the vector
82 * table
83 *
84 * Port Specific Information:
85 *
86 * XXX document implementation including references if appropriate
87 */
88#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
89
90/**
91 * Does this CPU have hardware support for a dedicated interrupt stack?
92 *
93 * If TRUE, then it must be installed during initialization.
94 * If FALSE, then no installation is performed.
95 *
96 * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
97 *
98 * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
99 * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
100 * possible that both are FALSE for a particular CPU.  Although it
101 * is unclear what that would imply about the interrupt processing
102 * procedure on that CPU.
103 *
104 * Port Specific Information:
105 *
106 * XXX document implementation including references if appropriate
107 */
108#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
109
110/**
111 * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
112 *
113 * If TRUE, then the memory is allocated during initialization.
114 * If FALSE, then the memory is allocated during initialization.
115 *
116 * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
117 *
118 * Port Specific Information:
119 *
120 * XXX document implementation including references if appropriate
121 */
122#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
123
124/**
125 * Does the RTEMS invoke the user's ISR with the vector number and
126 * a pointer to the saved interrupt frame (1) or just the vector
127 * number (0)?
128 *
129 * Port Specific Information:
130 *
131 * XXX document implementation including references if appropriate
132 */
133#define CPU_ISR_PASSES_FRAME_POINTER FALSE
134
135/**
136 * @def CPU_HARDWARE_FP
137 *
138 * Does the CPU have hardware floating point?
139 *
140 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
141 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
142 *
143 * If there is a FP coprocessor such as the i387 or mc68881, then
144 * the answer is TRUE.
145 *
146 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
147 * It indicates whether or not this CPU model has FP support.  For
148 * example, it would be possible to have an i386_nofp CPU model
149 * which set this to false to indicate that you have an i386 without
150 * an i387 and wish to leave floating point support out of RTEMS.
151 */
152
153/**
154 * @def CPU_SOFTWARE_FP
155 *
156 * Does the CPU have no hardware floating point and GCC provides a
157 * software floating point implementation which must be context
158 * switched?
159 *
160 * This feature conditional is used to indicate whether or not there
161 * is software implemented floating point that must be context
162 * switched.  The determination of whether or not this applies
163 * is very tool specific and the state saved/restored is also
164 * compiler specific.
165 *
166 * Port Specific Information:
167 *
168 * XXX document implementation including references if appropriate
169 */
170#if ( NO_CPU_HAS_FPU == 1 )
171#define CPU_HARDWARE_FP     TRUE
172#else
173#define CPU_HARDWARE_FP     FALSE
174#endif
175#define CPU_SOFTWARE_FP     FALSE
176
177/**
178 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
179 *
180 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
181 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
182 *
183 * So far, the only CPUs in which this option has been used are the
184 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
185 * gcc both implicitly used the floating point registers to perform
186 * integer multiplies.  Similarly, the PowerPC port of gcc has been
187 * seen to allocate floating point local variables and touch the FPU
188 * even when the flow through a subroutine (like vfprintf()) might
189 * not use floating point formats.
190 *
191 * If a function which you would not think utilize the FP unit DOES,
192 * then one can not easily predict which tasks will use the FP hardware.
193 * In this case, this option should be TRUE.
194 *
195 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
196 *
197 * Port Specific Information:
198 *
199 * XXX document implementation including references if appropriate
200 */
201#define CPU_ALL_TASKS_ARE_FP     TRUE
202
203/**
204 * Should the IDLE task have a floating point context?
205 *
206 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
207 * and it has a floating point context which is switched in and out.
208 * If FALSE, then the IDLE task does not have a floating point context.
209 *
210 * Setting this to TRUE negatively impacts the time required to preempt
211 * the IDLE task from an interrupt because the floating point context
212 * must be saved as part of the preemption.
213 *
214 * Port Specific Information:
215 *
216 * XXX document implementation including references if appropriate
217 */
218#define CPU_IDLE_TASK_IS_FP      FALSE
219
220/**
221 * Should the saving of the floating point registers be deferred
222 * until a context switch is made to another different floating point
223 * task?
224 *
225 * If TRUE, then the floating point context will not be stored until
226 * necessary.  It will remain in the floating point registers and not
227 * disturned until another floating point task is switched to.
228 *
229 * If FALSE, then the floating point context is saved when a floating
230 * point task is switched out and restored when the next floating point
231 * task is restored.  The state of the floating point registers between
232 * those two operations is not specified.
233 *
234 * If the floating point context does NOT have to be saved as part of
235 * interrupt dispatching, then it should be safe to set this to TRUE.
236 *
237 * Setting this flag to TRUE results in using a different algorithm
238 * for deciding when to save and restore the floating point context.
239 * The deferred FP switch algorithm minimizes the number of times
240 * the FP context is saved and restored.  The FP context is not saved
241 * until a context switch is made to another, different FP task.
242 * Thus in a system with only one FP task, the FP context will never
243 * be saved or restored.
244 *
245 * Port Specific Information:
246 *
247 * XXX document implementation including references if appropriate
248 */
249#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
250
251/**
252 * @brief Enables a robust thread dispatch if set to TRUE.
253 *
254 * In general, it is an application bug to call blocking operating system
255 * services with interrupts disabled.  In most situations this only increases
256 * the interrupt latency.  However, on SMP configurations or on some CPU port
257 * like ARM Cortex-M it leads to undefined system behaviour.  It order to ease
258 * the application development, this error condition is checked at run-time in
259 * case this CPU port option is defined to TRUE.
260 */
261#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
262
263/**
264 * Does this port provide a CPU dependent IDLE task implementation?
265 *
266 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
267 * must be provided and is the default IDLE thread body instead of
268 * @ref _CPU_Thread_Idle_body.
269 *
270 * If FALSE, then use the generic IDLE thread body if the BSP does
271 * not provide one.
272 *
273 * This is intended to allow for supporting processors which have
274 * a low power or idle mode.  When the IDLE thread is executed, then
275 * the CPU can be powered down.
276 *
277 * The order of precedence for selecting the IDLE thread body is:
278 *
279 *   -#  BSP provided
280 *   -#  CPU dependent (if provided)
281 *   -#  generic (if no BSP and no CPU dependent)
282 *
283 * Port Specific Information:
284 *
285 * XXX document implementation including references if appropriate
286 */
287#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
288
289/**
290 * Does the stack grow up (toward higher addresses) or down
291 * (toward lower addresses)?
292 *
293 * If TRUE, then the grows upward.
294 * If FALSE, then the grows toward smaller addresses.
295 *
296 * Port Specific Information:
297 *
298 * XXX document implementation including references if appropriate
299 */
300#define CPU_STACK_GROWS_UP               TRUE
301
302/**
303 * The maximum cache line size in bytes.
304 *
305 * The actual processor may use no cache or a smaller cache line size.
306 */
307#define CPU_CACHE_LINE_BYTES 32
308
309/**
310 * The following is the variable attribute used to force alignment
311 * of critical RTEMS structures.  On some processors it may make
312 * sense to have these aligned on tighter boundaries than
313 * the minimum requirements of the compiler in order to have as
314 * much of the critical data area as possible in a cache line.
315 *
316 * Port Specific Information:
317 *
318 * XXX document implementation including references if appropriate
319 */
320#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
321
322/**
323 * @ingroup CPUInterrupt
324 *
325 * The following defines the number of bits actually used in the
326 * interrupt field of the task mode.  How those bits map to the
327 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
328 *
329 * Port Specific Information:
330 *
331 * XXX document implementation including references if appropriate
332 */
333#define CPU_MODES_INTERRUPT_MASK   0x00000001
334
335/**
336 * @brief Maximum number of processors of all systems supported by this CPU
337 * port.
338 */
339#define CPU_MAXIMUM_PROCESSORS 32
340
341/*
342 *  Processor defined structures required for cpukit/score.
343 *
344 *  Port Specific Information:
345 *
346 *  XXX document implementation including references if appropriate
347 */
348
349/* may need to put some structures here.  */
350
351/**
352 * @defgroup CPUContext Processor Dependent Context Management
353 *
354 * From the highest level viewpoint, there are 2 types of context to save.
355 *
356 *    -# Interrupt registers to save
357 *    -# Task level registers to save
358 *
359 * Since RTEMS handles integer and floating point contexts separately, this
360 * means we have the following 3 context items:
361 *
362 *    -# task level context stuff::  Context_Control
363 *    -# floating point task stuff:: Context_Control_fp
364 *    -# special interrupt level context :: CPU_Interrupt_frame
365 *
366 * On some processors, it is cost-effective to save only the callee
367 * preserved registers during a task context switch.  This means
368 * that the ISR code needs to save those registers which do not
369 * persist across function calls.  It is not mandatory to make this
370 * distinctions between the caller/callee saves registers for the
371 * purpose of minimizing context saved during task switch and on interrupts.
372 * If the cost of saving extra registers is minimal, simplicity is the
373 * choice.  Save the same context on interrupt entry as for tasks in
374 * this case.
375 *
376 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
377 * care should be used in designing the context area.
378 *
379 * On some CPUs with hardware floating point support, the Context_Control_fp
380 * structure will not be used or it simply consist of an array of a
381 * fixed number of bytes.   This is done when the floating point context
382 * is dumped by a "FP save context" type instruction and the format
383 * is not really defined by the CPU.  In this case, there is no need
384 * to figure out the exact format -- only the size.  Of course, although
385 * this is enough information for RTEMS, it is probably not enough for
386 * a debugger such as gdb.  But that is another problem.
387 *
388 * Port Specific Information:
389 *
390 * XXX document implementation including references if appropriate
391 *
392 */
393/**@{**/
394
395/**
396 * @ingroup Management
397 * This defines the minimal set of integer and processor state registers
398 * that must be saved during a voluntary context switch from one thread
399 * to another.
400 */
401typedef struct {
402    /**
403     * This field is a hint that a port will have a number of integer
404     * registers that need to be saved at a context switch.
405     */
406    uint32_t   some_integer_register;
407    /**
408     * This field is a hint that a port will have a number of system
409     * registers that need to be saved at a context switch.
410     */
411    uint32_t   some_system_register;
412
413    /**
414     * This field is a hint that a port will have a register that
415     * is the stack pointer.
416     */
417    uint32_t   stack_pointer;
418
419#ifdef RTEMS_SMP
420    /**
421     * @brief On SMP configurations the thread context must contain a boolean
422     * indicator to signal if this context is executing on a processor.
423     *
424     * This field must be updated during a context switch.  The context switch
425     * to the heir must wait until the heir context indicates that it is no
426     * longer executing on a processor.  This indicator must be updated using
427     * an atomic test and set operation to ensure that at most one processor
428     * uses the heir context at the same time.  The context switch must also
429     * check for a potential new heir thread for this processor in case the
430     * heir context is not immediately available.  Update the executing thread
431     * for this processor only if necessary to avoid a cache line
432     * monopolization.
433     *
434     * @code
435     * void _CPU_Context_switch(
436     *   Context_Control *executing_context,
437     *   Context_Control *heir_context
438     * )
439     * {
440     *   save( executing_context );
441     *
442     *   executing_context->is_executing = false;
443     *   memory_barrier();
444     *
445     *   if ( test_and_set( &heir_context->is_executing ) ) {
446     *     do {
447     *       Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot();
448     *       Thread_Control *executing = cpu_self->executing;
449     *       Thread_Control *heir = cpu_self->heir;
450     *
451     *       if ( heir != executing ) {
452     *         cpu_self->executing = heir;
453     *         heir_context = (Context_Control *)
454     *           ((uintptr_t) heir + (uintptr_t) executing_context
455     *             - (uintptr_t) executing)
456     *       }
457     *     } while ( test_and_set( &heir_context->is_executing ) );
458     *   }
459     *
460     *   restore( heir_context );
461     * }
462     * @endcode
463     */
464    volatile bool is_executing;
465#endif
466} Context_Control;
467
468/**
469 * @ingroup Management
470 *
471 * This macro returns the stack pointer associated with @a _context.
472 *
473 * @param[in] _context is the thread context area to access
474 *
475 * @return This method returns the stack pointer.
476 */
477#define _CPU_Context_Get_SP( _context ) \
478  (_context)->stack_pointer
479
480/**
481 * @ingroup Management
482 *
483 * This defines the complete set of floating point registers that must
484 * be saved during any context switch from one thread to another.
485 */
486typedef struct {
487    /** FPU registers are listed here */
488    double      some_float_register;
489} Context_Control_fp;
490
491/**
492 * @ingroup Management
493 *
494 * This defines the set of integer and processor state registers that must
495 * be saved during an interrupt.  This set does not include any which are
496 * in @ref Context_Control.
497 */
498typedef struct {
499    /**
500     * This field is a hint that a port will have a number of integer
501     * registers that need to be saved when an interrupt occurs or
502     * when a context switch occurs at the end of an ISR.
503     */
504    uint32_t   special_interrupt_register;
505} CPU_Interrupt_frame;
506
507/**
508 * This variable is optional.  It is used on CPUs on which it is difficult
509 * to generate an "uninitialized" FP context.  It is filled in by
510 * @ref _CPU_Initialize and copied into the task's FP context area during
511 * @ref _CPU_Context_Initialize.
512 *
513 * Port Specific Information:
514 *
515 * XXX document implementation including references if appropriate
516 */
517extern Context_Control_fp _CPU_Null_fp_context;
518
519/** @} */
520
521/**
522 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
523 *
524 * On some CPUs, RTEMS supports a software managed interrupt stack.
525 * This stack is allocated by the Interrupt Manager and the switch
526 * is performed in @ref _ISR_Handler.  These variables contain pointers
527 * to the lowest and highest addresses in the chunk of memory allocated
528 * for the interrupt stack.  Since it is unknown whether the stack
529 * grows up or down (in general), this give the CPU dependent
530 * code the option of picking the version it wants to use.
531 *
532 * NOTE: These two variables are required if the macro
533 *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
534 *
535 * Port Specific Information:
536 *
537 * XXX document implementation including references if appropriate
538 */
539
540/*
541 *  Nothing prevents the porter from declaring more CPU specific variables.
542 *
543 *  Port Specific Information:
544 *
545 *  XXX document implementation including references if appropriate
546 */
547
548/* XXX: if needed, put more variables here */
549
550/**
551 * @ingroup CPUContext
552 *
553 * The size of the floating point context area.  On some CPUs this
554 * will not be a "sizeof" because the format of the floating point
555 * area is not defined -- only the size is.  This is usually on
556 * CPUs with a "floating point save context" instruction.
557 *
558 * Port Specific Information:
559 *
560 * XXX document implementation including references if appropriate
561 */
562#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
563
564/**
565 * Amount of extra stack (above minimum stack size) required by
566 * MPCI receive server thread.  Remember that in a multiprocessor
567 * system this thread must exist and be able to process all directives.
568 *
569 * Port Specific Information:
570 *
571 * XXX document implementation including references if appropriate
572 */
573#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
574
575/**
576 * @ingroup CPUInterrupt
577 *
578 * This defines the number of entries in the _ISR_Vector_table managed by RTEMS
579 * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be a
580 * compile-time constant.
581 *
582 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
583 * FALSE.
584 */
585#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
586
587/**
588 * @ingroup CPUInterrupt
589 *
590 * This defines the highest interrupt vector number for this port in case
591 * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be less than
592 * CPU_INTERRUPT_NUMBER_OF_VECTORS.  It may be not a compile-time constant.
593 *
594 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
595 * FALSE.
596 */
597#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
598
599/**
600 * @ingroup CPUInterrupt
601 *
602 * This is defined if the port has a special way to report the ISR nesting
603 * level.  Most ports maintain the variable @a _ISR_Nest_level.
604 */
605#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
606
607/**
608 * @ingroup CPUContext
609 *
610 * Should be large enough to run all RTEMS tests.  This ensures
611 * that a "reasonable" small application should not have any problems.
612 *
613 * Port Specific Information:
614 *
615 * XXX document implementation including references if appropriate
616 */
617#define CPU_STACK_MINIMUM_SIZE          (1024*4)
618
619/**
620 * Size of a pointer.
621 *
622 * This must be an integer literal that can be used by the assembler.  This
623 * value will be used to calculate offsets of structure members.  These
624 * offsets will be used in assembler code.
625 */
626#define CPU_SIZEOF_POINTER         4
627
628/**
629 * CPU's worst alignment requirement for data types on a byte boundary.  This
630 * alignment does not take into account the requirements for the stack.  It
631 * must be a power of two greater than or equal to two.  The power of two
632 * requirement makes it possible to align values easily using simple bit
633 * operations.
634 *
635 * Port Specific Information:
636 *
637 * XXX document implementation including references if appropriate
638 */
639#define CPU_ALIGNMENT              8
640
641/**
642 * This number corresponds to the byte alignment requirement for the
643 * heap handler.  This alignment requirement may be stricter than that
644 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
645 * common for the heap to follow the same alignment requirement as
646 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
647 * the heap, then this should be set to @ref CPU_ALIGNMENT.
648 *
649 * NOTE:  It must be a power of two greater than or equal to two.  The
650 *        requirement to be a multiple of two is because the heap uses the
651 *        least significant field of the front and back flags to indicate that
652 *        a block is in use or free.  So you do not want any odd length blocks
653 *        really putting length data in that bit.
654 *
655 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
656 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
657 *        elements allocated from the heap meet all restrictions.
658 *
659 * Port Specific Information:
660 *
661 * XXX document implementation including references if appropriate
662 */
663#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
664
665/**
666 * This number corresponds to the byte alignment requirement for memory
667 * buffers allocated by the partition manager.  This alignment requirement
668 * may be stricter than that for the data types alignment specified by
669 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
670 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
671 * strict enough for the partition, then this should be set to
672 * @ref CPU_ALIGNMENT.
673 *
674 * NOTE:  This does not have to be a power of 2.  It does have to
675 *        be greater or equal to than @ref CPU_ALIGNMENT.
676 *
677 * Port Specific Information:
678 *
679 * XXX document implementation including references if appropriate
680 */
681#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
682
683/**
684 * This number corresponds to the byte alignment requirement for the
685 * stack.  This alignment requirement may be stricter than that for the
686 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
687 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
688 * set to 0.
689 *
690 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
691 *
692 * Port Specific Information:
693 *
694 * XXX document implementation including references if appropriate
695 */
696#define CPU_STACK_ALIGNMENT        0
697
698/*
699 *  ISR handler macros
700 */
701
702/**
703 * @ingroup CPUInterrupt
704 *
705 * Support routine to initialize the RTEMS vector table after it is allocated.
706 *
707 * Port Specific Information:
708 *
709 * XXX document implementation including references if appropriate
710 */
711#define _CPU_Initialize_vectors()
712
713/**
714 * @ingroup CPUInterrupt
715 *
716 * Disable all interrupts for an RTEMS critical section.  The previous
717 * level is returned in @a _isr_cookie.
718 *
719 * @param[out] _isr_cookie will contain the previous level cookie
720 *
721 * Port Specific Information:
722 *
723 * XXX document implementation including references if appropriate
724 */
725#define _CPU_ISR_Disable( _isr_cookie ) \
726  { \
727    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
728  }
729
730/**
731 * @ingroup CPUInterrupt
732 *
733 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
734 * This indicates the end of an RTEMS critical section.  The parameter
735 * @a _isr_cookie is not modified.
736 *
737 * @param[in] _isr_cookie contain the previous level cookie
738 *
739 * Port Specific Information:
740 *
741 * XXX document implementation including references if appropriate
742 */
743#define _CPU_ISR_Enable( _isr_cookie )  \
744  { \
745  }
746
747/**
748 * @ingroup CPUInterrupt
749 *
750 * This temporarily restores the interrupt to @a _isr_cookie before immediately
751 * disabling them again.  This is used to divide long RTEMS critical
752 * sections into two or more parts.  The parameter @a _isr_cookie is not
753 * modified.
754 *
755 * @param[in] _isr_cookie contain the previous level cookie
756 *
757 * Port Specific Information:
758 *
759 * XXX document implementation including references if appropriate
760 */
761#define _CPU_ISR_Flash( _isr_cookie ) \
762  { \
763  }
764
765/**
766 * @brief Returns true if interrupts are enabled in the specified ISR level,
767 * otherwise returns false.
768 *
769 * @param[in] level The ISR level.
770 *
771 * @retval true Interrupts are enabled in the ISR level.
772 * @retval false Otherwise.
773 */
774RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
775{
776  return false;
777}
778
779/**
780 * @ingroup CPUInterrupt
781 *
782 * This routine and @ref _CPU_ISR_Get_level
783 * Map the interrupt level in task mode onto the hardware that the CPU
784 * actually provides.  Currently, interrupt levels which do not
785 * map onto the CPU in a generic fashion are undefined.  Someday,
786 * it would be nice if these were "mapped" by the application
787 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
788 * 8 - 255 would be available for bsp/application specific meaning.
789 * This could be used to manage a programmable interrupt controller
790 * via the rtems_task_mode directive.
791 *
792 * Port Specific Information:
793 *
794 * XXX document implementation including references if appropriate
795 */
796#define _CPU_ISR_Set_level( new_level ) \
797  { \
798  }
799
800/**
801 * @ingroup CPUInterrupt
802 *
803 * Return the current interrupt disable level for this task in
804 * the format used by the interrupt level portion of the task mode.
805 *
806 * NOTE: This routine usually must be implemented as a subroutine.
807 *
808 * Port Specific Information:
809 *
810 * XXX document implementation including references if appropriate
811 */
812uint32_t   _CPU_ISR_Get_level( void );
813
814/* end of ISR handler macros */
815
816/* Context handler macros */
817
818/**
819 * @ingroup CPUContext
820 *
821 * @brief Destroys the context of the thread.
822 *
823 * It must be implemented as a macro and an implementation is optional.  The
824 * default implementation does nothing.
825 *
826 * @param[in] _the_thread The corresponding thread.
827 * @param[in] _the_context The context to destroy.
828 *
829 * Port Specific Information:
830 *
831 * XXX document implementation including references if appropriate
832 */
833#define _CPU_Context_Destroy( _the_thread, _the_context ) \
834  { \
835  }
836
837/**
838 *  @ingroup CPUContext
839 *
840 * Initialize the context to a state suitable for starting a
841 * task after a context restore operation.  Generally, this
842 * involves:
843 *
844 *    - setting a starting address
845 *    - preparing the stack
846 *    - preparing the stack and frame pointers
847 *    - setting the proper interrupt level in the context
848 *    - initializing the floating point context
849 *
850 * This routine generally does not set any unnecessary register
851 * in the context.  The state of the "general data" registers is
852 * undefined at task start time.
853 *
854 * The ISR dispatch disable field of the context must be cleared to zero if it
855 * is used by the CPU port.  Otherwise, a thread restart results in
856 * unpredictable behaviour.
857 *
858 * @param[in] _the_context is the context structure to be initialized
859 * @param[in] _stack_base is the lowest physical address of this task's stack
860 * @param[in] _size is the size of this task's stack
861 * @param[in] _isr is the interrupt disable level
862 * @param[in] _entry_point is the thread's entry point.  This is
863 *        always @a _Thread_Handler
864 * @param[in] _is_fp is TRUE if the thread is to be a floating
865 *       point thread.  This is typically only used on CPUs where the
866 *       FPU may be easily disabled by software such as on the SPARC
867 *       where the PSR contains an enable FPU bit.
868 * @param[in] _tls_area The thread-local storage (TLS) area.
869 *
870 * Port Specific Information:
871 *
872 * XXX document implementation including references if appropriate
873 */
874#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
875                                 _isr, _entry_point, _is_fp, _tls_area ) \
876  { \
877  }
878
879/**
880 * This routine is responsible for somehow restarting the currently
881 * executing task.  If you are lucky, then all that is necessary
882 * is restoring the context.  Otherwise, there will need to be
883 * a special assembly routine which does something special in this
884 * case.  For many ports, simply adding a label to the restore path
885 * of @ref _CPU_Context_switch will work.  On other ports, it may be
886 * possibly to load a few arguments and jump to the restore path. It will
887 * not work if restarting self conflicts with the stack frame
888 * assumptions of restoring a context.
889 *
890 * Port Specific Information:
891 *
892 * XXX document implementation including references if appropriate
893 */
894#define _CPU_Context_Restart_self( _the_context ) \
895   _CPU_Context_restore( (_the_context) );
896
897/**
898 * This routine initializes the FP context area passed to it to.
899 * There are a few standard ways in which to initialize the
900 * floating point context.  The code included for this macro assumes
901 * that this is a CPU in which a "initial" FP context was saved into
902 * @a _CPU_Null_fp_context and it simply copies it to the destination
903 * context passed to it.
904 *
905 * Other floating point context save/restore models include:
906 *   -# not doing anything, and
907 *   -# putting a "null FP status word" in the correct place in the FP context.
908 *
909 * @param[in] _destination is the floating point context area
910 *
911 * Port Specific Information:
912 *
913 * XXX document implementation including references if appropriate
914 */
915#define _CPU_Context_Initialize_fp( _destination ) \
916  { \
917   *(*(_destination)) = _CPU_Null_fp_context; \
918  }
919
920/* end of Context handler macros */
921
922/* Fatal Error manager macros */
923
924/**
925 * This routine copies _error into a known place -- typically a stack
926 * location or a register, optionally disables interrupts, and
927 * halts/stops the CPU.
928 *
929 * Port Specific Information:
930 *
931 * XXX document implementation including references if appropriate
932 */
933#define _CPU_Fatal_halt( _source, _error ) \
934  { \
935  }
936
937/* end of Fatal Error manager macros */
938
939/* Bitfield handler macros */
940
941/**
942 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
943 *
944 * This set of routines are used to implement fast searches for
945 * the most important ready task.
946 *
947 */
948/**@{**/
949
950/**
951 * This definition is set to TRUE if the port uses the generic bitfield
952 * manipulation implementation.
953 */
954#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
955
956/**
957 * This routine sets @a _output to the bit number of the first bit
958 * set in @a _value.  @a _value is of CPU dependent type
959 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
960 * wide although only the 16 least significant bits will be used.
961 *
962 * There are a number of variables in using a "find first bit" type
963 * instruction.
964 *
965 *   -# What happens when run on a value of zero?
966 *   -# Bits may be numbered from MSB to LSB or vice-versa.
967 *   -# The numbering may be zero or one based.
968 *   -# The "find first bit" instruction may search from MSB or LSB.
969 *
970 * RTEMS guarantees that (1) will never happen so it is not a concern.
971 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
972 * @ref _CPU_Priority_bits_index.  These three form a set of routines
973 * which must logically operate together.  Bits in the _value are
974 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
975 * The basic major and minor values calculated by @ref _Priority_Major
976 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
977 * to properly range between the values returned by the "find first bit"
978 * instruction.  This makes it possible for @ref _Priority_Get_highest to
979 * calculate the major and directly index into the minor table.
980 * This mapping is necessary to ensure that 0 (a high priority major/minor)
981 * is the first bit found.
982 *
983 * This entire "find first bit" and mapping process depends heavily
984 * on the manner in which a priority is broken into a major and minor
985 * components with the major being the 4 MSB of a priority and minor
986 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
987 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
988 * to the lowest priority.
989 *
990 * If your CPU does not have a "find first bit" instruction, then
991 * there are ways to make do without it.  Here are a handful of ways
992 * to implement this in software:
993 *
994@verbatim
995      - a series of 16 bit test instructions
996      - a "binary search using if's"
997      - _number = 0
998        if _value > 0x00ff
999          _value >>=8
1000          _number = 8;
1001
1002        if _value > 0x0000f
1003          _value >=8
1004          _number += 4
1005
1006        _number += bit_set_table[ _value ]
1007@endverbatim
1008
1009 *   where bit_set_table[ 16 ] has values which indicate the first
1010 *     bit set
1011 *
1012 * @param[in] _value is the value to be scanned
1013 * @param[in] _output is the first bit set
1014 *
1015 * Port Specific Information:
1016 *
1017 * XXX document implementation including references if appropriate
1018 */
1019
1020#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1021#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1022  { \
1023    (_output) = 0;   /* do something to prevent warnings */ \
1024  }
1025#endif
1026
1027/** @} */
1028
1029/* end of Bitfield handler macros */
1030
1031/**
1032 * This routine builds the mask which corresponds to the bit fields
1033 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1034 * for that routine.
1035 *
1036 * Port Specific Information:
1037 *
1038 * XXX document implementation including references if appropriate
1039 */
1040#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1041
1042#define _CPU_Priority_Mask( _bit_number ) \
1043  ( 1 << (_bit_number) )
1044
1045#endif
1046
1047/**
1048 * @ingroup CPUBitfield
1049 *
1050 * This routine translates the bit numbers returned by
1051 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1052 * a major or minor component of a priority.  See the discussion
1053 * for that routine.
1054 *
1055 * @param[in] _priority is the major or minor number to translate
1056 *
1057 * Port Specific Information:
1058 *
1059 * XXX document implementation including references if appropriate
1060 */
1061#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1062
1063#define _CPU_Priority_bits_index( _priority ) \
1064  (_priority)
1065
1066#endif
1067
1068/* end of Priority handler macros */
1069
1070/* functions */
1071
1072/**
1073 * This routine performs CPU dependent initialization.
1074 *
1075 * Port Specific Information:
1076 *
1077 * XXX document implementation including references if appropriate
1078 */
1079void _CPU_Initialize(void);
1080
1081/**
1082 * @ingroup CPUInterrupt
1083 *
1084 * This routine installs a "raw" interrupt handler directly into the
1085 * processor's vector table.
1086 *
1087 * @param[in] vector is the vector number
1088 * @param[in] new_handler is the raw ISR handler to install
1089 * @param[in] old_handler is the previously installed ISR Handler
1090 *
1091 * Port Specific Information:
1092 *
1093 * XXX document implementation including references if appropriate
1094 */
1095void _CPU_ISR_install_raw_handler(
1096  uint32_t    vector,
1097  proc_ptr    new_handler,
1098  proc_ptr   *old_handler
1099);
1100
1101/**
1102 * @ingroup CPUInterrupt
1103 *
1104 * This routine installs an interrupt vector.
1105 *
1106 * @param[in] vector is the vector number
1107 * @param[in] new_handler is the RTEMS ISR handler to install
1108 * @param[in] old_handler is the previously installed ISR Handler
1109 *
1110 * Port Specific Information:
1111 *
1112 * XXX document implementation including references if appropriate
1113 */
1114void _CPU_ISR_install_vector(
1115  uint32_t    vector,
1116  proc_ptr    new_handler,
1117  proc_ptr   *old_handler
1118);
1119
1120/**
1121 * @ingroup CPUInterrupt
1122 * This routine installs the hardware interrupt stack pointer.
1123 *
1124 * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1125 *        is TRUE.
1126 *
1127 * Port Specific Information:
1128 *
1129 * XXX document implementation including references if appropriate
1130 */
1131void _CPU_Install_interrupt_stack( void );
1132
1133/**
1134 * This routine is the CPU dependent IDLE thread body.
1135 *
1136 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1137 *         is TRUE.
1138 *
1139 * Port Specific Information:
1140 *
1141 * XXX document implementation including references if appropriate
1142 */
1143void *_CPU_Thread_Idle_body( uintptr_t ignored );
1144
1145/**
1146 * @ingroup CPUContext
1147 *
1148 * This routine switches from the run context to the heir context.
1149 *
1150 * @param[in] run points to the context of the currently executing task
1151 * @param[in] heir points to the context of the heir task
1152 *
1153 * Port Specific Information:
1154 *
1155 * XXX document implementation including references if appropriate
1156 */
1157void _CPU_Context_switch(
1158  Context_Control  *run,
1159  Context_Control  *heir
1160);
1161
1162/**
1163 * @ingroup CPUContext
1164 *
1165 * This routine is generally used only to restart self in an
1166 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1167 *
1168 * @param[in] new_context points to the context to be restored.
1169 *
1170 * NOTE: May be unnecessary to reload some registers.
1171 *
1172 * Port Specific Information:
1173 *
1174 * XXX document implementation including references if appropriate
1175 */
1176void _CPU_Context_restore(
1177  Context_Control *new_context
1178) RTEMS_NO_RETURN;
1179
1180/**
1181 * @ingroup CPUContext
1182 *
1183 * This routine saves the floating point context passed to it.
1184 *
1185 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1186 * point context area
1187 *
1188 * @return on output @a *fp_context_ptr will contain the address that
1189 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1190 *
1191 * Port Specific Information:
1192 *
1193 * XXX document implementation including references if appropriate
1194 */
1195void _CPU_Context_save_fp(
1196  Context_Control_fp **fp_context_ptr
1197);
1198
1199/**
1200 * @ingroup CPUContext
1201 *
1202 * This routine restores the floating point context passed to it.
1203 *
1204 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1205 * point context area to restore
1206 *
1207 * @return on output @a *fp_context_ptr will contain the address that
1208 * should be used with @ref _CPU_Context_save_fp to save this context.
1209 *
1210 * Port Specific Information:
1211 *
1212 * XXX document implementation including references if appropriate
1213 */
1214void _CPU_Context_restore_fp(
1215  Context_Control_fp **fp_context_ptr
1216);
1217
1218/**
1219 * @ingroup CPUContext
1220 *
1221 * @brief Clobbers all volatile registers with values derived from the pattern
1222 * parameter.
1223 *
1224 * This function is used only in test sptests/spcontext01.
1225 *
1226 * @param[in] pattern Pattern used to generate distinct register values.
1227 *
1228 * @see _CPU_Context_validate().
1229 */
1230void _CPU_Context_volatile_clobber( uintptr_t pattern );
1231
1232/**
1233 * @ingroup CPUContext
1234 *
1235 * @brief Initializes and validates the CPU context with values derived from
1236 * the pattern parameter.
1237 *
1238 * This function will not return if the CPU context remains consistent.  In
1239 * case this function returns the CPU port is broken.
1240 *
1241 * This function is used only in test sptests/spcontext01.
1242 *
1243 * @param[in] pattern Pattern used to generate distinct register values.
1244 *
1245 * @see _CPU_Context_volatile_clobber().
1246 */
1247void _CPU_Context_validate( uintptr_t pattern );
1248
1249/**
1250 * @brief The set of registers that specifies the complete processor state.
1251 *
1252 * The CPU exception frame may be available in fatal error conditions like for
1253 * example illegal opcodes, instruction fetch errors, or data access errors.
1254 *
1255 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1256 * rtems_exception_frame_print().
1257 */
1258typedef struct {
1259  uint32_t processor_state_register;
1260  uint32_t integer_registers [1];
1261  double float_registers [1];
1262} CPU_Exception_frame;
1263
1264/**
1265 * @brief Prints the exception frame via printk().
1266 *
1267 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1268 */
1269void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1270
1271/**
1272 * @ingroup CPUEndian
1273 *
1274 * The following routine swaps the endian format of an unsigned int.
1275 * It must be static because it is referenced indirectly.
1276 *
1277 * This version will work on any processor, but if there is a better
1278 * way for your CPU PLEASE use it.  The most common way to do this is to:
1279 *
1280 *    swap least significant two bytes with 16-bit rotate
1281 *    swap upper and lower 16-bits
1282 *    swap most significant two bytes with 16-bit rotate
1283 *
1284 * Some CPUs have special instructions which swap a 32-bit quantity in
1285 * a single instruction (e.g. i486).  It is probably best to avoid
1286 * an "endian swapping control bit" in the CPU.  One good reason is
1287 * that interrupts would probably have to be disabled to ensure that
1288 * an interrupt does not try to access the same "chunk" with the wrong
1289 * endian.  Another good reason is that on some CPUs, the endian bit
1290 * endianness for ALL fetches -- both code and data -- so the code
1291 * will be fetched incorrectly.
1292 *
1293 * @param[in] value is the value to be swapped
1294 * @return the value after being endian swapped
1295 *
1296 * Port Specific Information:
1297 *
1298 * XXX document implementation including references if appropriate
1299 */
1300static inline uint32_t CPU_swap_u32(
1301  uint32_t value
1302)
1303{
1304  uint32_t byte1, byte2, byte3, byte4, swapped;
1305
1306  byte4 = (value >> 24) & 0xff;
1307  byte3 = (value >> 16) & 0xff;
1308  byte2 = (value >> 8)  & 0xff;
1309  byte1 =  value        & 0xff;
1310
1311  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1312  return swapped;
1313}
1314
1315/**
1316 * @ingroup CPUEndian
1317 *
1318 * This routine swaps a 16 bir quantity.
1319 *
1320 * @param[in] value is the value to be swapped
1321 * @return the value after being endian swapped
1322 */
1323#define CPU_swap_u16( value ) \
1324  (((value&0xff) << 8) | ((value >> 8)&0xff))
1325
1326/**
1327 * @brief Unsigned integer type for CPU counter values.
1328 */
1329typedef uint32_t CPU_Counter_ticks;
1330
1331/**
1332 * @brief Returns the current CPU counter value.
1333 *
1334 * A CPU counter is some free-running counter.  It ticks usually with a
1335 * frequency close to the CPU or system bus clock.  The board support package
1336 * must ensure that this function works before the RTEMS initialization.
1337 * Otherwise invalid profiling statistics will be gathered.
1338 *
1339 * @return The current CPU counter value.
1340 */
1341CPU_Counter_ticks _CPU_Counter_read( void );
1342
1343/**
1344 * @brief Returns the difference between the second and first CPU counter
1345 * value.
1346 *
1347 * This operation may be carried out as a modulo operation depending on the
1348 * range of the CPU counter device.
1349 *
1350 * @param[in] second The second CPU counter value.
1351 * @param[in] first The first CPU counter value.
1352 *
1353 * @return Returns second minus first modulo counter period.
1354 */
1355CPU_Counter_ticks _CPU_Counter_difference(
1356  CPU_Counter_ticks second,
1357  CPU_Counter_ticks first
1358);
1359
1360#ifdef RTEMS_SMP
1361  /**
1362   * @brief Performs CPU specific SMP initialization in the context of the boot
1363   * processor.
1364   *
1365   * This function is invoked on the boot processor during system
1366   * initialization.  All interrupt stacks are allocated at this point in case
1367   * the CPU port allocates the interrupt stacks.  This function is called
1368   * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
1369   * used.
1370   *
1371   * @return The count of physically or virtually available processors.
1372   * Depending on the configuration the application may use not all processors.
1373   */
1374  uint32_t _CPU_SMP_Initialize( void );
1375
1376  /**
1377   * @brief Starts a processor specified by its index.
1378   *
1379   * This function is invoked on the boot processor during system
1380   * initialization.
1381   *
1382   * This function will be called after _CPU_SMP_Initialize().
1383   *
1384   * @param[in] cpu_index The processor index.
1385   *
1386   * @retval true Successful operation.
1387   * @retval false Unable to start this processor.
1388   */
1389  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1390
1391  /**
1392   * @brief Performs final steps of CPU specific SMP initialization in the
1393   * context of the boot processor.
1394   *
1395   * This function is invoked on the boot processor during system
1396   * initialization.
1397   *
1398   * This function will be called after all processors requested by the
1399   * application have been started.
1400   *
1401   * @param[in] cpu_count The minimum value of the count of processors
1402   * requested by the application configuration and the count of physically or
1403   * virtually available processors.
1404   */
1405  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1406
1407  /**
1408   * @brief Prepares a CPU to start multitasking in terms of SMP.
1409   *
1410   * This function is invoked on all processors requested by the application
1411   * during system initialization.
1412   *
1413   * This function will be called after all processors requested by the
1414   * application have been started right before the context switch to the first
1415   * thread takes place.
1416   */
1417  void _CPU_SMP_Prepare_start_multitasking( void );
1418
1419  /**
1420   * @brief Returns the index of the current processor.
1421   *
1422   * An architecture specific method must be used to obtain the index of the
1423   * current processor in the system.  The set of processor indices is the
1424   * range of integers starting with zero up to the processor count minus one.
1425   */
1426  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1427  {
1428    return 123;
1429  }
1430
1431  /**
1432   * @brief Sends an inter-processor interrupt to the specified target
1433   * processor.
1434   *
1435   * This operation is undefined for target processor indices out of range.
1436   *
1437   * @param[in] target_processor_index The target processor index.
1438   */
1439  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1440
1441  /**
1442   * @brief Broadcasts a processor event.
1443   *
1444   * Some architectures provide a low-level synchronization primitive for
1445   * processors in a multi-processor environment.  Processors waiting for this
1446   * event may go into a low-power state and stop generating system bus
1447   * transactions.  This function must ensure that preceding store operations
1448   * can be observed by other processors.
1449   *
1450   * @see _CPU_SMP_Processor_event_receive().
1451   */
1452  static inline void _CPU_SMP_Processor_event_broadcast( void )
1453  {
1454    __asm__ volatile ( "" : : : "memory" );
1455  }
1456
1457  /**
1458   * @brief Receives a processor event.
1459   *
1460   * This function will wait for the processor event and may wait forever if no
1461   * such event arrives.
1462   *
1463   * @see _CPU_SMP_Processor_event_broadcast().
1464   */
1465  static inline void _CPU_SMP_Processor_event_receive( void )
1466  {
1467    __asm__ volatile ( "" : : : "memory" );
1468  }
1469
1470  /**
1471   * @brief Gets the is executing indicator of the thread context.
1472   *
1473   * @param[in] context The context.
1474   */
1475  static inline bool _CPU_Context_Get_is_executing(
1476    const Context_Control *context
1477  )
1478  {
1479    return context->is_executing;
1480  }
1481
1482  /**
1483   * @brief Sets the is executing indicator of the thread context.
1484   *
1485   * @param[in] context The context.
1486   * @param[in] is_executing The new value for the is executing indicator.
1487   */
1488  static inline void _CPU_Context_Set_is_executing(
1489    Context_Control *context,
1490    bool is_executing
1491  )
1492  {
1493    context->is_executing = is_executing;
1494  }
1495
1496/** Type that can store a 32-bit integer or a pointer. */
1497typedef uintptr_t CPU_Uint32ptr;
1498
1499#endif
1500
1501#ifdef __cplusplus
1502}
1503#endif
1504
1505#endif
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