source: rtems/cpukit/score/cpu/no_cpu/include/rtems/score/cpu.h @ 42f2fdfd

5
Last change on this file since 42f2fdfd was 42f2fdfd, checked in by Sebastian Huber <sebastian.huber@…>, on 07/20/18 at 05:56:43

score: Move context validation declarations

The context validation support functions _CPU_Context_validate() and
_CPU_Context_volatile_clobber() are used only by one test program
(spcontext01). Move the function declarations to the CPU port
implementation header file.

  • Property mode set to 100644
File size: 43.7 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 *
4 * @brief NO_CPU Department Source
5 *
6 * This include file contains information pertaining to the NO_CPU
7 * processor.
8 */
9
10/*
11 *  This include file contains information pertaining to the XXX
12 *  processor.
13 *
14 *  @note This file is part of a porting template that is intended
15 *  to be used as the starting point when porting RTEMS to a new
16 *  CPU family.  The following needs to be done when using this as
17 *  the starting point for a new port:
18 *
19 *  + Anywhere there is an XXX, it should be replaced
20 *    with information about the CPU family being ported to.
21 *
22 *  + At the end of each comment section, there is a heading which
23 *    says "Port Specific Information:".  When porting to RTEMS,
24 *    add CPU family specific information in this section
25 */
26
27/*
28 *  COPYRIGHT (c) 1989-2008.
29 *  On-Line Applications Research Corporation (OAR).
30 *
31 *  The license and distribution terms for this file may be
32 *  found in the file LICENSE in this distribution or at
33 *  http://www.rtems.org/license/LICENSE.
34 */
35
36#ifndef _RTEMS_SCORE_CPU_H
37#define _RTEMS_SCORE_CPU_H
38
39#ifdef __cplusplus
40extern "C" {
41#endif
42
43#include <rtems/score/basedefs.h>
44#include <rtems/score/no_cpu.h>
45
46/* conditional compilation parameters */
47
48/**
49 * Does the CPU follow the simple vectored interrupt model?
50 *
51 * If TRUE, then RTEMS allocates the vector table it internally manages.
52 * If FALSE, then the BSP is assumed to allocate and manage the vector
53 * table
54 *
55 * Port Specific Information:
56 *
57 * XXX document implementation including references if appropriate
58 */
59#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
60
61/**
62 * Does the RTEMS invoke the user's ISR with the vector number and
63 * a pointer to the saved interrupt frame (1) or just the vector
64 * number (0)?
65 *
66 * Port Specific Information:
67 *
68 * XXX document implementation including references if appropriate
69 */
70#define CPU_ISR_PASSES_FRAME_POINTER FALSE
71
72/**
73 * @def CPU_HARDWARE_FP
74 *
75 * Does the CPU have hardware floating point?
76 *
77 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
78 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
79 *
80 * If there is a FP coprocessor such as the i387 or mc68881, then
81 * the answer is TRUE.
82 *
83 * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
84 * It indicates whether or not this CPU model has FP support.  For
85 * example, it would be possible to have an i386_nofp CPU model
86 * which set this to false to indicate that you have an i386 without
87 * an i387 and wish to leave floating point support out of RTEMS.
88 */
89
90/**
91 * @def CPU_SOFTWARE_FP
92 *
93 * Does the CPU have no hardware floating point and GCC provides a
94 * software floating point implementation which must be context
95 * switched?
96 *
97 * This feature conditional is used to indicate whether or not there
98 * is software implemented floating point that must be context
99 * switched.  The determination of whether or not this applies
100 * is very tool specific and the state saved/restored is also
101 * compiler specific.
102 *
103 * Port Specific Information:
104 *
105 * XXX document implementation including references if appropriate
106 */
107#if ( NO_CPU_HAS_FPU == 1 )
108#define CPU_HARDWARE_FP     TRUE
109#else
110#define CPU_HARDWARE_FP     FALSE
111#endif
112#define CPU_SOFTWARE_FP     FALSE
113
114/**
115 * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
116 *
117 * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
118 * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
119 *
120 * So far, the only CPUs in which this option has been used are the
121 * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
122 * gcc both implicitly used the floating point registers to perform
123 * integer multiplies.  Similarly, the PowerPC port of gcc has been
124 * seen to allocate floating point local variables and touch the FPU
125 * even when the flow through a subroutine (like vfprintf()) might
126 * not use floating point formats.
127 *
128 * If a function which you would not think utilize the FP unit DOES,
129 * then one can not easily predict which tasks will use the FP hardware.
130 * In this case, this option should be TRUE.
131 *
132 * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
133 *
134 * Port Specific Information:
135 *
136 * XXX document implementation including references if appropriate
137 */
138#define CPU_ALL_TASKS_ARE_FP     TRUE
139
140/**
141 * Should the IDLE task have a floating point context?
142 *
143 * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
144 * and it has a floating point context which is switched in and out.
145 * If FALSE, then the IDLE task does not have a floating point context.
146 *
147 * Setting this to TRUE negatively impacts the time required to preempt
148 * the IDLE task from an interrupt because the floating point context
149 * must be saved as part of the preemption.
150 *
151 * Port Specific Information:
152 *
153 * XXX document implementation including references if appropriate
154 */
155#define CPU_IDLE_TASK_IS_FP      FALSE
156
157/**
158 * Should the saving of the floating point registers be deferred
159 * until a context switch is made to another different floating point
160 * task?
161 *
162 * If TRUE, then the floating point context will not be stored until
163 * necessary.  It will remain in the floating point registers and not
164 * disturned until another floating point task is switched to.
165 *
166 * If FALSE, then the floating point context is saved when a floating
167 * point task is switched out and restored when the next floating point
168 * task is restored.  The state of the floating point registers between
169 * those two operations is not specified.
170 *
171 * If the floating point context does NOT have to be saved as part of
172 * interrupt dispatching, then it should be safe to set this to TRUE.
173 *
174 * Setting this flag to TRUE results in using a different algorithm
175 * for deciding when to save and restore the floating point context.
176 * The deferred FP switch algorithm minimizes the number of times
177 * the FP context is saved and restored.  The FP context is not saved
178 * until a context switch is made to another, different FP task.
179 * Thus in a system with only one FP task, the FP context will never
180 * be saved or restored.
181 *
182 * Port Specific Information:
183 *
184 * XXX document implementation including references if appropriate
185 */
186#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
187
188/**
189 * @brief Enables a robust thread dispatch if set to TRUE.
190 *
191 * In general, it is an application bug to call blocking operating system
192 * services with interrupts disabled.  In most situations this only increases
193 * the interrupt latency.  However, on SMP configurations or on some CPU port
194 * like ARM Cortex-M it leads to undefined system behaviour.  It order to ease
195 * the application development, this error condition is checked at run-time in
196 * case this CPU port option is defined to TRUE.
197 */
198#define CPU_ENABLE_ROBUST_THREAD_DISPATCH FALSE
199
200/**
201 * Does this port provide a CPU dependent IDLE task implementation?
202 *
203 * If TRUE, then the routine @ref _CPU_Thread_Idle_body
204 * must be provided and is the default IDLE thread body instead of
205 * @ref _CPU_Thread_Idle_body.
206 *
207 * If FALSE, then use the generic IDLE thread body if the BSP does
208 * not provide one.
209 *
210 * This is intended to allow for supporting processors which have
211 * a low power or idle mode.  When the IDLE thread is executed, then
212 * the CPU can be powered down.
213 *
214 * The order of precedence for selecting the IDLE thread body is:
215 *
216 *   -#  BSP provided
217 *   -#  CPU dependent (if provided)
218 *   -#  generic (if no BSP and no CPU dependent)
219 *
220 * Port Specific Information:
221 *
222 * XXX document implementation including references if appropriate
223 */
224#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
225
226/**
227 * Does the stack grow up (toward higher addresses) or down
228 * (toward lower addresses)?
229 *
230 * If TRUE, then the grows upward.
231 * If FALSE, then the grows toward smaller addresses.
232 *
233 * Port Specific Information:
234 *
235 * XXX document implementation including references if appropriate
236 */
237#define CPU_STACK_GROWS_UP               TRUE
238
239/**
240 * The maximum cache line size in bytes.
241 *
242 * The actual processor may use no cache or a smaller cache line size.
243 */
244#define CPU_CACHE_LINE_BYTES 32
245
246/**
247 * The following is the variable attribute used to force alignment
248 * of critical RTEMS structures.  On some processors it may make
249 * sense to have these aligned on tighter boundaries than
250 * the minimum requirements of the compiler in order to have as
251 * much of the critical data area as possible in a cache line.
252 *
253 * Port Specific Information:
254 *
255 * XXX document implementation including references if appropriate
256 */
257#define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES )
258
259/**
260 * @ingroup CPUInterrupt
261 *
262 * The following defines the number of bits actually used in the
263 * interrupt field of the task mode.  How those bits map to the
264 * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
265 *
266 * Port Specific Information:
267 *
268 * XXX document implementation including references if appropriate
269 */
270#define CPU_MODES_INTERRUPT_MASK   0x00000001
271
272/**
273 * @brief Maximum number of processors of all systems supported by this CPU
274 * port.
275 */
276#define CPU_MAXIMUM_PROCESSORS 32
277
278/*
279 *  Processor defined structures required for cpukit/score.
280 *
281 *  Port Specific Information:
282 *
283 *  XXX document implementation including references if appropriate
284 */
285
286/* may need to put some structures here.  */
287
288/**
289 * @defgroup CPUContext Processor Dependent Context Management
290 *
291 * From the highest level viewpoint, there are 2 types of context to save.
292 *
293 *    -# Interrupt registers to save
294 *    -# Task level registers to save
295 *
296 * Since RTEMS handles integer and floating point contexts separately, this
297 * means we have the following 3 context items:
298 *
299 *    -# task level context stuff::  Context_Control
300 *    -# floating point task stuff:: Context_Control_fp
301 *    -# special interrupt level context :: CPU_Interrupt_frame
302 *
303 * On some processors, it is cost-effective to save only the callee
304 * preserved registers during a task context switch.  This means
305 * that the ISR code needs to save those registers which do not
306 * persist across function calls.  It is not mandatory to make this
307 * distinctions between the caller/callee saves registers for the
308 * purpose of minimizing context saved during task switch and on interrupts.
309 * If the cost of saving extra registers is minimal, simplicity is the
310 * choice.  Save the same context on interrupt entry as for tasks in
311 * this case.
312 *
313 * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
314 * care should be used in designing the context area.
315 *
316 * On some CPUs with hardware floating point support, the Context_Control_fp
317 * structure will not be used or it simply consist of an array of a
318 * fixed number of bytes.   This is done when the floating point context
319 * is dumped by a "FP save context" type instruction and the format
320 * is not really defined by the CPU.  In this case, there is no need
321 * to figure out the exact format -- only the size.  Of course, although
322 * this is enough information for RTEMS, it is probably not enough for
323 * a debugger such as gdb.  But that is another problem.
324 *
325 * Port Specific Information:
326 *
327 * XXX document implementation including references if appropriate
328 *
329 */
330/**@{**/
331
332/**
333 * @ingroup Management
334 * This defines the minimal set of integer and processor state registers
335 * that must be saved during a voluntary context switch from one thread
336 * to another.
337 */
338typedef struct {
339    /**
340     * This field is a hint that a port will have a number of integer
341     * registers that need to be saved at a context switch.
342     */
343    uint32_t   some_integer_register;
344    /**
345     * This field is a hint that a port will have a number of system
346     * registers that need to be saved at a context switch.
347     */
348    uint32_t   some_system_register;
349
350    /**
351     * This field is a hint that a port will have a register that
352     * is the stack pointer.
353     */
354    uint32_t   stack_pointer;
355
356#ifdef RTEMS_SMP
357    /**
358     * @brief On SMP configurations the thread context must contain a boolean
359     * indicator to signal if this context is executing on a processor.
360     *
361     * This field must be updated during a context switch.  The context switch
362     * to the heir must wait until the heir context indicates that it is no
363     * longer executing on a processor.  This indicator must be updated using
364     * an atomic test and set operation to ensure that at most one processor
365     * uses the heir context at the same time.  The context switch must also
366     * check for a potential new heir thread for this processor in case the
367     * heir context is not immediately available.  Update the executing thread
368     * for this processor only if necessary to avoid a cache line
369     * monopolization.
370     *
371     * @code
372     * void _CPU_Context_switch(
373     *   Context_Control *executing_context,
374     *   Context_Control *heir_context
375     * )
376     * {
377     *   save( executing_context );
378     *
379     *   executing_context->is_executing = false;
380     *   memory_barrier();
381     *
382     *   if ( test_and_set( &heir_context->is_executing ) ) {
383     *     do {
384     *       Per_CPU_Control *cpu_self = _Per_CPU_Get_snapshot();
385     *       Thread_Control *executing = cpu_self->executing;
386     *       Thread_Control *heir = cpu_self->heir;
387     *
388     *       if ( heir != executing ) {
389     *         cpu_self->executing = heir;
390     *         heir_context = (Context_Control *)
391     *           ((uintptr_t) heir + (uintptr_t) executing_context
392     *             - (uintptr_t) executing)
393     *       }
394     *     } while ( test_and_set( &heir_context->is_executing ) );
395     *   }
396     *
397     *   restore( heir_context );
398     * }
399     * @endcode
400     */
401    volatile bool is_executing;
402#endif
403} Context_Control;
404
405/**
406 * @ingroup Management
407 *
408 * This macro returns the stack pointer associated with @a _context.
409 *
410 * @param[in] _context is the thread context area to access
411 *
412 * @return This method returns the stack pointer.
413 */
414#define _CPU_Context_Get_SP( _context ) \
415  (_context)->stack_pointer
416
417/**
418 * @ingroup Management
419 *
420 * This defines the complete set of floating point registers that must
421 * be saved during any context switch from one thread to another.
422 */
423typedef struct {
424    /** FPU registers are listed here */
425    double      some_float_register;
426} Context_Control_fp;
427
428/**
429 * @ingroup Management
430 *
431 * This defines the set of integer and processor state registers that must
432 * be saved during an interrupt.  This set does not include any which are
433 * in @ref Context_Control.
434 */
435typedef struct {
436    /**
437     * This field is a hint that a port will have a number of integer
438     * registers that need to be saved when an interrupt occurs or
439     * when a context switch occurs at the end of an ISR.
440     */
441    uint32_t   special_interrupt_register;
442} CPU_Interrupt_frame;
443
444/**
445 * This variable is optional.  It is used on CPUs on which it is difficult
446 * to generate an "uninitialized" FP context.  It is filled in by
447 * @ref _CPU_Initialize and copied into the task's FP context area during
448 * @ref _CPU_Context_Initialize.
449 *
450 * Port Specific Information:
451 *
452 * XXX document implementation including references if appropriate
453 */
454extern Context_Control_fp _CPU_Null_fp_context;
455
456/** @} */
457
458/**
459 * @defgroup CPUInterrupt Processor Dependent Interrupt Management
460 *
461 * RTEMS supports a software managed interrupt stack.  The interrupt stacks
462 * are statically allocated by <rtems/confdefs.h> and the switch is performed
463 * by hardware or the interrupt processing code.  These variables contain
464 * pointers to the lowest and highest addresses in the chunk of memory
465 * allocated for the interrupt stack.  Since it is unknown whether the stack
466 * grows up or down (in general), this give the CPU dependent code the option
467 * of picking the version it wants to use.
468 *
469 * Port Specific Information:
470 *
471 * XXX document implementation including references if appropriate
472 */
473
474/*
475 *  Nothing prevents the porter from declaring more CPU specific variables.
476 *
477 *  Port Specific Information:
478 *
479 *  XXX document implementation including references if appropriate
480 */
481
482/* XXX: if needed, put more variables here */
483
484/**
485 * @ingroup CPUContext
486 *
487 * The size of the floating point context area.  On some CPUs this
488 * will not be a "sizeof" because the format of the floating point
489 * area is not defined -- only the size is.  This is usually on
490 * CPUs with a "floating point save context" instruction.
491 *
492 * Port Specific Information:
493 *
494 * XXX document implementation including references if appropriate
495 */
496#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
497
498/**
499 * Amount of extra stack (above minimum stack size) required by
500 * MPCI receive server thread.  Remember that in a multiprocessor
501 * system this thread must exist and be able to process all directives.
502 *
503 * Port Specific Information:
504 *
505 * XXX document implementation including references if appropriate
506 */
507#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
508
509/**
510 * @ingroup CPUInterrupt
511 *
512 * This defines the number of entries in the _ISR_Vector_table managed by RTEMS
513 * in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be a
514 * compile-time constant.
515 *
516 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
517 * FALSE.
518 */
519#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
520
521/**
522 * @ingroup CPUInterrupt
523 *
524 * This defines the highest interrupt vector number for this port in case
525 * CPU_SIMPLE_VECTORED_INTERRUPTS is defined to TRUE.  It must be less than
526 * CPU_INTERRUPT_NUMBER_OF_VECTORS.  It may be not a compile-time constant.
527 *
528 * It must be undefined in case CPU_SIMPLE_VECTORED_INTERRUPTS is defined to
529 * FALSE.
530 */
531#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
532
533/**
534 * @ingroup CPUInterrupt
535 *
536 * This is defined if the port has a special way to report the ISR nesting
537 * level.  Most ports maintain the variable @a _ISR_Nest_level.
538 */
539#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
540
541/**
542 * @ingroup CPUContext
543 *
544 * Should be large enough to run all RTEMS tests.  This ensures
545 * that a "reasonable" small application should not have any problems.
546 *
547 * Port Specific Information:
548 *
549 * XXX document implementation including references if appropriate
550 */
551#define CPU_STACK_MINIMUM_SIZE          (1024*4)
552
553/**
554 * Size of a pointer.
555 *
556 * This must be an integer literal that can be used by the assembler.  This
557 * value will be used to calculate offsets of structure members.  These
558 * offsets will be used in assembler code.
559 */
560#define CPU_SIZEOF_POINTER         4
561
562/**
563 * CPU's worst alignment requirement for data types on a byte boundary.  This
564 * alignment does not take into account the requirements for the stack.  It
565 * must be a power of two greater than or equal to two.  The power of two
566 * requirement makes it possible to align values easily using simple bit
567 * operations.
568 *
569 * Port Specific Information:
570 *
571 * XXX document implementation including references if appropriate
572 */
573#define CPU_ALIGNMENT              8
574
575/**
576 * This number corresponds to the byte alignment requirement for the
577 * heap handler.  This alignment requirement may be stricter than that
578 * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
579 * common for the heap to follow the same alignment requirement as
580 * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
581 * the heap, then this should be set to @ref CPU_ALIGNMENT.
582 *
583 * NOTE:  It must be a power of two greater than or equal to two.  The
584 *        requirement to be a multiple of two is because the heap uses the
585 *        least significant field of the front and back flags to indicate that
586 *        a block is in use or free.  So you do not want any odd length blocks
587 *        really putting length data in that bit.
588 *
589 *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
590 *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
591 *        elements allocated from the heap meet all restrictions.
592 *
593 * Port Specific Information:
594 *
595 * XXX document implementation including references if appropriate
596 */
597#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
598
599/**
600 * This number corresponds to the byte alignment requirement for memory
601 * buffers allocated by the partition manager.  This alignment requirement
602 * may be stricter than that for the data types alignment specified by
603 * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
604 * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
605 * strict enough for the partition, then this should be set to
606 * @ref CPU_ALIGNMENT.
607 *
608 * NOTE:  This does not have to be a power of 2.  It does have to
609 *        be greater or equal to than @ref CPU_ALIGNMENT.
610 *
611 * Port Specific Information:
612 *
613 * XXX document implementation including references if appropriate
614 */
615#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
616
617/**
618 * This number corresponds to the byte alignment requirement for the
619 * stack.  This alignment requirement may be stricter than that for the
620 * data types alignment specified by @ref CPU_ALIGNMENT.  If the
621 * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
622 * set to 0.
623 *
624 * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
625 *
626 * Port Specific Information:
627 *
628 * XXX document implementation including references if appropriate
629 */
630#define CPU_STACK_ALIGNMENT        0
631
632/**
633 * The alignment of the interrupt stack in bytes.
634 *
635 * The alignment should take the stack ABI and the cache line size into
636 * account.
637 */
638#define CPU_INTERRUPT_STACK_ALIGNMENT CPU_CACHE_LINE_BYTES
639
640/*
641 *  ISR handler macros
642 */
643
644/**
645 * @ingroup CPUInterrupt
646 *
647 * Support routine to initialize the RTEMS vector table after it is allocated.
648 *
649 * Port Specific Information:
650 *
651 * XXX document implementation including references if appropriate
652 */
653#define _CPU_Initialize_vectors()
654
655/**
656 * @ingroup CPUInterrupt
657 *
658 * Disable all interrupts for an RTEMS critical section.  The previous
659 * level is returned in @a _isr_cookie.
660 *
661 * @param[out] _isr_cookie will contain the previous level cookie
662 *
663 * Port Specific Information:
664 *
665 * XXX document implementation including references if appropriate
666 */
667#define _CPU_ISR_Disable( _isr_cookie ) \
668  { \
669    (_isr_cookie) = 0;   /* do something to prevent warnings */ \
670  }
671
672/**
673 * @ingroup CPUInterrupt
674 *
675 * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
676 * This indicates the end of an RTEMS critical section.  The parameter
677 * @a _isr_cookie is not modified.
678 *
679 * @param[in] _isr_cookie contain the previous level cookie
680 *
681 * Port Specific Information:
682 *
683 * XXX document implementation including references if appropriate
684 */
685#define _CPU_ISR_Enable( _isr_cookie )  \
686  { \
687  }
688
689/**
690 * @ingroup CPUInterrupt
691 *
692 * This temporarily restores the interrupt to @a _isr_cookie before immediately
693 * disabling them again.  This is used to divide long RTEMS critical
694 * sections into two or more parts.  The parameter @a _isr_cookie is not
695 * modified.
696 *
697 * @param[in] _isr_cookie contain the previous level cookie
698 *
699 * Port Specific Information:
700 *
701 * XXX document implementation including references if appropriate
702 */
703#define _CPU_ISR_Flash( _isr_cookie ) \
704  { \
705  }
706
707/**
708 * @brief Returns true if interrupts are enabled in the specified ISR level,
709 * otherwise returns false.
710 *
711 * @param[in] level The ISR level.
712 *
713 * @retval true Interrupts are enabled in the ISR level.
714 * @retval false Otherwise.
715 */
716RTEMS_INLINE_ROUTINE bool _CPU_ISR_Is_enabled( uint32_t level )
717{
718  return false;
719}
720
721/**
722 * @ingroup CPUInterrupt
723 *
724 * This routine and @ref _CPU_ISR_Get_level
725 * Map the interrupt level in task mode onto the hardware that the CPU
726 * actually provides.  Currently, interrupt levels which do not
727 * map onto the CPU in a generic fashion are undefined.  Someday,
728 * it would be nice if these were "mapped" by the application
729 * via a callout.  For example, m68k has 8 levels 0 - 7, levels
730 * 8 - 255 would be available for bsp/application specific meaning.
731 * This could be used to manage a programmable interrupt controller
732 * via the rtems_task_mode directive.
733 *
734 * Port Specific Information:
735 *
736 * XXX document implementation including references if appropriate
737 */
738#define _CPU_ISR_Set_level( new_level ) \
739  { \
740  }
741
742/**
743 * @ingroup CPUInterrupt
744 *
745 * Return the current interrupt disable level for this task in
746 * the format used by the interrupt level portion of the task mode.
747 *
748 * NOTE: This routine usually must be implemented as a subroutine.
749 *
750 * Port Specific Information:
751 *
752 * XXX document implementation including references if appropriate
753 */
754uint32_t   _CPU_ISR_Get_level( void );
755
756/* end of ISR handler macros */
757
758/* Context handler macros */
759
760/**
761 * @ingroup CPUContext
762 *
763 * @brief Destroys the context of the thread.
764 *
765 * It must be implemented as a macro and an implementation is optional.  The
766 * default implementation does nothing.
767 *
768 * @param[in] _the_thread The corresponding thread.
769 * @param[in] _the_context The context to destroy.
770 *
771 * Port Specific Information:
772 *
773 * XXX document implementation including references if appropriate
774 */
775#define _CPU_Context_Destroy( _the_thread, _the_context ) \
776  { \
777  }
778
779/**
780 *  @ingroup CPUContext
781 *
782 * Initialize the context to a state suitable for starting a
783 * task after a context restore operation.  Generally, this
784 * involves:
785 *
786 *    - setting a starting address
787 *    - preparing the stack
788 *    - preparing the stack and frame pointers
789 *    - setting the proper interrupt level in the context
790 *    - initializing the floating point context
791 *
792 * This routine generally does not set any unnecessary register
793 * in the context.  The state of the "general data" registers is
794 * undefined at task start time.
795 *
796 * The ISR dispatch disable field of the context must be cleared to zero if it
797 * is used by the CPU port.  Otherwise, a thread restart results in
798 * unpredictable behaviour.
799 *
800 * @param[in] _the_context is the context structure to be initialized
801 * @param[in] _stack_base is the lowest physical address of this task's stack
802 * @param[in] _size is the size of this task's stack
803 * @param[in] _isr is the interrupt disable level
804 * @param[in] _entry_point is the thread's entry point.  This is
805 *        always @a _Thread_Handler
806 * @param[in] _is_fp is TRUE if the thread is to be a floating
807 *       point thread.  This is typically only used on CPUs where the
808 *       FPU may be easily disabled by software such as on the SPARC
809 *       where the PSR contains an enable FPU bit.
810 * @param[in] _tls_area The thread-local storage (TLS) area.
811 *
812 * Port Specific Information:
813 *
814 * XXX document implementation including references if appropriate
815 */
816#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
817                                 _isr, _entry_point, _is_fp, _tls_area ) \
818  { \
819  }
820
821/**
822 * This routine is responsible for somehow restarting the currently
823 * executing task.  If you are lucky, then all that is necessary
824 * is restoring the context.  Otherwise, there will need to be
825 * a special assembly routine which does something special in this
826 * case.  For many ports, simply adding a label to the restore path
827 * of @ref _CPU_Context_switch will work.  On other ports, it may be
828 * possibly to load a few arguments and jump to the restore path. It will
829 * not work if restarting self conflicts with the stack frame
830 * assumptions of restoring a context.
831 *
832 * Port Specific Information:
833 *
834 * XXX document implementation including references if appropriate
835 */
836#define _CPU_Context_Restart_self( _the_context ) \
837   _CPU_Context_restore( (_the_context) );
838
839/**
840 * This routine initializes the FP context area passed to it to.
841 * There are a few standard ways in which to initialize the
842 * floating point context.  The code included for this macro assumes
843 * that this is a CPU in which a "initial" FP context was saved into
844 * @a _CPU_Null_fp_context and it simply copies it to the destination
845 * context passed to it.
846 *
847 * Other floating point context save/restore models include:
848 *   -# not doing anything, and
849 *   -# putting a "null FP status word" in the correct place in the FP context.
850 *
851 * @param[in] _destination is the floating point context area
852 *
853 * Port Specific Information:
854 *
855 * XXX document implementation including references if appropriate
856 */
857#define _CPU_Context_Initialize_fp( _destination ) \
858  { \
859   *(*(_destination)) = _CPU_Null_fp_context; \
860  }
861
862/* end of Context handler macros */
863
864/* Fatal Error manager macros */
865
866/**
867 * This routine copies _error into a known place -- typically a stack
868 * location or a register, optionally disables interrupts, and
869 * halts/stops the CPU.
870 *
871 * Port Specific Information:
872 *
873 * XXX document implementation including references if appropriate
874 */
875#define _CPU_Fatal_halt( _source, _error ) \
876  { \
877  }
878
879/* end of Fatal Error manager macros */
880
881/* Bitfield handler macros */
882
883/**
884 * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
885 *
886 * This set of routines are used to implement fast searches for
887 * the most important ready task.
888 *
889 */
890/**@{**/
891
892/**
893 * This definition is set to TRUE if the port uses the generic bitfield
894 * manipulation implementation.
895 */
896#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
897
898/**
899 * This routine sets @a _output to the bit number of the first bit
900 * set in @a _value.  @a _value is of CPU dependent type
901 * @a Priority_bit_map_Word.  This type may be either 16 or 32 bits
902 * wide although only the 16 least significant bits will be used.
903 *
904 * There are a number of variables in using a "find first bit" type
905 * instruction.
906 *
907 *   -# What happens when run on a value of zero?
908 *   -# Bits may be numbered from MSB to LSB or vice-versa.
909 *   -# The numbering may be zero or one based.
910 *   -# The "find first bit" instruction may search from MSB or LSB.
911 *
912 * RTEMS guarantees that (1) will never happen so it is not a concern.
913 * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
914 * @ref _CPU_Priority_bits_index.  These three form a set of routines
915 * which must logically operate together.  Bits in the _value are
916 * set and cleared based on masks built by @ref _CPU_Priority_Mask.
917 * The basic major and minor values calculated by @ref _Priority_Major
918 * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
919 * to properly range between the values returned by the "find first bit"
920 * instruction.  This makes it possible for @ref _Priority_Get_highest to
921 * calculate the major and directly index into the minor table.
922 * This mapping is necessary to ensure that 0 (a high priority major/minor)
923 * is the first bit found.
924 *
925 * This entire "find first bit" and mapping process depends heavily
926 * on the manner in which a priority is broken into a major and minor
927 * components with the major being the 4 MSB of a priority and minor
928 * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
929 * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
930 * to the lowest priority.
931 *
932 * If your CPU does not have a "find first bit" instruction, then
933 * there are ways to make do without it.  Here are a handful of ways
934 * to implement this in software:
935 *
936@verbatim
937      - a series of 16 bit test instructions
938      - a "binary search using if's"
939      - _number = 0
940        if _value > 0x00ff
941          _value >>=8
942          _number = 8;
943
944        if _value > 0x0000f
945          _value >=8
946          _number += 4
947
948        _number += bit_set_table[ _value ]
949@endverbatim
950
951 *   where bit_set_table[ 16 ] has values which indicate the first
952 *     bit set
953 *
954 * @param[in] _value is the value to be scanned
955 * @param[in] _output is the first bit set
956 *
957 * Port Specific Information:
958 *
959 * XXX document implementation including references if appropriate
960 */
961
962#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
963#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
964  { \
965    (_output) = 0;   /* do something to prevent warnings */ \
966  }
967#endif
968
969/** @} */
970
971/* end of Bitfield handler macros */
972
973/**
974 * This routine builds the mask which corresponds to the bit fields
975 * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
976 * for that routine.
977 *
978 * Port Specific Information:
979 *
980 * XXX document implementation including references if appropriate
981 */
982#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
983
984#define _CPU_Priority_Mask( _bit_number ) \
985  ( 1 << (_bit_number) )
986
987#endif
988
989/**
990 * @ingroup CPUBitfield
991 *
992 * This routine translates the bit numbers returned by
993 * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
994 * a major or minor component of a priority.  See the discussion
995 * for that routine.
996 *
997 * @param[in] _priority is the major or minor number to translate
998 *
999 * Port Specific Information:
1000 *
1001 * XXX document implementation including references if appropriate
1002 */
1003#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1004
1005#define _CPU_Priority_bits_index( _priority ) \
1006  (_priority)
1007
1008#endif
1009
1010/* end of Priority handler macros */
1011
1012/* functions */
1013
1014/**
1015 * This routine performs CPU dependent initialization.
1016 *
1017 * Port Specific Information:
1018 *
1019 * XXX document implementation including references if appropriate
1020 */
1021void _CPU_Initialize(void);
1022
1023/**
1024 * @ingroup CPUInterrupt
1025 *
1026 * This routine installs a "raw" interrupt handler directly into the
1027 * processor's vector table.
1028 *
1029 * @param[in] vector is the vector number
1030 * @param[in] new_handler is the raw ISR handler to install
1031 * @param[in] old_handler is the previously installed ISR Handler
1032 *
1033 * Port Specific Information:
1034 *
1035 * XXX document implementation including references if appropriate
1036 */
1037void _CPU_ISR_install_raw_handler(
1038  uint32_t    vector,
1039  proc_ptr    new_handler,
1040  proc_ptr   *old_handler
1041);
1042
1043/**
1044 * @ingroup CPUInterrupt
1045 *
1046 * This routine installs an interrupt vector.
1047 *
1048 * @param[in] vector is the vector number
1049 * @param[in] new_handler is the RTEMS ISR handler to install
1050 * @param[in] old_handler is the previously installed ISR Handler
1051 *
1052 * Port Specific Information:
1053 *
1054 * XXX document implementation including references if appropriate
1055 */
1056void _CPU_ISR_install_vector(
1057  uint32_t    vector,
1058  proc_ptr    new_handler,
1059  proc_ptr   *old_handler
1060);
1061
1062/**
1063 * This routine is the CPU dependent IDLE thread body.
1064 *
1065 * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1066 *         is TRUE.
1067 *
1068 * Port Specific Information:
1069 *
1070 * XXX document implementation including references if appropriate
1071 */
1072void *_CPU_Thread_Idle_body( uintptr_t ignored );
1073
1074/**
1075 * @ingroup CPUContext
1076 *
1077 * This routine switches from the run context to the heir context.
1078 *
1079 * @param[in] run points to the context of the currently executing task
1080 * @param[in] heir points to the context of the heir task
1081 *
1082 * Port Specific Information:
1083 *
1084 * XXX document implementation including references if appropriate
1085 */
1086void _CPU_Context_switch(
1087  Context_Control  *run,
1088  Context_Control  *heir
1089);
1090
1091/**
1092 * @ingroup CPUContext
1093 *
1094 * This routine is generally used only to restart self in an
1095 * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1096 *
1097 * @param[in] new_context points to the context to be restored.
1098 *
1099 * NOTE: May be unnecessary to reload some registers.
1100 *
1101 * Port Specific Information:
1102 *
1103 * XXX document implementation including references if appropriate
1104 */
1105void _CPU_Context_restore(
1106  Context_Control *new_context
1107) RTEMS_NO_RETURN;
1108
1109/**
1110 * @ingroup CPUContext
1111 *
1112 * This routine saves the floating point context passed to it.
1113 *
1114 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1115 * point context area
1116 *
1117 * @return on output @a *fp_context_ptr will contain the address that
1118 * should be used with @ref _CPU_Context_restore_fp to restore this context.
1119 *
1120 * Port Specific Information:
1121 *
1122 * XXX document implementation including references if appropriate
1123 */
1124void _CPU_Context_save_fp(
1125  Context_Control_fp **fp_context_ptr
1126);
1127
1128/**
1129 * @ingroup CPUContext
1130 *
1131 * This routine restores the floating point context passed to it.
1132 *
1133 * @param[in] fp_context_ptr is a pointer to a pointer to a floating
1134 * point context area to restore
1135 *
1136 * @return on output @a *fp_context_ptr will contain the address that
1137 * should be used with @ref _CPU_Context_save_fp to save this context.
1138 *
1139 * Port Specific Information:
1140 *
1141 * XXX document implementation including references if appropriate
1142 */
1143void _CPU_Context_restore_fp(
1144  Context_Control_fp **fp_context_ptr
1145);
1146
1147/**
1148 * @brief The set of registers that specifies the complete processor state.
1149 *
1150 * The CPU exception frame may be available in fatal error conditions like for
1151 * example illegal opcodes, instruction fetch errors, or data access errors.
1152 *
1153 * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
1154 * rtems_exception_frame_print().
1155 */
1156typedef struct {
1157  uint32_t processor_state_register;
1158  uint32_t integer_registers [1];
1159  double float_registers [1];
1160} CPU_Exception_frame;
1161
1162/**
1163 * @brief Prints the exception frame via printk().
1164 *
1165 * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
1166 */
1167void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
1168
1169/**
1170 * @ingroup CPUEndian
1171 *
1172 * The following routine swaps the endian format of an unsigned int.
1173 * It must be static because it is referenced indirectly.
1174 *
1175 * This version will work on any processor, but if there is a better
1176 * way for your CPU PLEASE use it.  The most common way to do this is to:
1177 *
1178 *    swap least significant two bytes with 16-bit rotate
1179 *    swap upper and lower 16-bits
1180 *    swap most significant two bytes with 16-bit rotate
1181 *
1182 * Some CPUs have special instructions which swap a 32-bit quantity in
1183 * a single instruction (e.g. i486).  It is probably best to avoid
1184 * an "endian swapping control bit" in the CPU.  One good reason is
1185 * that interrupts would probably have to be disabled to ensure that
1186 * an interrupt does not try to access the same "chunk" with the wrong
1187 * endian.  Another good reason is that on some CPUs, the endian bit
1188 * endianness for ALL fetches -- both code and data -- so the code
1189 * will be fetched incorrectly.
1190 *
1191 * @param[in] value is the value to be swapped
1192 * @return the value after being endian swapped
1193 *
1194 * Port Specific Information:
1195 *
1196 * XXX document implementation including references if appropriate
1197 */
1198static inline uint32_t CPU_swap_u32(
1199  uint32_t value
1200)
1201{
1202  uint32_t byte1, byte2, byte3, byte4, swapped;
1203
1204  byte4 = (value >> 24) & 0xff;
1205  byte3 = (value >> 16) & 0xff;
1206  byte2 = (value >> 8)  & 0xff;
1207  byte1 =  value        & 0xff;
1208
1209  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1210  return swapped;
1211}
1212
1213/**
1214 * @ingroup CPUEndian
1215 *
1216 * This routine swaps a 16 bir quantity.
1217 *
1218 * @param[in] value is the value to be swapped
1219 * @return the value after being endian swapped
1220 */
1221#define CPU_swap_u16( value ) \
1222  (((value&0xff) << 8) | ((value >> 8)&0xff))
1223
1224/**
1225 * @brief Unsigned integer type for CPU counter values.
1226 */
1227typedef uint32_t CPU_Counter_ticks;
1228
1229/**
1230 * @brief Returns the current CPU counter frequency in Hz.
1231 *
1232 * @return The current CPU counter frequency in Hz.
1233 */
1234uint32_t _CPU_Counter_frequency( void );
1235
1236/**
1237 * @brief Returns the current CPU counter value.
1238 *
1239 * A CPU counter is some free-running counter.  It ticks usually with a
1240 * frequency close to the CPU or system bus clock.  The board support package
1241 * must ensure that this function works before the RTEMS initialization.
1242 * Otherwise invalid profiling statistics will be gathered.
1243 *
1244 * @return The current CPU counter value.
1245 */
1246CPU_Counter_ticks _CPU_Counter_read( void );
1247
1248/**
1249 * @brief Returns the difference between the second and first CPU counter
1250 * value.
1251 *
1252 * This operation may be carried out as a modulo operation depending on the
1253 * range of the CPU counter device.
1254 *
1255 * @param[in] second The second CPU counter value.
1256 * @param[in] first The first CPU counter value.
1257 *
1258 * @return Returns second minus first modulo counter period.
1259 */
1260CPU_Counter_ticks _CPU_Counter_difference(
1261  CPU_Counter_ticks second,
1262  CPU_Counter_ticks first
1263);
1264
1265#ifdef RTEMS_SMP
1266  /**
1267   * @brief Performs CPU specific SMP initialization in the context of the boot
1268   * processor.
1269   *
1270   * This function is invoked on the boot processor during system
1271   * initialization.  All interrupt stacks are allocated at this point in case
1272   * the CPU port allocates the interrupt stacks.  This function is called
1273   * before _CPU_SMP_Start_processor() or _CPU_SMP_Finalize_initialization() is
1274   * used.
1275   *
1276   * @return The count of physically or virtually available processors.
1277   * Depending on the configuration the application may use not all processors.
1278   */
1279  uint32_t _CPU_SMP_Initialize( void );
1280
1281  /**
1282   * @brief Starts a processor specified by its index.
1283   *
1284   * This function is invoked on the boot processor during system
1285   * initialization.
1286   *
1287   * This function will be called after _CPU_SMP_Initialize().
1288   *
1289   * @param[in] cpu_index The processor index.
1290   *
1291   * @retval true Successful operation.
1292   * @retval false Unable to start this processor.
1293   */
1294  bool _CPU_SMP_Start_processor( uint32_t cpu_index );
1295
1296  /**
1297   * @brief Performs final steps of CPU specific SMP initialization in the
1298   * context of the boot processor.
1299   *
1300   * This function is invoked on the boot processor during system
1301   * initialization.
1302   *
1303   * This function will be called after all processors requested by the
1304   * application have been started.
1305   *
1306   * @param[in] cpu_count The minimum value of the count of processors
1307   * requested by the application configuration and the count of physically or
1308   * virtually available processors.
1309   */
1310  void _CPU_SMP_Finalize_initialization( uint32_t cpu_count );
1311
1312  /**
1313   * @brief Prepares a CPU to start multitasking in terms of SMP.
1314   *
1315   * This function is invoked on all processors requested by the application
1316   * during system initialization.
1317   *
1318   * This function will be called after all processors requested by the
1319   * application have been started right before the context switch to the first
1320   * thread takes place.
1321   */
1322  void _CPU_SMP_Prepare_start_multitasking( void );
1323
1324  /**
1325   * @brief Returns the index of the current processor.
1326   *
1327   * An architecture specific method must be used to obtain the index of the
1328   * current processor in the system.  The set of processor indices is the
1329   * range of integers starting with zero up to the processor count minus one.
1330   */
1331  static inline uint32_t _CPU_SMP_Get_current_processor( void )
1332  {
1333    return 123;
1334  }
1335
1336  /**
1337   * @brief Sends an inter-processor interrupt to the specified target
1338   * processor.
1339   *
1340   * This operation is undefined for target processor indices out of range.
1341   *
1342   * @param[in] target_processor_index The target processor index.
1343   */
1344  void _CPU_SMP_Send_interrupt( uint32_t target_processor_index );
1345
1346  /**
1347   * @brief Broadcasts a processor event.
1348   *
1349   * Some architectures provide a low-level synchronization primitive for
1350   * processors in a multi-processor environment.  Processors waiting for this
1351   * event may go into a low-power state and stop generating system bus
1352   * transactions.  This function must ensure that preceding store operations
1353   * can be observed by other processors.
1354   *
1355   * @see _CPU_SMP_Processor_event_receive().
1356   */
1357  static inline void _CPU_SMP_Processor_event_broadcast( void )
1358  {
1359    __asm__ volatile ( "" : : : "memory" );
1360  }
1361
1362  /**
1363   * @brief Receives a processor event.
1364   *
1365   * This function will wait for the processor event and may wait forever if no
1366   * such event arrives.
1367   *
1368   * @see _CPU_SMP_Processor_event_broadcast().
1369   */
1370  static inline void _CPU_SMP_Processor_event_receive( void )
1371  {
1372    __asm__ volatile ( "" : : : "memory" );
1373  }
1374
1375  /**
1376   * @brief Gets the is executing indicator of the thread context.
1377   *
1378   * @param[in] context The context.
1379   */
1380  static inline bool _CPU_Context_Get_is_executing(
1381    const Context_Control *context
1382  )
1383  {
1384    return context->is_executing;
1385  }
1386
1387  /**
1388   * @brief Sets the is executing indicator of the thread context.
1389   *
1390   * @param[in] context The context.
1391   * @param[in] is_executing The new value for the is executing indicator.
1392   */
1393  static inline void _CPU_Context_Set_is_executing(
1394    Context_Control *context,
1395    bool is_executing
1396  )
1397  {
1398    context->is_executing = is_executing;
1399  }
1400
1401/** Type that can store a 32-bit integer or a pointer. */
1402typedef uintptr_t CPU_Uint32ptr;
1403
1404#endif
1405
1406#ifdef __cplusplus
1407}
1408#endif
1409
1410#endif
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