1 | /* |
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2 | * Copyright (c) 2011 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Obere Lagerstr. 30 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.com/license/LICENSE. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #ifndef _RTEMS_SCORE_NIOS2_UTILITY_H |
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18 | #define _RTEMS_SCORE_NIOS2_UTILITY_H |
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19 | |
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20 | #define NIOS2_CTLREG_INDEX_STATUS 0 |
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21 | #define NIOS2_CTLREG_INDEX_ESTATUS 1 |
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22 | #define NIOS2_CTLREG_INDEX_BSTATUS 2 |
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23 | #define NIOS2_CTLREG_INDEX_IENABLE 3 |
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24 | #define NIOS2_CTLREG_INDEX_IPENDING 4 |
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25 | #define NIOS2_CTLREG_INDEX_CPUID 5 |
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26 | #define NIOS2_CTLREG_INDEX_EXCEPTION 7 |
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27 | #define NIOS2_CTLREG_INDEX_PTEADDR 8 |
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28 | #define NIOS2_CTLREG_INDEX_TLBACC 9 |
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29 | #define NIOS2_CTLREG_INDEX_TLBMISC 10 |
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30 | #define NIOS2_CTLREG_INDEX_BADADDR 12 |
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31 | #define NIOS2_CTLREG_INDEX_CONFIG 13 |
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32 | #define NIOS2_CTLREG_INDEX_MPUBASE 14 |
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33 | #define NIOS2_CTLREG_INDEX_MPUACC 15 |
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34 | |
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35 | #define NIOS2_CONTEXT_OFFSET_R16 0 |
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36 | #define NIOS2_CONTEXT_OFFSET_R17 4 |
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37 | #define NIOS2_CONTEXT_OFFSET_R18 8 |
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38 | #define NIOS2_CONTEXT_OFFSET_R19 12 |
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39 | #define NIOS2_CONTEXT_OFFSET_R20 16 |
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40 | #define NIOS2_CONTEXT_OFFSET_R21 20 |
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41 | #define NIOS2_CONTEXT_OFFSET_R22 24 |
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42 | #define NIOS2_CONTEXT_OFFSET_R23 28 |
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43 | #define NIOS2_CONTEXT_OFFSET_FP 32 |
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44 | #define NIOS2_CONTEXT_OFFSET_STATUS 36 |
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45 | #define NIOS2_CONTEXT_OFFSET_SP 40 |
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46 | #define NIOS2_CONTEXT_OFFSET_RA 44 |
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47 | #define NIOS2_CONTEXT_OFFSET_TDD 48 |
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48 | |
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49 | #define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe |
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50 | #define NIOS2_ISR_STATUS_BITS_IIC 0x00000000 |
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51 | |
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52 | #define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f |
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53 | #define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0 |
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54 | |
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55 | #define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff |
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56 | #define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000 |
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57 | |
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58 | #define NIOS2_STATUS_RSIE (1 << 23) |
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59 | #define NIOS2_STATUS_NMI (1 << 22) |
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60 | #define NIOS2_STATUS_PRS_OFFSET 16 |
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61 | #define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET) |
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62 | #define NIOS2_STATUS_CRS_OFFSET 10 |
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63 | #define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET) |
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64 | #define NIOS2_STATUS_IL_OFFSET 4 |
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65 | #define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET) |
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66 | #define NIOS2_STATUS_IH (1 << 3) |
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67 | #define NIOS2_STATUS_EH (1 << 2) |
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68 | #define NIOS2_STATUS_U (1 << 1) |
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69 | #define NIOS2_STATUS_PIE (1 << 0) |
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70 | |
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71 | #define NIOS2_EXCEPTION_CAUSE_OFFSET 2 |
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72 | #define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET) |
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73 | |
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74 | #define NIOS2_PTEADDR_PTBASE_OFFSET 22 |
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75 | #define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET) |
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76 | #define NIOS2_PTEADDR_VPN_OFFSET 2 |
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77 | #define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET) |
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78 | |
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79 | #define NIOS2_TLBACC_IG_OFFSET 25 |
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80 | #define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET) |
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81 | #define NIOS2_TLBACC_C (1 << 24) |
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82 | #define NIOS2_TLBACC_R (1 << 23) |
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83 | #define NIOS2_TLBACC_W (1 << 22) |
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84 | #define NIOS2_TLBACC_X (1 << 21) |
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85 | #define NIOS2_TLBACC_G (1 << 20) |
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86 | #define NIOS2_TLBACC_PFN_OFFSET 2 |
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87 | #define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET) |
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88 | |
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89 | #define NIOS2_TLBMISC_WAY_OFFSET 20 |
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90 | #define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET) |
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91 | #define NIOS2_TLBMISC_RD (1 << 19) |
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92 | #define NIOS2_TLBMISC_WE (1 << 18) |
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93 | #define NIOS2_TLBMISC_PID_OFFSET 5 |
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94 | #define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET) |
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95 | #define NIOS2_TLBMISC_DBL (1 << 3) |
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96 | #define NIOS2_TLBMISC_BAD (1 << 2) |
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97 | #define NIOS2_TLBMISC_PERM (1 << 1) |
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98 | #define NIOS2_TLBMISC_D (1 << 0) |
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99 | |
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100 | #define NIOS2_CONFIG_ANI (1 << 1) |
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101 | #define NIOS2_CONFIG_PE (1 << 0) |
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102 | |
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103 | #define NIOS2_MPUBASE_BASE_OFFSET 5 |
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104 | #define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET) |
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105 | #define NIOS2_MPUBASE_INDEX_OFFSET 1 |
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106 | |
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107 | /* Avoid redefines with Altera HAL */ |
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108 | #define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) |
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109 | |
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110 | #define NIOS2_MPUBASE_D (1 << 0) |
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111 | |
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112 | #define NIOS2_MPUACC_MASK_OFFSET 6 |
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113 | |
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114 | /* Avoid redefines with Altera HAL */ |
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115 | #define NIOS2_MPUACC_MASK_MASK (0x7fffffc0) |
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116 | |
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117 | #define NIOS2_MPUACC_LIMIT_OFFSET 6 |
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118 | |
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119 | /* Avoid redefines with Altera HAL */ |
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120 | #define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) |
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121 | |
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122 | #define NIOS2_MPUACC_C (1 << 5) |
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123 | #define NIOS2_MPUACC_PERM_OFFSET 2 |
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124 | |
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125 | /* Avoid redefines with Altera HAL */ |
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126 | #define NIOS2_MPUACC_PERM_MASK (0x0000001c) |
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127 | |
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128 | #define NIOS2_MPUACC_RD (1 << 1) |
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129 | #define NIOS2_MPUACC_WR (1 << 0) |
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130 | |
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131 | #ifndef ASM |
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132 | |
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133 | #include <stdint.h> |
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134 | #include <stdbool.h> |
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135 | |
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136 | #ifdef __cplusplus |
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137 | extern "C" { |
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138 | #endif /* __cplusplus */ |
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139 | |
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140 | /** |
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141 | * @brief Nios II specific thread dispatch disabled indicator. |
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142 | * |
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143 | * This global variable is used by the interrupt dispatch support for the |
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144 | * external interrupt controller (EIC) with shadow registers. This makes it |
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145 | * possible to do the thread dispatch after an interrupt without disabled |
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146 | * interrupts and thus probably reduce the maximum interrupt latency. Its |
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147 | * purpose is to prevent unbounded stack usage of the interrupted thread. |
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148 | */ |
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149 | extern uint32_t _Nios2_Thread_dispatch_disabled; |
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150 | |
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151 | /** |
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152 | * @brief This global symbol specifies the status register mask used to disable |
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153 | * interrupts. |
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154 | * |
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155 | * The board support package must provide a global symbol with this name to |
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156 | * specifiy the status register mask used in _CPU_ISR_Disable(). |
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157 | */ |
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158 | extern char _Nios2_ISR_Status_mask []; |
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159 | |
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160 | /** |
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161 | * @brief This symbol specifies the status register bits used to disable |
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162 | * interrupts. |
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163 | * |
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164 | * The board support package must provide a global symbol with this name to |
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165 | * specifiy the status register bits used in _CPU_ISR_Disable(). |
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166 | */ |
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167 | extern char _Nios2_ISR_Status_bits []; |
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168 | |
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169 | static inline uint32_t _Nios2_Get_ctlreg_status( void ) |
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170 | { |
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171 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS ); |
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172 | } |
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173 | |
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174 | static inline void _Nios2_Set_ctlreg_status( uint32_t value ) |
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175 | { |
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176 | __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (int) value ); |
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177 | } |
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178 | |
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179 | static inline uint32_t _Nios2_Get_ctlreg_estatus( void ) |
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180 | { |
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181 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS ); |
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182 | } |
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183 | |
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184 | static inline void _Nios2_Set_ctlreg_estatus( uint32_t value ) |
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185 | { |
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186 | __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (int) value ); |
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187 | } |
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188 | |
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189 | static inline uint32_t _Nios2_Get_ctlreg_bstatus( void ) |
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190 | { |
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191 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS ); |
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192 | } |
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193 | |
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194 | static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value ) |
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195 | { |
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196 | __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (int) value ); |
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197 | } |
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198 | |
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199 | static inline uint32_t _Nios2_Get_ctlreg_ienable( void ) |
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200 | { |
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201 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE ); |
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202 | } |
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203 | |
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204 | static inline void _Nios2_Set_ctlreg_ienable( uint32_t value ) |
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205 | { |
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206 | __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (int) value ); |
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207 | } |
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208 | |
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209 | static inline uint32_t _Nios2_Get_ctlreg_ipending( void ) |
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210 | { |
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211 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING ); |
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212 | } |
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213 | |
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214 | static inline uint32_t _Nios2_Get_ctlreg_cpuid( void ) |
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215 | { |
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216 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID ); |
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217 | } |
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218 | |
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219 | static inline uint32_t _Nios2_Get_ctlreg_exception( void ) |
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220 | { |
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221 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION ); |
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222 | } |
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223 | |
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224 | static inline uint32_t _Nios2_Get_ctlreg_pteaddr( void ) |
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225 | { |
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226 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR ); |
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227 | } |
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228 | |
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229 | static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value ) |
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230 | { |
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231 | __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (int) value ); |
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232 | } |
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233 | |
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234 | static inline uint32_t _Nios2_Get_ctlreg_tlbacc( void ) |
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235 | { |
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236 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC ); |
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237 | } |
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238 | |
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239 | static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value ) |
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240 | { |
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241 | __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (int) value ); |
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242 | } |
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243 | |
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244 | static inline uint32_t _Nios2_Get_ctlreg_tlbmisc( void ) |
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245 | { |
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246 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC ); |
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247 | } |
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248 | |
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249 | static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value ) |
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250 | { |
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251 | __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (int) value ); |
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252 | } |
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253 | |
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254 | static inline uint32_t _Nios2_Get_ctlreg_badaddr( void ) |
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255 | { |
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256 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR ); |
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257 | } |
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258 | |
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259 | static inline uint32_t _Nios2_Get_ctlreg_config( void ) |
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260 | { |
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261 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG ); |
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262 | } |
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263 | |
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264 | static inline void _Nios2_Set_ctlreg_config( uint32_t value ) |
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265 | { |
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266 | __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (int) value ); |
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267 | } |
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268 | |
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269 | static inline uint32_t _Nios2_Get_ctlreg_mpubase( void ) |
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270 | { |
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271 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE ); |
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272 | } |
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273 | |
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274 | static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value ) |
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275 | { |
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276 | __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (int) value ); |
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277 | } |
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278 | |
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279 | static inline uint32_t _Nios2_Get_ctlreg_mpuacc( void ) |
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280 | { |
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281 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC ); |
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282 | } |
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283 | |
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284 | static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value ) |
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285 | { |
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286 | __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (int) value ); |
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287 | } |
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288 | |
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289 | static inline uint32_t _Nios2_ISR_Get_status_mask( void ) |
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290 | { |
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291 | return (uint32_t) &_Nios2_ISR_Status_mask [0]; |
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292 | } |
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293 | |
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294 | static inline uint32_t _Nios2_ISR_Get_status_bits( void ) |
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295 | { |
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296 | return (uint32_t) &_Nios2_ISR_Status_bits [0]; |
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297 | } |
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298 | |
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299 | static inline bool _Nios2_Has_internal_interrupt_controller( void ) |
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300 | { |
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301 | return _Nios2_ISR_Get_status_mask() == NIOS2_ISR_STATUS_MASK_IIC; |
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302 | } |
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303 | |
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304 | uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status ); |
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305 | |
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306 | #ifdef __cplusplus |
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307 | } |
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308 | #endif /* __cplusplus */ |
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309 | |
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310 | #endif /* !ASM */ |
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311 | |
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312 | #endif /* _RTEMS_SCORE_NIOS2_UTILITY_H */ |
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