source: rtems/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h @ 1c963169

4.115
Last change on this file since 1c963169 was 1c963169, checked in by Sebastian Huber <sebastian.huber@…>, on Sep 2, 2011 at 11:20:28 AM

2011-09-02 Sebastian Huber <sebastian.huber@…>

  • rtems/score/nios2-utility.h: Use the same values for defines used by Altera HAL.
  • Property mode set to 100644
File size: 8.7 KB
Line 
1/*
2 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Obere Lagerstr. 30
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 *
14 * $Id$
15 */
16
17#ifndef _RTEMS_SCORE_NIOS2_UTILITY_H
18#define _RTEMS_SCORE_NIOS2_UTILITY_H
19
20#define NIOS2_CTLREG_INDEX_STATUS 0
21#define NIOS2_CTLREG_INDEX_ESTATUS 1
22#define NIOS2_CTLREG_INDEX_BSTATUS 2
23#define NIOS2_CTLREG_INDEX_IENABLE 3
24#define NIOS2_CTLREG_INDEX_IPENDING 4
25#define NIOS2_CTLREG_INDEX_CPUID 5
26#define NIOS2_CTLREG_INDEX_EXCEPTION 7
27#define NIOS2_CTLREG_INDEX_PTEADDR 8
28#define NIOS2_CTLREG_INDEX_TLBACC 9
29#define NIOS2_CTLREG_INDEX_TLBMISC 10
30#define NIOS2_CTLREG_INDEX_BADADDR 12
31#define NIOS2_CTLREG_INDEX_CONFIG 13
32#define NIOS2_CTLREG_INDEX_MPUBASE 14
33#define NIOS2_CTLREG_INDEX_MPUACC 15
34
35#define NIOS2_CONTEXT_OFFSET_R16 0
36#define NIOS2_CONTEXT_OFFSET_R17 4
37#define NIOS2_CONTEXT_OFFSET_R18 8
38#define NIOS2_CONTEXT_OFFSET_R19 12
39#define NIOS2_CONTEXT_OFFSET_R20 16
40#define NIOS2_CONTEXT_OFFSET_R21 20
41#define NIOS2_CONTEXT_OFFSET_R22 24
42#define NIOS2_CONTEXT_OFFSET_R23 28
43#define NIOS2_CONTEXT_OFFSET_FP 32
44#define NIOS2_CONTEXT_OFFSET_STATUS 36
45#define NIOS2_CONTEXT_OFFSET_SP 40
46#define NIOS2_CONTEXT_OFFSET_RA 44
47#define NIOS2_CONTEXT_OFFSET_TDD 48
48
49#define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe
50#define NIOS2_ISR_STATUS_BITS_IIC 0x00000000
51
52#define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f
53#define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0
54
55#define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff
56#define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000
57
58#define NIOS2_STATUS_RSIE (1 << 23)
59#define NIOS2_STATUS_NMI (1 << 22)
60#define NIOS2_STATUS_PRS_OFFSET 16
61#define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET)
62#define NIOS2_STATUS_CRS_OFFSET 10
63#define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET)
64#define NIOS2_STATUS_IL_OFFSET 4
65#define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET)
66#define NIOS2_STATUS_IH (1 << 3)
67#define NIOS2_STATUS_EH (1 << 2)
68#define NIOS2_STATUS_U (1 << 1)
69#define NIOS2_STATUS_PIE (1 << 0)
70
71#define NIOS2_EXCEPTION_CAUSE_OFFSET 2
72#define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET)
73
74#define NIOS2_PTEADDR_PTBASE_OFFSET 22
75#define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET)
76#define NIOS2_PTEADDR_VPN_OFFSET 2
77#define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET)
78
79#define NIOS2_TLBACC_IG_OFFSET 25
80#define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET)
81#define NIOS2_TLBACC_C (1 << 24)
82#define NIOS2_TLBACC_R (1 << 23)
83#define NIOS2_TLBACC_W (1 << 22)
84#define NIOS2_TLBACC_X (1 << 21)
85#define NIOS2_TLBACC_G (1 << 20)
86#define NIOS2_TLBACC_PFN_OFFSET 2
87#define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET)
88
89#define NIOS2_TLBMISC_WAY_OFFSET 20
90#define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET)
91#define NIOS2_TLBMISC_RD (1 << 19)
92#define NIOS2_TLBMISC_WE (1 << 18)
93#define NIOS2_TLBMISC_PID_OFFSET 5
94#define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET)
95#define NIOS2_TLBMISC_DBL (1 << 3)
96#define NIOS2_TLBMISC_BAD (1 << 2)
97#define NIOS2_TLBMISC_PERM (1 << 1)
98#define NIOS2_TLBMISC_D (1 << 0)
99
100#define NIOS2_CONFIG_ANI (1 << 1)
101#define NIOS2_CONFIG_PE (1 << 0)
102
103#define NIOS2_MPUBASE_BASE_OFFSET 5
104#define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET)
105#define NIOS2_MPUBASE_INDEX_OFFSET 1
106
107/* Avoid redefines with Altera HAL */
108#define NIOS2_MPUBASE_INDEX_MASK (0x0000003e)
109
110#define NIOS2_MPUBASE_D (1 << 0)
111
112#define NIOS2_MPUACC_MASK_OFFSET 6
113
114/* Avoid redefines with Altera HAL */
115#define NIOS2_MPUACC_MASK_MASK (0x7fffffc0)
116
117#define NIOS2_MPUACC_LIMIT_OFFSET 6
118
119/* Avoid redefines with Altera HAL */
120#define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0)
121
122#define NIOS2_MPUACC_C (1 << 5)
123#define NIOS2_MPUACC_PERM_OFFSET 2
124
125/* Avoid redefines with Altera HAL */
126#define NIOS2_MPUACC_PERM_MASK (0x0000001c)
127
128#define NIOS2_MPUACC_RD (1 << 1)
129#define NIOS2_MPUACC_WR (1 << 0)
130
131#ifndef ASM
132
133#include <stdint.h>
134#include <stdbool.h>
135
136#ifdef __cplusplus
137extern "C" {
138#endif /* __cplusplus */
139
140/**
141 * @brief Nios II specific thread dispatch disabled indicator.
142 *
143 * This global variable is used by the interrupt dispatch support for the
144 * external interrupt controller (EIC) with shadow registers.  This makes it
145 * possible to do the thread dispatch after an interrupt without disabled
146 * interrupts and thus probably reduce the maximum interrupt latency.  Its
147 * purpose is to prevent unbounded stack usage of the interrupted thread.
148 */
149extern uint32_t _Nios2_Thread_dispatch_disabled;
150
151/**
152 * @brief This global symbol specifies the status register mask used to disable
153 * interrupts.
154 *
155 * The board support package must provide a global symbol with this name to
156 * specifiy the status register mask used in _CPU_ISR_Disable().
157 */
158extern char _Nios2_ISR_Status_mask [];
159
160/**
161 * @brief This symbol specifies the status register bits used to disable
162 * interrupts.
163 *
164 * The board support package must provide a global symbol with this name to
165 * specifiy the status register bits used in _CPU_ISR_Disable().
166 */
167extern char _Nios2_ISR_Status_bits [];
168
169static inline uint32_t _Nios2_Get_ctlreg_status( void )
170{
171  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS );
172}
173
174static inline void _Nios2_Set_ctlreg_status( uint32_t value )
175{
176  __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (int) value );
177}
178
179static inline uint32_t _Nios2_Get_ctlreg_estatus( void )
180{
181  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS );
182}
183
184static inline void _Nios2_Set_ctlreg_estatus( uint32_t value )
185{
186  __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (int) value );
187}
188
189static inline uint32_t _Nios2_Get_ctlreg_bstatus( void )
190{
191  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS );
192}
193
194static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value )
195{
196  __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (int) value );
197}
198
199static inline uint32_t _Nios2_Get_ctlreg_ienable( void )
200{
201  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE );
202}
203
204static inline void _Nios2_Set_ctlreg_ienable( uint32_t value )
205{
206  __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (int) value );
207}
208
209static inline uint32_t _Nios2_Get_ctlreg_ipending( void )
210{
211  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING );
212}
213
214static inline uint32_t _Nios2_Get_ctlreg_cpuid( void )
215{
216  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID );
217}
218
219static inline uint32_t _Nios2_Get_ctlreg_exception( void )
220{
221  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION );
222}
223
224static inline uint32_t _Nios2_Get_ctlreg_pteaddr( void )
225{
226  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR );
227}
228
229static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value )
230{
231  __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (int) value );
232}
233
234static inline uint32_t _Nios2_Get_ctlreg_tlbacc( void )
235{
236  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC );
237}
238
239static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value )
240{
241  __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (int) value );
242}
243
244static inline uint32_t _Nios2_Get_ctlreg_tlbmisc( void )
245{
246  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC );
247}
248
249static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value )
250{
251  __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (int) value );
252}
253
254static inline uint32_t _Nios2_Get_ctlreg_badaddr( void )
255{
256  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR );
257}
258
259static inline uint32_t _Nios2_Get_ctlreg_config( void )
260{
261  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG );
262}
263
264static inline void _Nios2_Set_ctlreg_config( uint32_t value )
265{
266  __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (int) value );
267}
268
269static inline uint32_t _Nios2_Get_ctlreg_mpubase( void )
270{
271  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE );
272}
273
274static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value )
275{
276  __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (int) value );
277}
278
279static inline uint32_t _Nios2_Get_ctlreg_mpuacc( void )
280{
281  return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC );
282}
283
284static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value )
285{
286  __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (int) value );
287}
288
289static inline uint32_t _Nios2_Get_ISR_status_mask( void )
290{
291  return (uint32_t) &_Nios2_ISR_Status_mask [0];
292}
293
294static inline uint32_t _Nios2_Get_ISR_status_bits( void )
295{
296  return (uint32_t) &_Nios2_ISR_Status_bits [0];
297}
298
299static inline bool _Nios2_Has_internal_interrupt_controller( void )
300{
301  return _Nios2_Get_ISR_status_mask() == NIOS2_ISR_STATUS_MASK_IIC;
302}
303
304uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status );
305
306#ifdef __cplusplus
307}
308#endif /* __cplusplus */
309
310#endif /* !ASM */
311
312#endif /* _RTEMS_SCORE_NIOS2_UTILITY_H */
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