1 | /** |
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2 | * @file |
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3 | * |
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4 | * @brief NIOS II Utility |
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5 | */ |
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6 | /* |
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7 | * Copyright (c) 2011 embedded brains GmbH. All rights reserved. |
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8 | * |
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9 | * embedded brains GmbH |
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10 | * Obere Lagerstr. 30 |
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11 | * 82178 Puchheim |
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12 | * Germany |
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13 | * <rtems@embedded-brains.de> |
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14 | * |
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15 | * The license and distribution terms for this file may be |
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16 | * found in the file LICENSE in this distribution or at |
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17 | * http://www.rtems.com/license/LICENSE. |
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18 | */ |
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19 | |
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20 | #ifndef _RTEMS_SCORE_NIOS2_UTILITY_H |
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21 | #define _RTEMS_SCORE_NIOS2_UTILITY_H |
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22 | |
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23 | #define NIOS2_CTLREG_INDEX_STATUS 0 |
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24 | #define NIOS2_CTLREG_INDEX_ESTATUS 1 |
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25 | #define NIOS2_CTLREG_INDEX_BSTATUS 2 |
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26 | #define NIOS2_CTLREG_INDEX_IENABLE 3 |
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27 | #define NIOS2_CTLREG_INDEX_IPENDING 4 |
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28 | #define NIOS2_CTLREG_INDEX_CPUID 5 |
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29 | #define NIOS2_CTLREG_INDEX_EXCEPTION 7 |
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30 | #define NIOS2_CTLREG_INDEX_PTEADDR 8 |
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31 | #define NIOS2_CTLREG_INDEX_TLBACC 9 |
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32 | #define NIOS2_CTLREG_INDEX_TLBMISC 10 |
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33 | #define NIOS2_CTLREG_INDEX_BADADDR 12 |
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34 | #define NIOS2_CTLREG_INDEX_CONFIG 13 |
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35 | #define NIOS2_CTLREG_INDEX_MPUBASE 14 |
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36 | #define NIOS2_CTLREG_INDEX_MPUACC 15 |
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37 | |
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38 | #define NIOS2_CONTEXT_OFFSET_R16 0 |
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39 | #define NIOS2_CONTEXT_OFFSET_R17 4 |
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40 | #define NIOS2_CONTEXT_OFFSET_R18 8 |
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41 | #define NIOS2_CONTEXT_OFFSET_R19 12 |
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42 | #define NIOS2_CONTEXT_OFFSET_R20 16 |
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43 | #define NIOS2_CONTEXT_OFFSET_R21 20 |
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44 | #define NIOS2_CONTEXT_OFFSET_R22 24 |
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45 | #define NIOS2_CONTEXT_OFFSET_R23 28 |
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46 | #define NIOS2_CONTEXT_OFFSET_FP 32 |
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47 | #define NIOS2_CONTEXT_OFFSET_STATUS 36 |
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48 | #define NIOS2_CONTEXT_OFFSET_SP 40 |
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49 | #define NIOS2_CONTEXT_OFFSET_RA 44 |
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50 | #define NIOS2_CONTEXT_OFFSET_THREAD_DISPATCH_DISABLED 48 |
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51 | #define NIOS2_CONTEXT_OFFSET_STACK_MPUBASE 52 |
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52 | #define NIOS2_CONTEXT_OFFSET_STACK_MPUACC 56 |
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53 | |
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54 | #define NIOS2_ISR_STATUS_MASK_IIC 0xfffffffe |
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55 | #define NIOS2_ISR_STATUS_BITS_IIC 0x00000000 |
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56 | |
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57 | #define NIOS2_ISR_STATUS_MASK_EIC_IL 0xfffffc0f |
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58 | #define NIOS2_ISR_STATUS_BITS_EIC_IL 0x000003f0 |
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59 | |
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60 | #define NIOS2_ISR_STATUS_MASK_EIC_RSIE 0xf7ffffff |
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61 | #define NIOS2_ISR_STATUS_BITS_EIC_RSIE 0x00000000 |
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62 | |
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63 | #define NIOS2_STATUS_RSIE (1 << 23) |
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64 | #define NIOS2_STATUS_NMI (1 << 22) |
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65 | #define NIOS2_STATUS_PRS_OFFSET 16 |
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66 | #define NIOS2_STATUS_PRS_MASK (0x3f << NIOS2_STATUS_PRS_OFFSET) |
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67 | #define NIOS2_STATUS_CRS_OFFSET 10 |
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68 | #define NIOS2_STATUS_CRS_MASK (0x3f << NIOS2_STATUS_CRS_OFFSET) |
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69 | #define NIOS2_STATUS_IL_OFFSET 4 |
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70 | #define NIOS2_STATUS_IL_MASK (0x3f << NIOS2_STATUS_IL_OFFSET) |
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71 | #define NIOS2_STATUS_IH (1 << 3) |
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72 | #define NIOS2_STATUS_EH (1 << 2) |
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73 | #define NIOS2_STATUS_U (1 << 1) |
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74 | #define NIOS2_STATUS_PIE (1 << 0) |
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75 | |
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76 | #define NIOS2_EXCEPTION_CAUSE_OFFSET 2 |
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77 | #define NIOS2_EXCEPTION_CAUSE_MASK (0x1f << NIOS2_EXCEPTION_CAUSE_OFFSET) |
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78 | |
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79 | #define NIOS2_PTEADDR_PTBASE_OFFSET 22 |
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80 | #define NIOS2_PTEADDR_PTBASE_MASK (0x3ff << NIOS2_PTEADDR_PTBASE_OFFSET) |
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81 | #define NIOS2_PTEADDR_VPN_OFFSET 2 |
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82 | #define NIOS2_PTEADDR_VPN_MASK (0xfffff << NIOS2_PTEADDR_VPN_OFFSET) |
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83 | |
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84 | #define NIOS2_TLBACC_IG_OFFSET 25 |
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85 | #define NIOS2_TLBACC_IG_MASK (0x3ff << NIOS2_TLBACC_IG_OFFSET) |
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86 | #define NIOS2_TLBACC_C (1 << 24) |
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87 | #define NIOS2_TLBACC_R (1 << 23) |
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88 | #define NIOS2_TLBACC_W (1 << 22) |
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89 | #define NIOS2_TLBACC_X (1 << 21) |
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90 | #define NIOS2_TLBACC_G (1 << 20) |
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91 | #define NIOS2_TLBACC_PFN_OFFSET 2 |
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92 | #define NIOS2_TLBACC_PFN_MASK (0xfffff << NIOS2_TLBACC_PFN_OFFSET) |
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93 | |
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94 | #define NIOS2_TLBMISC_WAY_OFFSET 20 |
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95 | #define NIOS2_TLBMISC_WAY_MASK (0xf << NIOS2_TLBMISC_WAY_OFFSET) |
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96 | #define NIOS2_TLBMISC_RD (1 << 19) |
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97 | #define NIOS2_TLBMISC_WE (1 << 18) |
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98 | #define NIOS2_TLBMISC_PID_OFFSET 5 |
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99 | #define NIOS2_TLBMISC_PID_MASK (0x3fff << NIOS2_TLBMISC_PID_OFFSET) |
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100 | #define NIOS2_TLBMISC_DBL (1 << 3) |
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101 | #define NIOS2_TLBMISC_BAD (1 << 2) |
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102 | #define NIOS2_TLBMISC_PERM (1 << 1) |
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103 | #define NIOS2_TLBMISC_D (1 << 0) |
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104 | |
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105 | #define NIOS2_CONFIG_ANI (1 << 1) |
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106 | #define NIOS2_CONFIG_PE (1 << 0) |
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107 | |
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108 | #define NIOS2_MPUBASE_BASE_OFFSET 6 |
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109 | #define NIOS2_MPUBASE_BASE_MASK (0x1ffffff << NIOS2_MPUBASE_BASE_OFFSET) |
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110 | #define NIOS2_MPUBASE_INDEX_OFFSET 1 |
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111 | |
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112 | /* Avoid redefines with Altera HAL */ |
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113 | #define NIOS2_MPUBASE_INDEX_MASK (0x0000003e) |
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114 | |
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115 | #define NIOS2_MPUBASE_D (1 << 0) |
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116 | |
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117 | #define NIOS2_MPUACC_MASK_OFFSET 6 |
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118 | |
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119 | /* Avoid redefines with Altera HAL */ |
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120 | #define NIOS2_MPUACC_MASK_MASK (0x7fffffc0) |
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121 | |
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122 | #define NIOS2_MPUACC_LIMIT_OFFSET 6 |
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123 | |
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124 | /* Avoid redefines with Altera HAL */ |
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125 | #define NIOS2_MPUACC_LIMIT_MASK (0xffffffc0) |
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126 | |
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127 | #define NIOS2_MPUACC_C (1 << 5) |
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128 | #define NIOS2_MPUACC_PERM_OFFSET 2 |
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129 | |
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130 | /* Avoid redefines with Altera HAL */ |
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131 | #define NIOS2_MPUACC_PERM_MASK (0x0000001c) |
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132 | |
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133 | #define NIOS2_MPUACC_RD (1 << 1) |
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134 | #define NIOS2_MPUACC_WR (1 << 0) |
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135 | |
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136 | #ifndef ASM |
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137 | |
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138 | #include <stddef.h> |
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139 | #include <stdint.h> |
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140 | #include <stdbool.h> |
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141 | |
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142 | #ifdef __cplusplus |
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143 | extern "C" { |
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144 | #endif /* __cplusplus */ |
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145 | |
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146 | /** |
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147 | * @brief Nios II specific thread dispatch disabled indicator. |
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148 | * |
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149 | * This global variable is used by the interrupt dispatch support for the |
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150 | * external interrupt controller (EIC) with shadow registers. This makes it |
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151 | * possible to do the thread dispatch after an interrupt without disabled |
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152 | * interrupts and thus probably reduce the maximum interrupt latency. Its |
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153 | * purpose is to prevent unbounded stack usage of the interrupted thread. |
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154 | */ |
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155 | extern uint32_t _Nios2_Thread_dispatch_disabled; |
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156 | |
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157 | /** |
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158 | * @brief This global symbol specifies the status register mask used to disable |
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159 | * interrupts. |
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160 | * |
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161 | * The board support package must provide a global symbol with this name to |
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162 | * specifiy the status register mask used in _CPU_ISR_Disable(). |
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163 | */ |
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164 | extern char _Nios2_ISR_Status_mask []; |
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165 | |
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166 | /** |
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167 | * @brief This symbol specifies the status register bits used to disable |
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168 | * interrupts. |
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169 | * |
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170 | * The board support package must provide a global symbol with this name to |
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171 | * specifiy the status register bits used in _CPU_ISR_Disable(). |
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172 | */ |
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173 | extern char _Nios2_ISR_Status_bits []; |
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174 | |
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175 | static inline void _Nios2_Flush_pipeline( void ) |
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176 | { |
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177 | __asm__ volatile ("flushp"); |
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178 | } |
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179 | |
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180 | static inline uint32_t _Nios2_Get_ctlreg_status( void ) |
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181 | { |
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182 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_STATUS ); |
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183 | } |
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184 | |
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185 | static inline void _Nios2_Set_ctlreg_status( uint32_t value ) |
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186 | { |
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187 | __builtin_wrctl( NIOS2_CTLREG_INDEX_STATUS, (int) value ); |
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188 | } |
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189 | |
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190 | static inline uint32_t _Nios2_Get_ctlreg_estatus( void ) |
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191 | { |
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192 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_ESTATUS ); |
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193 | } |
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194 | |
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195 | static inline void _Nios2_Set_ctlreg_estatus( uint32_t value ) |
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196 | { |
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197 | __builtin_wrctl( NIOS2_CTLREG_INDEX_ESTATUS, (int) value ); |
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198 | } |
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199 | |
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200 | static inline uint32_t _Nios2_Get_ctlreg_bstatus( void ) |
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201 | { |
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202 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BSTATUS ); |
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203 | } |
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204 | |
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205 | static inline void _Nios2_Set_ctlreg_bstatus( uint32_t value ) |
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206 | { |
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207 | __builtin_wrctl( NIOS2_CTLREG_INDEX_BSTATUS, (int) value ); |
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208 | } |
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209 | |
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210 | static inline uint32_t _Nios2_Get_ctlreg_ienable( void ) |
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211 | { |
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212 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IENABLE ); |
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213 | } |
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214 | |
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215 | static inline void _Nios2_Set_ctlreg_ienable( uint32_t value ) |
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216 | { |
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217 | __builtin_wrctl( NIOS2_CTLREG_INDEX_IENABLE, (int) value ); |
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218 | } |
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219 | |
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220 | static inline uint32_t _Nios2_Get_ctlreg_ipending( void ) |
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221 | { |
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222 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_IPENDING ); |
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223 | } |
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224 | |
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225 | static inline uint32_t _Nios2_Get_ctlreg_cpuid( void ) |
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226 | { |
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227 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CPUID ); |
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228 | } |
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229 | |
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230 | static inline uint32_t _Nios2_Get_ctlreg_exception( void ) |
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231 | { |
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232 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_EXCEPTION ); |
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233 | } |
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234 | |
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235 | static inline uint32_t _Nios2_Get_ctlreg_pteaddr( void ) |
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236 | { |
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237 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_PTEADDR ); |
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238 | } |
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239 | |
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240 | static inline void _Nios2_Set_ctlreg_pteaddr( uint32_t value ) |
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241 | { |
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242 | __builtin_wrctl( NIOS2_CTLREG_INDEX_PTEADDR, (int) value ); |
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243 | } |
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244 | |
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245 | static inline uint32_t _Nios2_Get_ctlreg_tlbacc( void ) |
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246 | { |
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247 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBACC ); |
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248 | } |
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249 | |
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250 | static inline void _Nios2_Set_ctlreg_tlbacc( uint32_t value ) |
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251 | { |
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252 | __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBACC, (int) value ); |
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253 | } |
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254 | |
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255 | static inline uint32_t _Nios2_Get_ctlreg_tlbmisc( void ) |
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256 | { |
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257 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_TLBMISC ); |
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258 | } |
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259 | |
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260 | static inline void _Nios2_Set_ctlreg_tlbmisc( uint32_t value ) |
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261 | { |
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262 | __builtin_wrctl( NIOS2_CTLREG_INDEX_TLBMISC, (int) value ); |
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263 | } |
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264 | |
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265 | static inline uint32_t _Nios2_Get_ctlreg_badaddr( void ) |
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266 | { |
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267 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_BADADDR ); |
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268 | } |
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269 | |
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270 | static inline uint32_t _Nios2_Get_ctlreg_config( void ) |
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271 | { |
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272 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_CONFIG ); |
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273 | } |
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274 | |
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275 | static inline void _Nios2_Set_ctlreg_config( uint32_t value ) |
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276 | { |
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277 | __builtin_wrctl( NIOS2_CTLREG_INDEX_CONFIG, (int) value ); |
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278 | } |
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279 | |
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280 | static inline uint32_t _Nios2_Get_ctlreg_mpubase( void ) |
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281 | { |
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282 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUBASE ); |
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283 | } |
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284 | |
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285 | static inline void _Nios2_Set_ctlreg_mpubase( uint32_t value ) |
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286 | { |
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287 | __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUBASE, (int) value ); |
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288 | } |
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289 | |
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290 | static inline uint32_t _Nios2_Get_ctlreg_mpuacc( void ) |
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291 | { |
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292 | return (uint32_t) __builtin_rdctl( NIOS2_CTLREG_INDEX_MPUACC ); |
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293 | } |
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294 | |
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295 | static inline void _Nios2_Set_ctlreg_mpuacc( uint32_t value ) |
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296 | { |
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297 | __builtin_wrctl( NIOS2_CTLREG_INDEX_MPUACC, (int) value ); |
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298 | } |
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299 | |
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300 | static inline uint32_t _Nios2_ISR_Get_status_mask( void ) |
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301 | { |
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302 | return (uint32_t) &_Nios2_ISR_Status_mask [0]; |
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303 | } |
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304 | |
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305 | static inline uint32_t _Nios2_ISR_Get_status_bits( void ) |
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306 | { |
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307 | return (uint32_t) &_Nios2_ISR_Status_bits [0]; |
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308 | } |
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309 | |
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310 | static inline bool _Nios2_Has_internal_interrupt_controller( void ) |
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311 | { |
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312 | return _Nios2_ISR_Get_status_mask() == NIOS2_ISR_STATUS_MASK_IIC; |
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313 | } |
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314 | |
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315 | uint32_t _Nios2_ISR_Set_level( uint32_t new_level, uint32_t status ); |
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316 | |
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317 | typedef struct { |
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318 | int data_address_width; |
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319 | int instruction_address_width; |
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320 | int data_region_size_log2; |
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321 | int instruction_region_size_log2; |
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322 | int data_region_count; |
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323 | int instruction_region_count; |
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324 | int data_index_for_stack_protection; |
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325 | bool region_uses_limit; |
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326 | bool enable_data_cache_for_stack; |
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327 | } Nios2_MPU_Configuration; |
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328 | |
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329 | void _Nios2_MPU_Set_configuration( const Nios2_MPU_Configuration *config ); |
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330 | |
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331 | const Nios2_MPU_Configuration *_Nios2_MPU_Get_configuration( void ); |
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332 | |
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333 | typedef enum { |
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334 | NIOS2_MPU_INST_PERM_SVR_NONE_USER_NONE = 0, |
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335 | NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, |
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336 | NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_EXECUTE, |
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337 | NIOS2_MPU_DATA_PERM_SVR_NONE_USER_NONE = 0, |
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338 | NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, |
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339 | NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_READONLY, |
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340 | NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE = 4, |
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341 | NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READONLY, |
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342 | NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_READWRITE |
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343 | } Nios2_MPU_Region_permissions; |
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344 | |
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345 | typedef struct { |
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346 | int index; |
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347 | const void *base; |
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348 | const void *end; |
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349 | Nios2_MPU_Region_permissions perm; |
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350 | bool data; |
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351 | bool cacheable; |
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352 | bool read; |
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353 | bool write; |
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354 | } Nios2_MPU_Region_descriptor; |
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355 | |
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356 | #define NIOS2_MPU_REGION_DESC_INST( index, base, end ) \ |
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357 | { \ |
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358 | (index), (base), (end), NIOS2_MPU_INST_PERM_SVR_EXECUTE_USER_NONE, \ |
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359 | false, false, false, true \ |
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360 | } |
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361 | |
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362 | #define NIOS2_MPU_REGION_DESC_DATA_RO( index, base, end ) \ |
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363 | { \ |
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364 | (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READONLY_USER_NONE, \ |
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365 | true, true, false, true \ |
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366 | } |
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367 | |
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368 | #define NIOS2_MPU_REGION_DESC_DATA_RW( index, base, end ) \ |
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369 | { \ |
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370 | (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ |
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371 | true, true, false, true \ |
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372 | } |
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373 | |
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374 | #define NIOS2_MPU_REGION_DESC_DATA_IO( index, base, end ) \ |
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375 | { \ |
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376 | (index), (base), (end), NIOS2_MPU_DATA_PERM_SVR_READWRITE_USER_NONE, \ |
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377 | true, false, false, true \ |
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378 | } |
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379 | |
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380 | static inline int _Nios2_MPU_Get_region_count( |
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381 | const Nios2_MPU_Configuration *config, |
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382 | bool data |
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383 | ) |
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384 | { |
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385 | return data ? |
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386 | config->data_region_count |
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387 | : config->instruction_region_count; |
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388 | } |
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389 | |
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390 | static inline bool _Nios2_MPU_Is_valid_index( |
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391 | const Nios2_MPU_Configuration *config, |
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392 | int index, |
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393 | bool data |
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394 | ) |
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395 | { |
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396 | return 0 <= index |
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397 | && index < _Nios2_MPU_Get_region_count( config, data ); |
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398 | } |
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399 | |
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400 | bool _Nios2_MPU_Setup_region_registers( |
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401 | const Nios2_MPU_Configuration *config, |
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402 | const Nios2_MPU_Region_descriptor *desc, |
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403 | uint32_t *mpubase, |
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404 | uint32_t *mpuacc |
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405 | ); |
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406 | |
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407 | bool _Nios2_MPU_Get_region_descriptor( |
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408 | const Nios2_MPU_Configuration *config, |
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409 | int index, |
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410 | bool data, |
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411 | Nios2_MPU_Region_descriptor *desc |
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412 | ); |
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413 | |
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414 | /** |
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415 | * @brief Searches the region table part for a disabled region. |
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416 | * |
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417 | * The table will be searched between indices @a begin and @a end. The @a end |
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418 | * index is not part of the search range. If @a end is negative, then the |
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419 | * region count will be used. Thus a @a begin of 0 and a @a end of -1 will |
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420 | * specify the complete table. |
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421 | * |
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422 | * @retval -1 No disabled region is available. |
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423 | * @retval other Index of disabled region. |
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424 | */ |
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425 | int _Nios2_MPU_Get_disabled_region_index( |
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426 | const Nios2_MPU_Configuration *config, |
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427 | bool data, |
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428 | int begin, |
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429 | int end |
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430 | ); |
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431 | |
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432 | /** |
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433 | * @brief Adds a region according to region descriptor @a desc. |
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434 | * |
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435 | * If @a force is true, then an enabled region will be overwritten. |
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436 | * |
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437 | * @retval true Successful operation. |
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438 | * @retval false Invalid region descriptor or region already in use. |
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439 | */ |
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440 | bool _Nios2_MPU_Add_region( |
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441 | const Nios2_MPU_Configuration *config, |
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442 | const Nios2_MPU_Region_descriptor *desc, |
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443 | bool force |
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444 | ); |
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445 | |
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446 | static inline void _Nios2_MPU_Get_region_registers( |
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447 | int index, |
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448 | bool data, |
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449 | uint32_t *mpubase, |
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450 | uint32_t *mpuacc |
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451 | ) |
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452 | { |
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453 | uint32_t base = (uint32_t) |
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454 | (((index << NIOS2_MPUBASE_INDEX_OFFSET) & NIOS2_MPUBASE_INDEX_MASK) |
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455 | | (data ? NIOS2_MPUBASE_D : 0)); |
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456 | |
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457 | _Nios2_Set_ctlreg_mpubase( base ); |
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458 | _Nios2_Set_ctlreg_mpuacc( NIOS2_MPUACC_RD ); |
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459 | _Nios2_Flush_pipeline(); |
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460 | *mpubase = _Nios2_Get_ctlreg_mpubase() | base; |
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461 | *mpuacc = _Nios2_Get_ctlreg_mpuacc(); |
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462 | } |
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463 | |
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464 | static inline void _Nios2_MPU_Set_region_registers( |
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465 | uint32_t mpubase, |
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466 | uint32_t mpuacc |
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467 | ) |
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468 | { |
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469 | _Nios2_Set_ctlreg_mpubase( mpubase ); |
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470 | _Nios2_Set_ctlreg_mpuacc( mpuacc ); |
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471 | _Nios2_Flush_pipeline(); |
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472 | } |
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473 | |
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474 | static inline void _Nios2_MPU_Enable( void ) |
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475 | { |
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476 | uint32_t config = _Nios2_Get_ctlreg_config(); |
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477 | |
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478 | _Nios2_Set_ctlreg_config( config | NIOS2_CONFIG_PE ); |
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479 | } |
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480 | |
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481 | static inline uint32_t _Nios2_MPU_Disable( void ) |
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482 | { |
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483 | uint32_t config = _Nios2_Get_ctlreg_config(); |
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484 | uint32_t config_pe = NIOS2_CONFIG_PE; |
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485 | |
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486 | _Nios2_Set_ctlreg_config( config & ~config_pe ); |
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487 | |
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488 | return config; |
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489 | } |
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490 | |
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491 | static inline void _Nios2_MPU_Restore( uint32_t config ) |
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492 | { |
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493 | _Nios2_Set_ctlreg_config( config ); |
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494 | } |
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495 | |
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496 | uint32_t _Nios2_MPU_Disable_protected( void ); |
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497 | |
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498 | void _Nios2_MPU_Reset( const Nios2_MPU_Configuration *config ); |
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499 | |
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500 | #ifdef __cplusplus |
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501 | } |
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502 | #endif /* __cplusplus */ |
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503 | |
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504 | #else /* ASM */ |
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505 | |
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506 | .macro NIOS2_ASM_DISABLE_INTERRUPTS new_status, current_status |
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507 | movhi \new_status, %hiadj(_Nios2_ISR_Status_mask) |
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508 | addi \new_status, \new_status, %lo(_Nios2_ISR_Status_mask) |
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509 | and \new_status, \current_status, \new_status |
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510 | ori \new_status, \new_status, %lo(_Nios2_ISR_Status_bits) |
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511 | wrctl status, \new_status |
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512 | .endm |
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513 | |
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514 | #endif /* ASM */ |
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515 | |
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516 | #endif /* _RTEMS_SCORE_NIOS2_UTILITY_H */ |
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