source: rtems/cpukit/score/cpu/nios2/rtems/score/cpu.h @ f4786d8

4.104.114.84.95
Last change on this file since f4786d8 was f4786d8, checked in by Joel Sherrill <joel.sherrill@…>, on Aug 9, 2006 at 9:28:40 PM

2006-08-09 Kolja Waschk <waschk@…>

  • rtems/score/cpu.h, rtems/score/cpu_asm.h, rtems/score/nios2.h, rtems/score/types.h: New files.
  • Property mode set to 100644
File size: 45.3 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 * 
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*  COPYRIGHT (c) 1989-2004.
23 *  On-Line Applications Research Corporation (OAR).
24 *
25 *  The license and distribution terms for this file may be
26 *  found in the file LICENSE in this distribution or at
27 *  http://www.rtems.com/license/LICENSE.
28 *
29 *  $Id$
30 */
31
32#ifndef _RTEMS_SCORE_CPU_H
33#define _RTEMS_SCORE_CPU_H
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <rtems/score/nios2.h>            /* pick up machine definitions */
40#ifndef ASM
41#include <rtems/score/types.h>
42#endif
43
44/* conditional compilation parameters */
45
46/**
47 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
48 *
49 *  If TRUE, then they are inlined.
50 *  If FALSE, then a subroutine call is made.
51 *
52 *  This conditional is an example of the classic trade-off of size
53 *  versus speed.  Inlining the call (TRUE) typically increases the
54 *  size of RTEMS while speeding up the enabling of dispatching.
55 *
56 *  @note In general, the @ref _Thread_Dispatch_disable_level will
57 *  only be 0 or 1 unless you are in an interrupt handler and that
58 *  interrupt handler invokes the executive.]  When not inlined
59 *  something calls @ref _Thread_Enable_dispatch which in turns calls
60 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
61 *  one subroutine call is avoided entirely.
62 *
63 *  Port Specific Information:
64 *
65 *  XXX document implementation including references if appropriate
66 */
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/**
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 *
86 *  Port Specific Information:
87 *
88 *  XXX document implementation including references if appropriate
89 */
90#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
91
92/**
93 *  Does RTEMS manage a dedicated interrupt stack in software?
94 *
95 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
96 *  If FALSE, nothing is done.
97 *
98 *  If the CPU supports a dedicated interrupt stack in hardware,
99 *  then it is generally the responsibility of the BSP to allocate it
100 *  and set it up.
101 *
102 *  If the CPU does not support a dedicated interrupt stack, then
103 *  the porter has two options: (1) execute interrupts on the
104 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
105 *  interrupt stack.
106 *
107 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 *
115 *  Port Specific Information:
116 *
117 *  XXX document implementation including references if appropriate
118 */
119#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
120
121/**
122 *  Does this CPU have hardware support for a dedicated interrupt stack?
123 *
124 *  If TRUE, then it must be installed during initialization.
125 *  If FALSE, then no installation is performed.
126 *
127 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
128 *
129 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
130 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
131 *  possible that both are FALSE for a particular CPU.  Although it
132 *  is unclear what that would imply about the interrupt processing
133 *  procedure on that CPU.
134 *
135 *  Port Specific Information:
136 *
137 *  XXX document implementation including references if appropriate
138 */
139#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
140
141/**
142 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
143 *
144 *  If TRUE, then the memory is allocated during initialization.
145 *  If FALSE, then the memory is allocated during initialization.
146 *
147 *  This should be TRUE is @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
148 *  or @ref CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
149 *
150 *  Port Specific Information:
151 *
152 *  XXX document implementation including references if appropriate
153 */
154#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
155
156/**
157 *  Does the RTEMS invoke the user's ISR with the vector number and
158 *  a pointer to the saved interrupt frame (1) or just the vector
159 *  number (0)?
160 *
161 *  Port Specific Information:
162 *
163 *  XXX document implementation including references if appropriate
164 */
165#define CPU_ISR_PASSES_FRAME_POINTER 1
166
167/**
168 *  @def CPU_HARDWARE_FP
169 *
170 *  Does the CPU have hardware floating point?
171 *
172 *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is supported.
173 *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is ignored.
174 *
175 *  If there is a FP coprocessor such as the i387 or mc68881, then
176 *  the answer is TRUE.
177 *
178 *  It indicates whether or not this CPU model has FP support.  For
179 *  example, it would be possible to have an i386_nofp CPU model
180 *  which set this to false to indicate that you have an i386 without
181 *  an i387 and wish to leave floating point support out of RTEMS.
182 */
183
184/**
185 *  @def CPU_SOFTWARE_FP
186 *
187 *  Does the CPU have no hardware floating point and GCC provides a
188 *  software floating point implementation which must be context
189 *  switched?
190 *
191 *  This feature conditional is used to indicate whether or not there
192 *  is software implemented floating point that must be context
193 *  switched.  The determination of whether or not this applies
194 *  is very tool specific and the state saved/restored is also
195 *  compiler specific.
196 *
197 *  Port Specific Information:
198 *
199 *  XXX document implementation including references if appropriate
200 */
201#define CPU_HARDWARE_FP     FALSE
202#define CPU_SOFTWARE_FP     FALSE
203
204/**
205 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
206 *
207 *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is assumed.
208 *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is followed.
209 *
210 *  So far, the only CPUs in which this option has been used are the
211 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
212 *  gcc both implicitly used the floating point registers to perform
213 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
214 *  seen to allocate floating point local variables and touch the FPU
215 *  even when the flow through a subroutine (like vfprintf()) might
216 *  not use floating point formats.
217 *
218 *  If a function which you would not think utilize the FP unit DOES,
219 *  then one can not easily predict which tasks will use the FP hardware.
220 *  In this case, this option should be TRUE.
221 *
222 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
223 *
224 *  Port Specific Information:
225 *
226 *  XXX document implementation including references if appropriate
227 */
228#define CPU_ALL_TASKS_ARE_FP     FALSE
229
230/**
231 *  Should the IDLE task have a floating point context?
232 *
233 *  If TRUE, then the IDLE task is created as a @ref RTEMS_FLOATING_POINT task
234 *  and it has a floating point context which is switched in and out.
235 *  If FALSE, then the IDLE task does not have a floating point context.
236 *
237 *  Setting this to TRUE negatively impacts the time required to preempt
238 *  the IDLE task from an interrupt because the floating point context
239 *  must be saved as part of the preemption.
240 *
241 *  Port Specific Information:
242 *
243 *  XXX document implementation including references if appropriate
244 */
245#define CPU_IDLE_TASK_IS_FP      FALSE
246
247/**
248 *  Should the saving of the floating point registers be deferred
249 *  until a context switch is made to another different floating point
250 *  task?
251 *
252 *  If TRUE, then the floating point context will not be stored until
253 *  necessary.  It will remain in the floating point registers and not
254 *  disturned until another floating point task is switched to.
255 *
256 *  If FALSE, then the floating point context is saved when a floating
257 *  point task is switched out and restored when the next floating point
258 *  task is restored.  The state of the floating point registers between
259 *  those two operations is not specified.
260 *
261 *  If the floating point context does NOT have to be saved as part of
262 *  interrupt dispatching, then it should be safe to set this to TRUE.
263 *
264 *  Setting this flag to TRUE results in using a different algorithm
265 *  for deciding when to save and restore the floating point context.
266 *  The deferred FP switch algorithm minimizes the number of times
267 *  the FP context is saved and restored.  The FP context is not saved
268 *  until a context switch is made to another, different FP task.
269 *  Thus in a system with only one FP task, the FP context will never
270 *  be saved or restored.
271 *
272 *  Port Specific Information:
273 *
274 *  XXX document implementation including references if appropriate
275 */
276#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
277
278/**
279 *  Does this port provide a CPU dependent IDLE task implementation?
280 *
281 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
282 *  must be provided and is the default IDLE thread body instead of
283 *  @ref _CPU_Thread_Idle_body.
284 *
285 *  If FALSE, then use the generic IDLE thread body if the BSP does
286 *  not provide one.
287 *
288 *  This is intended to allow for supporting processors which have
289 *  a low power or idle mode.  When the IDLE thread is executed, then
290 *  the CPU can be powered down.
291 *
292 *  The order of precedence for selecting the IDLE thread body is:
293 *
294 *    -#  BSP provided
295 *    -#  CPU dependent (if provided)
296 *    -#  generic (if no BSP and no CPU dependent)
297 *
298 *  Port Specific Information:
299 *
300 *  XXX document implementation including references if appropriate
301 */
302#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
303
304/**
305 *  Does the stack grow up (toward higher addresses) or down
306 *  (toward lower addresses)?
307 *
308 *  If TRUE, then the grows upward.
309 *  If FALSE, then the grows toward smaller addresses.
310 *
311 *  Port Specific Information:
312 *
313 *  XXX document implementation including references if appropriate
314 */
315#define CPU_STACK_GROWS_UP               FALSE
316
317/**
318 *  The following is the variable attribute used to force alignment
319 *  of critical RTEMS structures.  On some processors it may make
320 *  sense to have these aligned on tighter boundaries than
321 *  the minimum requirements of the compiler in order to have as
322 *  much of the critical data area as possible in a cache line.
323 *
324 *  The placement of this macro in the declaration of the variables
325 *  is based on the syntactically requirements of the GNU C
326 *  "__attribute__" extension.  For example with GNU C, use
327 *  the following to force a structures to a 32 byte boundary.
328 *
329 *      __attribute__ ((aligned (32)))
330 *
331 *  @note Currently only the Priority Bit Map table uses this feature.
332 *        To benefit from using this, the data must be heavily
333 *        used so it will stay in the cache and used frequently enough
334 *        in the executive to justify turning this on.
335 *
336 *  Port Specific Information:
337 *
338 *  XXX document implementation including references if appropriate
339 */
340#define CPU_STRUCTURE_ALIGNMENT
341
342/**
343 *  @defgroup CPUEndian Processor Dependent Endianness Support
344 *
345 *  This group assists in issues related to processor endianness.
346 */
347
348/**
349 *  @ingroup CPUEndian
350 *  Define what is required to specify how the network to host conversion
351 *  routines are handled.
352 *
353 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
354 *  same values.
355 *
356 *  @see CPU_LITTLE_ENDIAN
357 *
358 *  Port Specific Information:
359 *
360 *  XXX document implementation including references if appropriate
361 */
362#define CPU_BIG_ENDIAN                           FALSE
363
364/**
365 *  @ingroup CPUEndian
366 *  Define what is required to specify how the network to host conversion
367 *  routines are handled.
368 *
369 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
370 *  same values.
371 *
372 *  @see CPU_BIG_ENDIAN
373 *
374 *  Port Specific Information:
375 *
376 *  XXX document implementation including references if appropriate
377 */
378#define CPU_LITTLE_ENDIAN                        TRUE
379
380/**
381 *  @ingroup CPUInterrupt
382 *  The following defines the number of bits actually used in the
383 *  interrupt field of the task mode.  How those bits map to the
384 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
385 *
386 *  Port Specific Information:
387 *
388 *  XXX document implementation including references if appropriate
389 */
390#define CPU_MODES_INTERRUPT_MASK   0x00000001
391
392/*
393 *  Processor defined structures required for cpukit/score.
394 *
395 *  Port Specific Information:
396 *
397 *  XXX document implementation including references if appropriate
398 */
399
400/* may need to put some structures here.  */
401
402/**
403 * @defgroup CPUContext Processor Dependent Context Management
404 *
405 *  From the highest level viewpoint, there are 2 types of context to save.
406 *
407 *     -# Interrupt registers to save
408 *     -# Task level registers to save
409 *
410 *  Since RTEMS handles integer and floating point contexts separately, this
411 *  means we have the following 3 context items:
412 *
413 *     -# task level context stuff::  Context_Control
414 *     -# floating point task stuff:: Context_Control_fp
415 *     -# special interrupt level context :: CPU_Interrupt_frame
416 *
417 *  On some processors, it is cost-effective to save only the callee
418 *  preserved registers during a task context switch.  This means
419 *  that the ISR code needs to save those registers which do not
420 *  persist across function calls.  It is not mandatory to make this
421 *  distinctions between the caller/callee saves registers for the
422 *  purpose of minimizing context saved during task switch and on interrupts.
423 *  If the cost of saving extra registers is minimal, simplicity is the
424 *  choice.  Save the same context on interrupt entry as for tasks in
425 *  this case.
426 *
427 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
428 *  care should be used in designing the context area.
429 *
430 *  On some CPUs with hardware floating point support, the Context_Control_fp
431 *  structure will not be used or it simply consist of an array of a
432 *  fixed number of bytes.   This is done when the floating point context
433 *  is dumped by a "FP save context" type instruction and the format
434 *  is not really defined by the CPU.  In this case, there is no need
435 *  to figure out the exact format -- only the size.  Of course, although
436 *  this is enough information for RTEMS, it is probably not enough for
437 *  a debugger such as gdb.  But that is another problem.
438 *
439 *  Port Specific Information:
440 *
441 *  XXX document implementation including references if appropriate
442 */
443
444/**
445 *  @ingroup CPUContext Management
446 *  This defines the minimal set of integer and processor state registers
447 *  that must be saved during a voluntary context switch from one thread
448 *  to another.
449 */
450typedef struct {
451    uint32_t r16;
452    uint32_t r17;
453    uint32_t r18;
454    uint32_t r19;
455    uint32_t r20;
456    uint32_t r21;
457    uint32_t r22;
458    uint32_t r23;
459    uint32_t gp;
460    uint32_t fp;
461    uint32_t sp;
462    uint32_t ra;
463    uint32_t status;
464    /* ienable? */
465    /* ipending? */
466} Context_Control;
467
468/**
469 *  @ingroup CPUContext Management
470 *  This defines the complete set of floating point registers that must
471 *  be saved during any context switch from one thread to another.
472 */
473typedef struct {
474} Context_Control_fp;
475
476/**
477 *  @ingroup CPUContext Management
478 *  This defines the set of integer and processor state registers that must
479 *  be saved during an interrupt.  This set does not include any which are
480 *  in @ref Context_Control.
481 */
482typedef struct {
483    uint32_t r1;
484    uint32_t r2;
485    uint32_t r3;
486    uint32_t r4;
487    uint32_t r5;
488    uint32_t r6;
489    uint32_t r7;
490    uint32_t r8;
491    uint32_t r9;
492    uint32_t r10;
493    uint32_t r11;
494    uint32_t r12;
495    uint32_t r13;
496    uint32_t r14;
497    uint32_t r15;
498    uint32_t ra;
499    uint32_t gp;
500    uint32_t et;
501    uint32_t ea;
502} CPU_Interrupt_frame;
503
504/**
505 *  @ingroup CPUContext Management
506 *  This defines the set of integer and processor state registers that are
507 *  saved during a software exception.
508 */
509typedef struct {
510    uint32_t r1;
511    uint32_t r2;
512    uint32_t r3;
513    uint32_t r4;
514    uint32_t r5;
515    uint32_t r6;
516    uint32_t r7;
517    uint32_t r8;
518    uint32_t r9;
519    uint32_t r10;
520    uint32_t r11;
521    uint32_t r12;
522    uint32_t r13;
523    uint32_t r14;
524    uint32_t r15;
525    uint32_t r16;
526    uint32_t r17;
527    uint32_t r18;
528    uint32_t r19;
529    uint32_t r20;
530    uint32_t r21;
531    uint32_t r22;
532    uint32_t r23;
533    uint32_t gp;
534    uint32_t fp;
535    uint32_t sp;
536    uint32_t ra;
537    uint32_t et;
538    uint32_t ea;
539    uint32_t status;
540    uint32_t ienable;
541    uint32_t ipending;
542} CPU_Exception_frame;
543
544
545/**
546 *  The following table contains the information required to configure
547 *  the XXX processor specific parameters.
548 *
549 *  Port Specific Information:
550 *
551 *  XXX document implementation including references if appropriate
552 */
553
554typedef struct {
555  /** This element points to the BSP's pretasking hook. */
556  void       (*pretasking_hook)( void );
557  /** This element points to the BSP's predriver hook. */
558  void       (*predriver_hook)( void );
559  /** This element points to the BSP's postdriver hook. */
560  void       (*postdriver_hook)( void );
561  /** This element points to the BSP's optional idle task which may override
562   *  the default one provided with RTEMS.
563   */
564  void       (*idle_task)( void );
565  /** If this element is TRUE, then RTEMS will zero the Executive Workspace.
566   *  When this element is FALSE, it is assumed that the BSP or invoking
567   *  environment has ensured that memory was cleared before RTEMS was
568   *  invoked.
569   */
570  boolean      do_zero_of_workspace;
571  /** This field specifies the size of the IDLE task's stack.  If less than or
572   *  equal to the minimum stack size, then the IDLE task will have the minimum
573   *  stack size.
574   */
575  uint32_t     idle_task_stack_size;
576  /** This field specifies the size of the interrupt stack.  If less than or
577   *  equal to the minimum stack size, then the interrupt stack will be of
578   *  minimum stack size.
579   */
580  uint32_t     interrupt_stack_size;
581  /** The MPCI Receive server is assumed to have a stack of at least
582   *  minimum stack size.  This field specifies the amount of extra
583   *  stack this task will be given in bytes.
584   */
585  uint32_t     extra_mpci_receive_server_stack;
586  /** The BSP may want to provide it's own stack allocation routines.
587   *  In this case, the BSP will provide this stack allocation hook.
588   */
589  void *     (*stack_allocate_hook)( uint32_t   );
590  /** The BSP may want to provide it's own stack free routines.
591   *  In this case, the BSP will provide this stack free hook.
592   */
593  void       (*stack_free_hook)( void *);
594  /* end of fields required on all CPUs */
595}   rtems_cpu_table;
596
597/*
598 *  Macros to access required entires in the CPU Table are in
599 *  the file rtems/system.h.
600 *
601 *  Port Specific Information:
602 *
603 *  XXX document implementation including references if appropriate
604 */
605
606/*
607 *  Macros to access NIOS2 specific additions to the CPU Table
608 *
609 *  Port Specific Information:
610 *
611 *  XXX document implementation including references if appropriate
612 */
613
614/* There are no CPU specific additions to the CPU Table for this port. */
615
616/**
617 *  This variable is optional.  It is used on CPUs on which it is difficult
618 *  to generate an "uninitialized" FP context.  It is filled in by
619 *  @ref _CPU_Initialize and copied into the task's FP context area during
620 *  @ref _CPU_Context_Initialize.
621 *
622 *  Port Specific Information:
623 *
624 *  XXX document implementation including references if appropriate
625 */
626#if 0
627SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
628#endif
629
630/**
631 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
632 *
633 *  On some CPUs, RTEMS supports a software managed interrupt stack.
634 *  This stack is allocated by the Interrupt Manager and the switch
635 *  is performed in @ref _ISR_Handler.  These variables contain pointers
636 *  to the lowest and highest addresses in the chunk of memory allocated
637 *  for the interrupt stack.  Since it is unknown whether the stack
638 *  grows up or down (in general), this give the CPU dependent
639 *  code the option of picking the version it wants to use.
640 *
641 *  @note These two variables are required if the macro
642 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
643 *
644 *  Port Specific Information:
645 *
646 *  XXX document implementation including references if appropriate
647 */
648
649/**
650 *  @ingroup CPUInterrupt
651 *  This variable points to the lowest physical address of the interrupt
652 *  stack.
653 */
654SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
655
656/**
657 *  @ingroup CPUInterrupt
658 *  This variable points to the lowest physical address of the interrupt
659 *  stack.
660 */
661SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
662
663/**
664 *  @ingroup CPUInterrupt
665 *  With some compilation systems, it is difficult if not impossible to
666 *  call a high-level language routine from assembly language.  This
667 *  is especially true of commercial Ada compilers and name mangling
668 *  C++ ones.  This variable can be optionally defined by the CPU porter
669 *  and contains the address of the routine @ref _Thread_Dispatch.  This
670 *  can make it easier to invoke that routine at the end of the interrupt
671 *  sequence (if a dispatch is necessary).
672 *
673 *  Port Specific Information:
674 *
675 *  XXX document implementation including references if appropriate
676 */
677SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
678
679/*
680 *  Nothing prevents the porter from declaring more CPU specific variables.
681 *
682 *  Port Specific Information:
683 *
684 *  XXX document implementation including references if appropriate
685 */
686
687/* XXX: if needed, put more variables here */
688
689/**
690 *  @ingroup CPUContext
691 *  The size of the floating point context area.  On some CPUs this
692 *  will not be a "sizeof" because the format of the floating point
693 *  area is not defined -- only the size is.  This is usually on
694 *  CPUs with a "floating point save context" instruction.
695 *
696 *  Port Specific Information:
697 *
698 *  XXX document implementation including references if appropriate
699 */
700#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
701
702/**
703 *  Amount of extra stack (above minimum stack size) required by
704 *  MPCI receive server thread.  Remember that in a multiprocessor
705 *  system this thread must exist and be able to process all directives.
706 *
707 *  Port Specific Information:
708 *
709 *  XXX document implementation including references if appropriate
710 */
711#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
712
713/**
714 *  @ingroup CPUInterrupt
715 *  This defines the number of entries in the @ref _ISR_Vector_table managed
716 *  by RTEMS.
717 *
718 *  Port Specific Information:
719 *
720 *  XXX document implementation including references if appropriate
721 */
722#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
723
724/**
725 *  @ingroup CPUInterrupt
726 *  This defines the highest interrupt vector number for this port.
727 */
728#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
729
730/**
731 *  @ingroup CPUInterrupt
732 *  This is defined if the port has a special way to report the ISR nesting
733 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
734 */
735#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
736
737/**
738 *  @ingroup CPUContext
739 *  Should be large enough to run all RTEMS tests.  This ensures
740 *  that a "reasonable" small application should not have any problems.
741 *
742 *  Port Specific Information:
743 *
744 *  XXX document implementation including references if appropriate
745 */
746#define CPU_STACK_MINIMUM_SIZE          (1024*4)
747/* kawk: was *4 */
748
749/**
750 *  CPU's worst alignment requirement for data types on a byte boundary.  This
751 *  alignment does not take into account the requirements for the stack.
752 *
753 *  Port Specific Information:
754 *
755 *  XXX document implementation including references if appropriate
756 */
757#define CPU_ALIGNMENT              4
758
759/**
760 *  This number corresponds to the byte alignment requirement for the
761 *  heap handler.  This alignment requirement may be stricter than that
762 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
763 *  common for the heap to follow the same alignment requirement as
764 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
765 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
766 *
767 *  @note  This does not have to be a power of 2 although it should be
768 *         a multiple of 2 greater than or equal to 2.  The requirement
769 *         to be a multiple of 2 is because the heap uses the least
770 *         significant field of the front and back flags to indicate
771 *         that a block is in use or free.  So you do not want any odd
772 *         length blocks really putting length data in that bit.
773 *
774 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
775 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
776 *         elements allocated from the heap meet all restrictions.
777 *
778 *  Port Specific Information:
779 *
780 *  XXX document implementation including references if appropriate
781 */
782#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
783
784/**
785 *  This number corresponds to the byte alignment requirement for memory
786 *  buffers allocated by the partition manager.  This alignment requirement
787 *  may be stricter than that for the data types alignment specified by
788 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
789 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
790 *  strict enough for the partition, then this should be set to
791 *  @ref CPU_ALIGNMENT.
792 *
793 *  @note  This does not have to be a power of 2.  It does have to
794 *         be greater or equal to than @ref CPU_ALIGNMENT.
795 *
796 *  Port Specific Information:
797 *
798 *  XXX document implementation including references if appropriate
799 */
800#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
801
802/**
803 *  This number corresponds to the byte alignment requirement for the
804 *  stack.  This alignment requirement may be stricter than that for the
805 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
806 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
807 *  set to 0.
808 *
809 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
810 *
811 *  Port Specific Information:
812 *
813 *  XXX document implementation including references if appropriate
814 */
815#define CPU_STACK_ALIGNMENT        0
816
817/*
818 *  ISR handler macros
819 */
820
821/**
822 *  @ingroup CPUInterrupt
823 *  Support routine to initialize the RTEMS vector table after it is allocated.
824 *
825 *  Port Specific Information:
826 *
827 *  XXX document implementation including references if appropriate
828 */
829#define _CPU_Initialize_vectors()
830
831/**
832 *  @ingroup CPUInterrupt
833 *  Disable all interrupts for an RTEMS critical section.  The previous
834 *  level is returned in @a _isr_cookie.
835 *
836 *  @param _isr_cookie (out) will contain the previous level cookie
837 *
838 *  Port Specific Information:
839 *
840 *  XXX document implementation including references if appropriate
841 */
842#define _CPU_ISR_Disable( _isr_cookie ) \
843  { \
844    _isr_cookie = __builtin_rdctl(0); /* read status register */ \
845    __builtin_wrctl(0, 0); /* write 0 to status register */ \
846  }
847
848/**
849 *  @ingroup CPUInterrupt
850 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
851 *  This indicates the end of an RTEMS critical section.  The parameter
852 *  @a _isr_cookie is not modified.
853 *
854 *  @param _isr_cookie (in) contain the previous level cookie
855 *
856 *  Port Specific Information:
857 *
858 *  XXX document implementation including references if appropriate
859 */
860#define _CPU_ISR_Enable( _isr_cookie )  \
861  { \
862    __builtin_wrctl( 0, _isr_cookie ); \
863  }
864
865/**
866 *  @ingroup CPUInterrupt
867 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
868 *  disabling them again.  This is used to divide long RTEMS critical
869 *  sections into two or more parts.  The parameter @a _isr_cookie is not
870 *  modified.
871 *
872 *  @param _isr_cookie (in) contain the previous level cookie
873 *
874 *  Port Specific Information:
875 *
876 *  XXX document implementation including references if appropriate
877 */
878#define _CPU_ISR_Flash( _isr_cookie ) \
879  { \
880    __builtin_wrctl( 0, _isr_cookie ); \
881    /* TODO: Does NIOS2 get a chance to \
882    process IRQ between these statements? */ \
883    __builtin_wrctl( 0, 0 ); \
884  }
885
886/**
887 *  @ingroup CPUInterrupt
888 *
889 *  This routine and @ref _CPU_ISR_Get_level
890 *  Map the interrupt level in task mode onto the hardware that the CPU
891 *  actually provides.  Currently, interrupt levels which do not
892 *  map onto the CPU in a generic fashion are undefined.  Someday,
893 *  it would be nice if these were "mapped" by the application
894 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
895 *  8 - 255 would be available for bsp/application specific meaning.
896 *  This could be used to manage a programmable interrupt controller
897 *  via the rtems_task_mode directive.
898 *
899 *  Port Specific Information:
900 *
901 *  XXX document implementation including references if appropriate
902 */
903#define _CPU_ISR_Set_level( new_level ) \
904        _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 );
905
906/**
907 *  @ingroup CPUInterrupt
908 *  Return the current interrupt disable level for this task in
909 *  the format used by the interrupt level portion of the task mode.
910 *
911 *  @note This routine usually must be implemented as a subroutine.
912 *
913 *  Port Specific Information:
914 *
915 *  XXX document implementation including references if appropriate
916 */
917uint32_t   _CPU_ISR_Get_level( void );
918
919/* end of ISR handler macros */
920
921/* Context handler macros */
922
923/**
924 *  @ingroup CPUContext
925 *  Initialize the context to a state suitable for starting a
926 *  task after a context restore operation.  Generally, this
927 *  involves:
928 *
929 *     - setting a starting address
930 *     - preparing the stack
931 *     - preparing the stack and frame pointers
932 *     - setting the proper interrupt level in the context
933 *     - initializing the floating point context
934 *
935 *  This routine generally does not set any unnecessary register
936 *  in the context.  The state of the "general data" registers is
937 *  undefined at task start time.
938 *
939 *  @param _the_context (in) is the context structure to be initialized
940 *  @param _stack_base (in) is the lowest physical address of this task's stack
941 *  @param _size (in) is the size of this task's stack
942 *  @param _isr (in) is the interrupt disable level
943 *  @param _entry_point (in) is the thread's entry point.  This is
944 *         always @a _Thread_Handler
945 *  @param _is_fp (in) is TRUE if the thread is to be a floating
946 *        point thread.  This is typically only used on CPUs where the
947 *        FPU may be easily disabled by software such as on the SPARC
948 *        where the PSR contains an enable FPU bit.
949 *
950 *  Port Specific Information:
951 *
952 *  XXX document implementation including references if appropriate
953 */
954#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
955                                 _isr, _entry_point, _is_fp ) \
956   do { \
957     extern char _gp[]; \
958     uint32_t _stack = (uint32_t  )(_stack_base) + (_size) - 4; \
959     (_the_context)->gp = (void *)_gp; \
960     (_the_context)->fp = (void *)_stack; \
961     (_the_context)->sp = (void *)_stack; \
962     (_the_context)->ra = (void *)(_entry_point); \
963     (_the_context)->status  = 0x1; /* IRQs enabled */ \
964   } while ( 0 )
965
966/*
967 *  This routine is responsible for somehow restarting the currently
968 *  executing task.  If you are lucky, then all that is necessary
969 *  is restoring the context.  Otherwise, there will need to be
970 *  a special assembly routine which does something special in this
971 *  case.  @ref _CPU_Context_Restore should work most of the time.  It will
972 *  not work if restarting self conflicts with the stack frame
973 *  assumptions of restoring a context.
974 *
975 *  Port Specific Information:
976 *
977 *  XXX document implementation including references if appropriate
978 */
979#define _CPU_Context_Restart_self( _the_context ) \
980   _CPU_Context_restore( (_the_context) );
981
982/**
983 *  @ingroup CPUContext
984 *  The purpose of this macro is to allow the initial pointer into
985 *  a floating point context area (used to save the floating point
986 *  context) to be at an arbitrary place in the floating point
987 *  context area.
988 *
989 *  This is necessary because some FP units are designed to have
990 *  their context saved as a stack which grows into lower addresses.
991 *  Other FP units can be saved by simply moving registers into offsets
992 *  from the base of the context area.  Finally some FP units provide
993 *  a "dump context" instruction which could fill in from high to low
994 *  or low to high based on the whim of the CPU designers.
995 *
996 *  @param _base (in) is the lowest physical address of the floating point
997 *         context area
998 *  @param _offset (in) is the offset into the floating point area
999 *
1000 *  Port Specific Information:
1001 *
1002 *  XXX document implementation including references if appropriate
1003 */
1004#if 1
1005#define _CPU_Context_Fp_start( _base, _offset )
1006#else
1007#define _CPU_Context_Fp_start( _base, _offset ) \
1008   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
1009#endif
1010
1011/**
1012 *  This routine initializes the FP context area passed to it to.
1013 *  There are a few standard ways in which to initialize the
1014 *  floating point context.  The code included for this macro assumes
1015 *  that this is a CPU in which a "initial" FP context was saved into
1016 *  @a _CPU_Null_fp_context and it simply copies it to the destination
1017 *  context passed to it.
1018 *
1019 *  Other floating point context save/restore models include:
1020 *    -# not doing anything, and
1021 *    -# putting a "null FP status word" in the correct place in the FP context.
1022 *
1023 *  @param _destination (in) is the floating point context area
1024 *
1025 *  Port Specific Information:
1026 *
1027 *  XXX document implementation including references if appropriate
1028 */
1029#if 1
1030#define _CPU_Context_Initialize_fp( _destination )
1031#else
1032#define _CPU_Context_Initialize_fp( _destination ) \
1033  { \
1034   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
1035  }
1036#endif
1037
1038/* end of Context handler macros */
1039
1040/* Fatal Error manager macros */
1041
1042/**
1043 *  This routine copies _error into a known place -- typically a stack
1044 *  location or a register, optionally disables interrupts, and
1045 *  halts/stops the CPU.
1046 *
1047 *  Port Specific Information:
1048 *
1049 *  XXX document implementation including references if appropriate
1050 */
1051#define _CPU_Fatal_halt( _error ) \
1052  { \
1053    __builtin_wrctl(0, 0); /* write 0 to status register (disable interrupts) */ \
1054    __asm volatile ("mov et, %z0" : : "rM" (_error)); /* write error code to ET register */ \
1055    for(;;); \
1056  }
1057
1058/* end of Fatal Error manager macros */
1059
1060/* Bitfield handler macros */
1061
1062/**
1063 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
1064 *
1065 *  This set of routines are used to implement fast searches for
1066 *  the most important ready task.
1067 */
1068
1069/**
1070 *  @ingroup CPUBitfield
1071 *  This definition is set to TRUE if the port uses the generic bitfield
1072 *  manipulation implementation.
1073 */
1074#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1075
1076/**
1077 *  @ingroup CPUBitfield
1078 *  This definition is set to TRUE if the port uses the data tables provided
1079 *  by the generic bitfield manipulation implementation.
1080 *  This can occur when actually using the generic bitfield manipulation
1081 *  implementation or when implementing the same algorithm in assembly
1082 *  language for improved performance.  It is unlikely that a port will use
1083 *  the data if it has a bitfield scan instruction.
1084 */
1085#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1086
1087/**
1088 *  @ingroup CPUBitfield
1089 *  This routine sets @a _output to the bit number of the first bit
1090 *  set in @a _value.  @a _value is of CPU dependent type
1091 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
1092 *  wide although only the 16 least significant bits will be used.
1093 *
1094 *  There are a number of variables in using a "find first bit" type
1095 *  instruction.
1096 *
1097 *    -# What happens when run on a value of zero?
1098 *    -# Bits may be numbered from MSB to LSB or vice-versa.
1099 *    -# The numbering may be zero or one based.
1100 *    -# The "find first bit" instruction may search from MSB or LSB.
1101 *
1102 *  RTEMS guarantees that (1) will never happen so it is not a concern.
1103 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1104 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
1105 *  which must logically operate together.  Bits in the _value are
1106 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
1107 *  The basic major and minor values calculated by @ref _Priority_Major
1108 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1109 *  to properly range between the values returned by the "find first bit"
1110 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
1111 *  calculate the major and directly index into the minor table.
1112 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
1113 *  is the first bit found.
1114 *
1115 *  This entire "find first bit" and mapping process depends heavily
1116 *  on the manner in which a priority is broken into a major and minor
1117 *  components with the major being the 4 MSB of a priority and minor
1118 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1119 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1120 *  to the lowest priority.
1121 *
1122 *  If your CPU does not have a "find first bit" instruction, then
1123 *  there are ways to make do without it.  Here are a handful of ways
1124 *  to implement this in software:
1125 *
1126@verbatim
1127      - a series of 16 bit test instructions
1128      - a "binary search using if's"
1129      - _number = 0
1130        if _value > 0x00ff
1131          _value >>=8
1132          _number = 8;
1133 
1134        if _value > 0x0000f
1135          _value >=8
1136          _number += 4
1137 
1138        _number += bit_set_table[ _value ]
1139@endverbatim
1140 
1141 *    where bit_set_table[ 16 ] has values which indicate the first
1142 *      bit set
1143 *
1144 *  @param _value (in) is the value to be scanned
1145 *  @param _output (in) is the first bit set
1146 *
1147 *  Port Specific Information:
1148 *
1149 *  XXX document implementation including references if appropriate
1150 */
1151
1152#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1153#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1154  { \
1155    (_output) = 0;   /* do something to prevent warnings */ \
1156  }
1157#endif
1158
1159/* end of Bitfield handler macros */
1160
1161/**
1162 *  This routine builds the mask which corresponds to the bit fields
1163 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1164 *  for that routine.
1165 *
1166 *  Port Specific Information:
1167 *
1168 *  XXX document implementation including references if appropriate
1169 */
1170#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1171
1172#define _CPU_Priority_Mask( _bit_number ) \
1173  ( 1 << (_bit_number) )
1174
1175#endif
1176
1177/**
1178 *  @ingroup CPUBitfield
1179 *  This routine translates the bit numbers returned by
1180 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1181 *  a major or minor component of a priority.  See the discussion
1182 *  for that routine.
1183 *
1184 *  @param _priority (in) is the major or minor number to translate
1185 *
1186 *  Port Specific Information:
1187 *
1188 *  XXX document implementation including references if appropriate
1189 */
1190#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1191
1192#define _CPU_Priority_bits_index( _priority ) \
1193  (_priority)
1194
1195#endif
1196
1197/* end of Priority handler macros */
1198
1199/* functions */
1200
1201/**
1202 *  This routine performs CPU dependent initialization.
1203 *
1204 *  @param cpu_table (in) is the CPU Dependent Configuration Table
1205 *  @param thread_dispatch (in) is the address of @ref _Thread_Dispatch
1206 *
1207 *  Port Specific Information:
1208 *
1209 *  XXX document implementation including references if appropriate
1210 */
1211void _CPU_Initialize(
1212  rtems_cpu_table  *cpu_table,
1213  void      (*thread_dispatch)
1214);
1215
1216/**
1217 *  @ingroup CPUInterrupt
1218 *  This routine installs a "raw" interrupt handler directly into the
1219 *  processor's vector table.
1220 *
1221 *  @param vector (in) is the vector number
1222 *  @param new_handler (in) is the raw ISR handler to install
1223 *  @param old_handler (in) is the previously installed ISR Handler
1224 *
1225 *  Port Specific Information:
1226 *
1227 *  XXX document implementation including references if appropriate
1228 */
1229void _CPU_ISR_install_raw_handler(
1230  uint32_t    vector,
1231  proc_ptr    new_handler,
1232  proc_ptr   *old_handler
1233);
1234
1235/**
1236 *  @ingroup CPUInterrupt
1237 *  This routine installs an interrupt vector.
1238 *
1239 *  @param vector (in) is the vector number
1240 *  @param new_handler (in) is the RTEMS ISR handler to install
1241 *  @param old_handler (in) is the previously installed ISR Handler
1242 *
1243 *  Port Specific Information:
1244 *
1245 *  XXX document implementation including references if appropriate
1246 */
1247void _CPU_ISR_install_vector(
1248  uint32_t    vector,
1249  proc_ptr    new_handler,
1250  proc_ptr   *old_handler
1251);
1252
1253/**
1254 *  @ingroup CPUInterrupt
1255 *  This routine installs the hardware interrupt stack pointer.
1256 *
1257 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1258 *         is TRUE.
1259 *
1260 *  Port Specific Information:
1261 *
1262 *  XXX document implementation including references if appropriate
1263 */
1264void _CPU_Install_interrupt_stack( void );
1265
1266/**
1267 *  This routine is the CPU dependent IDLE thread body.
1268 *
1269 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1270 *         is TRUE.
1271 *
1272 *  Port Specific Information:
1273 *
1274 *  XXX document implementation including references if appropriate
1275 */
1276void _CPU_Thread_Idle_body( void );
1277
1278/**
1279 *  @ingroup CPUContext
1280 *  This routine switches from the run context to the heir context.
1281 *
1282 *  @param run (in) points to the context of the currently executing task
1283 *  @param heir (in) points to the context of the heir task
1284 *
1285 *  Port Specific Information:
1286 *
1287 *  XXX document implementation including references if appropriate
1288 */
1289void _CPU_Context_switch(
1290  Context_Control  *run,
1291  Context_Control  *heir
1292);
1293
1294/**
1295 *  @ingroup CPUContext
1296 *  This routine is generally used only to restart self in an
1297 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1298 *
1299 *  @param new_context (in) points to the context to be restored.
1300 *
1301 *  @note May be unnecessary to reload some registers.
1302 *
1303 *  Port Specific Information:
1304 *
1305 *  XXX document implementation including references if appropriate
1306 */
1307void _CPU_Context_restore(
1308  Context_Control *new_context
1309);
1310
1311/**
1312 *  @ingroup CPUContext
1313 *  This routine saves the floating point context passed to it.
1314 *
1315 *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
1316 *  point context area
1317 *
1318 *  @return on output @a *fp_context_ptr will contain the address that
1319 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1320 *
1321 *  Port Specific Information:
1322 *
1323 *  XXX document implementation including references if appropriate
1324 */
1325void _CPU_Context_save_fp(
1326  void **fp_context_ptr
1327);
1328
1329/**
1330 *  @ingroup CPUContext
1331 *  This routine restores the floating point context passed to it.
1332 *
1333 *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
1334 *  point context area to restore
1335 *
1336 *  @return on output @a *fp_context_ptr will contain the address that
1337 *  should be used with @ref _CPU_Context_save_fp to save this context.
1338 *
1339 *  Port Specific Information:
1340 *
1341 *  XXX document implementation including references if appropriate
1342 */
1343void _CPU_Context_restore_fp(
1344  void **fp_context_ptr
1345);
1346
1347/**
1348 *  @ingroup CPUEndian
1349 *  The following routine swaps the endian format of an unsigned int.
1350 *  It must be static because it is referenced indirectly.
1351 *
1352 *  This version will work on any processor, but if there is a better
1353 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1354 *
1355 *     swap least significant two bytes with 16-bit rotate
1356 *     swap upper and lower 16-bits
1357 *     swap most significant two bytes with 16-bit rotate
1358 *
1359 *  Some CPUs have special instructions which swap a 32-bit quantity in
1360 *  a single instruction (e.g. i486).  It is probably best to avoid
1361 *  an "endian swapping control bit" in the CPU.  One good reason is
1362 *  that interrupts would probably have to be disabled to insure that
1363 *  an interrupt does not try to access the same "chunk" with the wrong
1364 *  endian.  Another good reason is that on some CPUs, the endian bit
1365 *  endianness for ALL fetches -- both code and data -- so the code
1366 *  will be fetched incorrectly.
1367 *
1368 *  @param value (in) is the value to be swapped
1369 *  @return the value after being endian swapped
1370 *
1371 *  Port Specific Information:
1372 *
1373 *  XXX document implementation including references if appropriate
1374 */
1375static inline uint32_t CPU_swap_u32(
1376  uint32_t value
1377)
1378{
1379  uint32_t   byte1, byte2, byte3, byte4, swapped;
1380 
1381  byte4 = (value >> 24) & 0xff;
1382  byte3 = (value >> 16) & 0xff;
1383  byte2 = (value >> 8)  & 0xff;
1384  byte1 =  value        & 0xff;
1385 
1386  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1387  return( swapped );
1388}
1389
1390/**
1391 *  @ingroup CPUEndian
1392 *  This routine swaps a 16 bir quantity.
1393 *
1394 *  @param value (in) is the value to be swapped
1395 *  @return the value after being endian swapped
1396 */
1397#define CPU_swap_u16( value ) \
1398  (((value&0xff) << 8) | ((value >> 8)&0xff))
1399
1400#ifdef __cplusplus
1401}
1402#endif
1403
1404#endif
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