source: rtems/cpukit/score/cpu/nios2/rtems/score/cpu.h @ c499856

4.11
Last change on this file since c499856 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

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1/**
2 * @file
3 *
4 * @brief Altera Nios II CPU Department Source
5 */
6
7/*
8 *  Copyright (c) 2011 embedded brains GmbH
9 *
10 *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
11 *
12 *  COPYRIGHT (c) 1989-2004.
13 *  On-Line Applications Research Corporation (OAR).
14 *
15 *  The license and distribution terms for this file may be
16 *  found in the file LICENSE in this distribution or at
17 *  http://www.rtems.org/license/LICENSE.
18 */
19
20#ifndef _RTEMS_SCORE_CPU_H
21#define _RTEMS_SCORE_CPU_H
22
23#ifdef __cplusplus
24extern "C" {
25#endif
26
27#include <rtems/score/types.h>
28#include <rtems/score/nios2.h>
29
30/*
31 * TODO: Run the timing tests and figure out what is better.
32 */
33#define CPU_INLINE_ENABLE_DISPATCH FALSE
34
35/*
36 * TODO: Run the timing tests and figure out what is better.
37 */
38#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
39
40#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
41
42#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
43
44#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
45
46#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
47
48#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
49
50#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
51
52#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
53
54#define CPU_ISR_PASSES_FRAME_POINTER FALSE
55
56#define CPU_HARDWARE_FP FALSE
57
58#define CPU_SOFTWARE_FP FALSE
59
60#define CPU_CONTEXT_FP_SIZE 0
61
62#define CPU_ALL_TASKS_ARE_FP FALSE
63
64#define CPU_IDLE_TASK_IS_FP FALSE
65
66#define CPU_USE_DEFERRED_FP_SWITCH FALSE
67
68#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
69
70#define CPU_STACK_GROWS_UP FALSE
71
72#define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32)))
73
74#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
75
76#define CPU_BIG_ENDIAN FALSE
77
78#define CPU_LITTLE_ENDIAN TRUE
79
80#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
81
82#define CPU_SIZEOF_POINTER 4
83
84/*
85 * Alignment value according to "Nios II Processor Reference" chapter 7
86 * "Application Binary Interface" section "Memory Alignment".
87 */
88#define CPU_ALIGNMENT 4
89
90#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
91
92#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
93
94/*
95 * Alignment value according to "Nios II Processor Reference" chapter 7
96 * "Application Binary Interface" section "Stacks".
97 */
98#define CPU_STACK_ALIGNMENT 4
99
100/*
101 * A Nios II configuration with an external interrupt controller (EIC) supports
102 * up to 64 interrupt levels.  A Nios II configuration with an internal
103 * interrupt controller (IIC) has only two interrupt levels (enabled and
104 * disabled).  The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
105 * take care about configuration specific mappings.
106 */
107#define CPU_MODES_INTERRUPT_MASK 0x3f
108
109#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
110
111#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
112
113#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
114
115#define CPU_PER_CPU_CONTROL_SIZE 0
116
117#ifndef ASM
118
119typedef struct {
120  /* There is no CPU specific per-CPU state */
121} CPU_Per_CPU_control;
122
123/**
124 * @brief Thread register context.
125 *
126 * The thread register context covers the non-volatile registers, the thread
127 * stack pointer, the return address, and the processor status.
128 *
129 * There is no need to save the global pointer (gp) since it is a system wide
130 * constant and set-up with the C runtime environment.
131 *
132 * The @a thread_dispatch_disabled field is used for the external interrupt
133 * controller (EIC) support.
134 *
135 * @see _Nios2_Thread_dispatch_disabled
136 */
137typedef struct {
138  uint32_t r16;
139  uint32_t r17;
140  uint32_t r18;
141  uint32_t r19;
142  uint32_t r20;
143  uint32_t r21;
144  uint32_t r22;
145  uint32_t r23;
146  uint32_t fp;
147  uint32_t status;
148  uint32_t sp;
149  uint32_t ra;
150  uint32_t thread_dispatch_disabled;
151  uint32_t stack_mpubase;
152  uint32_t stack_mpuacc;
153} Context_Control;
154
155#define _CPU_Context_Get_SP( _context ) \
156  (_context)->sp
157
158typedef void CPU_Interrupt_frame;
159
160typedef struct {
161  uint32_t r1;
162  uint32_t r2;
163  uint32_t r3;
164  uint32_t r4;
165  uint32_t r5;
166  uint32_t r6;
167  uint32_t r7;
168  uint32_t r8;
169  uint32_t r9;
170  uint32_t r10;
171  uint32_t r11;
172  uint32_t r12;
173  uint32_t r13;
174  uint32_t r14;
175  uint32_t r15;
176  uint32_t r16;
177  uint32_t r17;
178  uint32_t r18;
179  uint32_t r19;
180  uint32_t r20;
181  uint32_t r21;
182  uint32_t r22;
183  uint32_t r23;
184  uint32_t gp;
185  uint32_t fp;
186  uint32_t sp;
187  uint32_t ra;
188  uint32_t et;
189  uint32_t ea;
190  uint32_t status;
191  uint32_t ienable;
192  uint32_t ipending;
193} CPU_Exception_frame;
194
195void _CPU_Initialize_vectors( void );
196
197/**
198 * @brief Macro to disable interrupts.
199 *
200 * The processor status before disabling the interrupts will be stored in
201 * @a _isr_cookie.  This value will be used in _CPU_ISR_Flash() and
202 * _CPU_ISR_Enable().
203 *
204 * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in
205 * the status register representing the interrupt level.  The global symbol
206 * _Nios2_ISR_Status_bits will be used to set the bits representing an
207 * interrupt level that disables interrupts.  Both global symbols must be
208 * provided by the board support package.
209 *
210 * In case the Nios II uses the internal interrupt controller (IIC), then only
211 * the PIE status bit is used.
212 *
213 * In case the Nios II uses the external interrupt controller (EIC), then the
214 * RSIE status bit or the IL status field is used depending on the interrupt
215 * handling variant and the shadow register usage.
216 */
217#define _CPU_ISR_Disable( _isr_cookie ) \
218  do { \
219    int _tmp; \
220    __asm__ volatile ( \
221      "rdctl %0, status\n" \
222      "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
223      "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
224      "and %1, %0, %1\n" \
225      "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
226      "wrctl status, %1" \
227      : "=&r" (_isr_cookie), "=&r" (_tmp) \
228    ); \
229  } while ( 0 )
230
231/**
232 * @brief Macro to restore the processor status.
233 *
234 * The @a _isr_cookie must contain the processor status returned by
235 * _CPU_ISR_Disable().  The value is not modified.
236 */
237#define _CPU_ISR_Enable( _isr_cookie ) \
238  __builtin_wrctl( 0, (int) _isr_cookie )
239
240/**
241 * @brief Macro to restore the processor status and disable the interrupts
242 * again.
243 *
244 * The @a _isr_cookie must contain the processor status returned by
245 * _CPU_ISR_Disable().  The value is not modified.
246 *
247 * This flash code is optimal for all Nios II configurations.  The rdctl does
248 * not flush the pipeline and has only a late result penalty.  The wrctl on
249 * the other hand leads to a pipeline flush.
250 */
251#define _CPU_ISR_Flash( _isr_cookie ) \
252  do { \
253    int _status = __builtin_rdctl( 0 ); \
254    __builtin_wrctl( 0, (int) _isr_cookie ); \
255    __builtin_wrctl( 0, _status ); \
256  } while ( 0 )
257
258/**
259 * @brief Sets the interrupt level for the executing thread.
260 *
261 * The valid values of @a new_level depend on the Nios II configuration.  A
262 * value of zero represents enabled interrupts in all configurations.
263 *
264 * @see _CPU_ISR_Get_level()
265 */
266void _CPU_ISR_Set_level( uint32_t new_level );
267
268/**
269 * @brief Returns the interrupt level of the executing thread.
270 *
271 * @retval 0 Interrupts are enabled.
272 * @retval otherwise The value depends on the Nios II configuration.  In case
273 * of an internal interrupt controller (IIC) the only valid value is one which
274 * indicates disabled interrupts.  In case of an external interrupt controller
275 * (EIC) there are two possibilities.  Firstly if the RSIE status bit is used
276 * to disable interrupts, then one is the only valid value indicating disabled
277 * interrupts.  Secondly if the IL status field is used to disable interrupts,
278 * then this value will be returned.  Interrupts are disabled at the maximum
279 * level specified by the _Nios2_ISR_Status_bits.
280 */
281uint32_t _CPU_ISR_Get_level( void );
282
283/**
284 * @brief Initializes the CPU context.
285 *
286 * The following steps are performed:
287 *  - setting a starting address
288 *  - preparing the stack
289 *  - preparing the stack and frame pointers
290 *  - setting the proper interrupt level in the context
291 *
292 * @param[in] context points to the context area
293 * @param[in] stack_area_begin is the low address of the allocated stack area
294 * @param[in] stack_area_size is the size of the stack area in bytes
295 * @param[in] new_level is the interrupt level for the task
296 * @param[in] entry_point is the task's entry point
297 * @param[in] is_fp is set to @c true if the task is a floating point task
298 * @param[in] tls_area is the thread-local storage (TLS) area
299 */
300void _CPU_Context_Initialize(
301  Context_Control *context,
302  void *stack_area_begin,
303  size_t stack_area_size,
304  uint32_t new_level,
305  void (*entry_point)( void ),
306  bool is_fp,
307  void *tls_area
308);
309
310#define _CPU_Context_Restart_self( _the_context ) \
311  _CPU_Context_restore( (_the_context) );
312
313void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
314
315/**
316 * @brief CPU initialization.
317 */
318void _CPU_Initialize( void );
319
320/**
321 * @brief CPU ISR install raw handler.
322 */
323void _CPU_ISR_install_raw_handler(
324  uint32_t vector,
325  proc_ptr new_handler,
326  proc_ptr *old_handler
327);
328
329/**
330 * @brief CPU ISR install vector.
331 */
332void _CPU_ISR_install_vector(
333  uint32_t vector,
334  proc_ptr new_handler,
335  proc_ptr *old_handler
336);
337
338void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
339
340void _CPU_Context_restore(
341  Context_Control *new_context
342) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
343
344void _CPU_Context_volatile_clobber( uintptr_t pattern );
345
346void _CPU_Context_validate( uintptr_t pattern );
347
348void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
349
350static inline uint32_t CPU_swap_u32( uint32_t value )
351{
352  uint32_t byte1, byte2, byte3, byte4, swapped;
353
354  byte4 = (value >> 24) & 0xff;
355  byte3 = (value >> 16) & 0xff;
356  byte2 = (value >> 8)  & 0xff;
357  byte1 =  value        & 0xff;
358
359  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
360
361  return swapped;
362}
363
364#define CPU_swap_u16( value ) \
365  (((value&0xff) << 8) | ((value >> 8)&0xff))
366
367typedef uint32_t CPU_Counter_ticks;
368
369CPU_Counter_ticks _CPU_Counter_read( void );
370
371static inline CPU_Counter_ticks _CPU_Counter_difference(
372  CPU_Counter_ticks second,
373  CPU_Counter_ticks first
374)
375{
376  return second - first;
377}
378
379#endif /* ASM */
380
381#ifdef __cplusplus
382}
383#endif
384
385#endif
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