source: rtems/cpukit/score/cpu/nios2/rtems/score/cpu.h @ c03e2bc

4.104.115
Last change on this file since c03e2bc was c03e2bc, checked in by Joel Sherrill <joel.sherrill@…>, on 02/11/09 at 21:45:05

2009-02-11 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and passing address of _Thread_Dispatch to _CPU_Initialize. Clean up comments.
  • Property mode set to 100644
File size: 42.3 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the XXX
7 *  processor.
8 *
9 *  @note This file is part of a porting template that is intended
10 *  to be used as the starting point when porting RTEMS to a new
11 *  CPU family.  The following needs to be done when using this as
12 *  the starting point for a new port:
13 *
14 *  + Anywhere there is an XXX, it should be replaced
15 *    with information about the CPU family being ported to.
16 * 
17 *  + At the end of each comment section, there is a heading which
18 *    says "Port Specific Information:".  When porting to RTEMS,
19 *    add CPU family specific information in this section
20 */
21
22/*  COPYRIGHT (c) 1989-2004.
23 *  On-Line Applications Research Corporation (OAR).
24 *
25 *  The license and distribution terms for this file may be
26 *  found in the file LICENSE in this distribution or at
27 *  http://www.rtems.com/license/LICENSE.
28 *
29 *  $Id$
30 */
31
32#ifndef _RTEMS_SCORE_CPU_H
33#define _RTEMS_SCORE_CPU_H
34
35#ifdef __cplusplus
36extern "C" {
37#endif
38
39#include <rtems/score/nios2.h>            /* pick up machine definitions */
40#ifndef ASM
41#include <rtems/score/types.h>
42#endif
43
44/* conditional compilation parameters */
45
46/**
47 *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
48 *
49 *  If TRUE, then they are inlined.
50 *  If FALSE, then a subroutine call is made.
51 *
52 *  This conditional is an example of the classic trade-off of size
53 *  versus speed.  Inlining the call (TRUE) typically increases the
54 *  size of RTEMS while speeding up the enabling of dispatching.
55 *
56 *  @note In general, the @ref _Thread_Dispatch_disable_level will
57 *  only be 0 or 1 unless you are in an interrupt handler and that
58 *  interrupt handler invokes the executive.]  When not inlined
59 *  something calls @ref _Thread_Enable_dispatch which in turns calls
60 *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
61 *  one subroutine call is avoided entirely.
62 *
63 *  Port Specific Information:
64 *
65 *  XXX document implementation including references if appropriate
66 */
67#define CPU_INLINE_ENABLE_DISPATCH       FALSE
68
69/**
70 *  Should the body of the search loops in _Thread_queue_Enqueue_priority
71 *  be unrolled one time?  In unrolled each iteration of the loop examines
72 *  two "nodes" on the chain being searched.  Otherwise, only one node
73 *  is examined per iteration.
74 *
75 *  If TRUE, then the loops are unrolled.
76 *  If FALSE, then the loops are not unrolled.
77 *
78 *  The primary factor in making this decision is the cost of disabling
79 *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
80 *  body of the loop.  On some CPUs, the flash is more expensive than
81 *  one iteration of the loop body.  In this case, it might be desirable
82 *  to unroll the loop.  It is important to note that on some CPUs, this
83 *  code is the longest interrupt disable period in RTEMS.  So it is
84 *  necessary to strike a balance when setting this parameter.
85 *
86 *  Port Specific Information:
87 *
88 *  XXX document implementation including references if appropriate
89 */
90#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
91
92/**
93 *  Does RTEMS manage a dedicated interrupt stack in software?
94 *
95 *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
96 *  If FALSE, nothing is done.
97 *
98 *  If the CPU supports a dedicated interrupt stack in hardware,
99 *  then it is generally the responsibility of the BSP to allocate it
100 *  and set it up.
101 *
102 *  If the CPU does not support a dedicated interrupt stack, then
103 *  the porter has two options: (1) execute interrupts on the
104 *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
105 *  interrupt stack.
106 *
107 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
108 *
109 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
110 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
111 *  possible that both are FALSE for a particular CPU.  Although it
112 *  is unclear what that would imply about the interrupt processing
113 *  procedure on that CPU.
114 *
115 *  Port Specific Information:
116 *
117 *  XXX document implementation including references if appropriate
118 */
119#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
120
121/**
122 *  Does the CPU follow the simple vectored interrupt model?
123 *
124 *  If TRUE, then RTEMS allocates the vector table it internally manages.
125 *  If FALSE, then the BSP is assumed to allocate and manage the vector
126 *  table
127 *
128 *  Port Specific Information:
129 *
130 *  XXX document implementation including references if appropriate
131 */
132#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
133
134/**
135 *  Does this CPU have hardware support for a dedicated interrupt stack?
136 *
137 *  If TRUE, then it must be installed during initialization.
138 *  If FALSE, then no installation is performed.
139 *
140 *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
141 *
142 *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
143 *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
144 *  possible that both are FALSE for a particular CPU.  Although it
145 *  is unclear what that would imply about the interrupt processing
146 *  procedure on that CPU.
147 *
148 *  Port Specific Information:
149 *
150 *  XXX document implementation including references if appropriate
151 */
152#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
153
154/**
155 *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
156 *
157 *  If TRUE, then the memory is allocated during initialization.
158 *  If FALSE, then the memory is allocated during initialization.
159 *
160 *  This should be TRUE is @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
161 *  or @ref CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
162 *
163 *  Port Specific Information:
164 *
165 *  XXX document implementation including references if appropriate
166 */
167#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
168
169/**
170 *  Does the RTEMS invoke the user's ISR with the vector number and
171 *  a pointer to the saved interrupt frame (1) or just the vector
172 *  number (0)?
173 *
174 *  Port Specific Information:
175 *
176 *  XXX document implementation including references if appropriate
177 */
178#define CPU_ISR_PASSES_FRAME_POINTER 1
179
180/**
181 *  @def CPU_HARDWARE_FP
182 *
183 *  Does the CPU have hardware floating point?
184 *
185 *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is supported.
186 *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is ignored.
187 *
188 *  If there is a FP coprocessor such as the i387 or mc68881, then
189 *  the answer is TRUE.
190 *
191 *  It indicates whether or not this CPU model has FP support.  For
192 *  example, it would be possible to have an i386_nofp CPU model
193 *  which set this to false to indicate that you have an i386 without
194 *  an i387 and wish to leave floating point support out of RTEMS.
195 */
196
197/**
198 *  @def CPU_SOFTWARE_FP
199 *
200 *  Does the CPU have no hardware floating point and GCC provides a
201 *  software floating point implementation which must be context
202 *  switched?
203 *
204 *  This feature conditional is used to indicate whether or not there
205 *  is software implemented floating point that must be context
206 *  switched.  The determination of whether or not this applies
207 *  is very tool specific and the state saved/restored is also
208 *  compiler specific.
209 *
210 *  Port Specific Information:
211 *
212 *  XXX document implementation including references if appropriate
213 */
214#define CPU_HARDWARE_FP     FALSE
215#define CPU_SOFTWARE_FP     FALSE
216
217/**
218 *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
219 *
220 *  If TRUE, then the @ref RTEMS_FLOATING_POINT task attribute is assumed.
221 *  If FALSE, then the @ref RTEMS_FLOATING_POINT task attribute is followed.
222 *
223 *  So far, the only CPUs in which this option has been used are the
224 *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
225 *  gcc both implicitly used the floating point registers to perform
226 *  integer multiplies.  Similarly, the PowerPC port of gcc has been
227 *  seen to allocate floating point local variables and touch the FPU
228 *  even when the flow through a subroutine (like vfprintf()) might
229 *  not use floating point formats.
230 *
231 *  If a function which you would not think utilize the FP unit DOES,
232 *  then one can not easily predict which tasks will use the FP hardware.
233 *  In this case, this option should be TRUE.
234 *
235 *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
236 *
237 *  Port Specific Information:
238 *
239 *  XXX document implementation including references if appropriate
240 */
241#define CPU_ALL_TASKS_ARE_FP     FALSE
242
243/**
244 *  Should the IDLE task have a floating point context?
245 *
246 *  If TRUE, then the IDLE task is created as a @ref RTEMS_FLOATING_POINT task
247 *  and it has a floating point context which is switched in and out.
248 *  If FALSE, then the IDLE task does not have a floating point context.
249 *
250 *  Setting this to TRUE negatively impacts the time required to preempt
251 *  the IDLE task from an interrupt because the floating point context
252 *  must be saved as part of the preemption.
253 *
254 *  Port Specific Information:
255 *
256 *  XXX document implementation including references if appropriate
257 */
258#define CPU_IDLE_TASK_IS_FP      FALSE
259
260/**
261 *  Should the saving of the floating point registers be deferred
262 *  until a context switch is made to another different floating point
263 *  task?
264 *
265 *  If TRUE, then the floating point context will not be stored until
266 *  necessary.  It will remain in the floating point registers and not
267 *  disturned until another floating point task is switched to.
268 *
269 *  If FALSE, then the floating point context is saved when a floating
270 *  point task is switched out and restored when the next floating point
271 *  task is restored.  The state of the floating point registers between
272 *  those two operations is not specified.
273 *
274 *  If the floating point context does NOT have to be saved as part of
275 *  interrupt dispatching, then it should be safe to set this to TRUE.
276 *
277 *  Setting this flag to TRUE results in using a different algorithm
278 *  for deciding when to save and restore the floating point context.
279 *  The deferred FP switch algorithm minimizes the number of times
280 *  the FP context is saved and restored.  The FP context is not saved
281 *  until a context switch is made to another, different FP task.
282 *  Thus in a system with only one FP task, the FP context will never
283 *  be saved or restored.
284 *
285 *  Port Specific Information:
286 *
287 *  XXX document implementation including references if appropriate
288 */
289#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
290
291/**
292 *  Does this port provide a CPU dependent IDLE task implementation?
293 *
294 *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
295 *  must be provided and is the default IDLE thread body instead of
296 *  @ref _CPU_Thread_Idle_body.
297 *
298 *  If FALSE, then use the generic IDLE thread body if the BSP does
299 *  not provide one.
300 *
301 *  This is intended to allow for supporting processors which have
302 *  a low power or idle mode.  When the IDLE thread is executed, then
303 *  the CPU can be powered down.
304 *
305 *  The order of precedence for selecting the IDLE thread body is:
306 *
307 *    -#  BSP provided
308 *    -#  CPU dependent (if provided)
309 *    -#  generic (if no BSP and no CPU dependent)
310 *
311 *  Port Specific Information:
312 *
313 *  XXX document implementation including references if appropriate
314 */
315#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
316
317/**
318 *  Does the stack grow up (toward higher addresses) or down
319 *  (toward lower addresses)?
320 *
321 *  If TRUE, then the grows upward.
322 *  If FALSE, then the grows toward smaller addresses.
323 *
324 *  Port Specific Information:
325 *
326 *  XXX document implementation including references if appropriate
327 */
328#define CPU_STACK_GROWS_UP               FALSE
329
330/**
331 *  The following is the variable attribute used to force alignment
332 *  of critical RTEMS structures.  On some processors it may make
333 *  sense to have these aligned on tighter boundaries than
334 *  the minimum requirements of the compiler in order to have as
335 *  much of the critical data area as possible in a cache line.
336 *
337 *  The placement of this macro in the declaration of the variables
338 *  is based on the syntactically requirements of the GNU C
339 *  "__attribute__" extension.  For example with GNU C, use
340 *  the following to force a structures to a 32 byte boundary.
341 *
342 *      __attribute__ ((aligned (32)))
343 *
344 *  @note Currently only the Priority Bit Map table uses this feature.
345 *        To benefit from using this, the data must be heavily
346 *        used so it will stay in the cache and used frequently enough
347 *        in the executive to justify turning this on.
348 *
349 *  Port Specific Information:
350 *
351 *  XXX document implementation including references if appropriate
352 */
353#define CPU_STRUCTURE_ALIGNMENT
354
355/**
356 *  @defgroup CPUEndian Processor Dependent Endianness Support
357 *
358 *  This group assists in issues related to processor endianness.
359 */
360
361/**
362 *  @ingroup CPUEndian
363 *  Define what is required to specify how the network to host conversion
364 *  routines are handled.
365 *
366 *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
367 *  same values.
368 *
369 *  @see CPU_LITTLE_ENDIAN
370 *
371 *  Port Specific Information:
372 *
373 *  XXX document implementation including references if appropriate
374 */
375#define CPU_BIG_ENDIAN                           FALSE
376
377/**
378 *  @ingroup CPUEndian
379 *  Define what is required to specify how the network to host conversion
380 *  routines are handled.
381 *
382 *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
383 *  same values.
384 *
385 *  @see CPU_BIG_ENDIAN
386 *
387 *  Port Specific Information:
388 *
389 *  XXX document implementation including references if appropriate
390 */
391#define CPU_LITTLE_ENDIAN                        TRUE
392
393/**
394 *  @ingroup CPUInterrupt
395 *  The following defines the number of bits actually used in the
396 *  interrupt field of the task mode.  How those bits map to the
397 *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
398 *
399 *  Port Specific Information:
400 *
401 *  XXX document implementation including references if appropriate
402 */
403#define CPU_MODES_INTERRUPT_MASK   0x00000001
404
405/*
406 *  Processor defined structures required for cpukit/score.
407 *
408 *  Port Specific Information:
409 *
410 *  XXX document implementation including references if appropriate
411 */
412
413/* may need to put some structures here.  */
414
415/**
416 * @defgroup CPUContext Processor Dependent Context Management
417 *
418 *  From the highest level viewpoint, there are 2 types of context to save.
419 *
420 *     -# Interrupt registers to save
421 *     -# Task level registers to save
422 *
423 *  Since RTEMS handles integer and floating point contexts separately, this
424 *  means we have the following 3 context items:
425 *
426 *     -# task level context stuff::  Context_Control
427 *     -# floating point task stuff:: Context_Control_fp
428 *     -# special interrupt level context :: CPU_Interrupt_frame
429 *
430 *  On some processors, it is cost-effective to save only the callee
431 *  preserved registers during a task context switch.  This means
432 *  that the ISR code needs to save those registers which do not
433 *  persist across function calls.  It is not mandatory to make this
434 *  distinctions between the caller/callee saves registers for the
435 *  purpose of minimizing context saved during task switch and on interrupts.
436 *  If the cost of saving extra registers is minimal, simplicity is the
437 *  choice.  Save the same context on interrupt entry as for tasks in
438 *  this case.
439 *
440 *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
441 *  care should be used in designing the context area.
442 *
443 *  On some CPUs with hardware floating point support, the Context_Control_fp
444 *  structure will not be used or it simply consist of an array of a
445 *  fixed number of bytes.   This is done when the floating point context
446 *  is dumped by a "FP save context" type instruction and the format
447 *  is not really defined by the CPU.  In this case, there is no need
448 *  to figure out the exact format -- only the size.  Of course, although
449 *  this is enough information for RTEMS, it is probably not enough for
450 *  a debugger such as gdb.  But that is another problem.
451 *
452 *  Port Specific Information:
453 *
454 *  XXX document implementation including references if appropriate
455 */
456
457/**
458 *  @ingroup CPUContext Management
459 *  This defines the minimal set of integer and processor state registers
460 *  that must be saved during a voluntary context switch from one thread
461 *  to another.
462 */
463typedef struct {
464    uint32_t r16;
465    uint32_t r17;
466    uint32_t r18;
467    uint32_t r19;
468    uint32_t r20;
469    uint32_t r21;
470    uint32_t r22;
471    uint32_t r23;
472    uint32_t gp;
473    uint32_t fp;
474    uint32_t sp;
475    uint32_t ra;
476    uint32_t status;
477    /* ienable? */
478    /* ipending? */
479} Context_Control;
480
481#define _CPU_Context_Get_SP( _context ) \
482  (_context)->sp
483
484/**
485 *  @ingroup CPUContext Management
486 *  This defines the complete set of floating point registers that must
487 *  be saved during any context switch from one thread to another.
488 */
489typedef struct {
490} Context_Control_fp;
491
492/**
493 *  @ingroup CPUContext Management
494 *  This defines the set of integer and processor state registers that must
495 *  be saved during an interrupt.  This set does not include any which are
496 *  in @ref Context_Control.
497 */
498typedef struct {
499    uint32_t r1;
500    uint32_t r2;
501    uint32_t r3;
502    uint32_t r4;
503    uint32_t r5;
504    uint32_t r6;
505    uint32_t r7;
506    uint32_t r8;
507    uint32_t r9;
508    uint32_t r10;
509    uint32_t r11;
510    uint32_t r12;
511    uint32_t r13;
512    uint32_t r14;
513    uint32_t r15;
514    uint32_t ra;
515    uint32_t gp;
516    uint32_t et;
517    uint32_t ea;
518} CPU_Interrupt_frame;
519
520/**
521 *  @ingroup CPUContext Management
522 *  This defines the set of integer and processor state registers that are
523 *  saved during a software exception.
524 */
525typedef struct {
526    uint32_t r1;
527    uint32_t r2;
528    uint32_t r3;
529    uint32_t r4;
530    uint32_t r5;
531    uint32_t r6;
532    uint32_t r7;
533    uint32_t r8;
534    uint32_t r9;
535    uint32_t r10;
536    uint32_t r11;
537    uint32_t r12;
538    uint32_t r13;
539    uint32_t r14;
540    uint32_t r15;
541    uint32_t r16;
542    uint32_t r17;
543    uint32_t r18;
544    uint32_t r19;
545    uint32_t r20;
546    uint32_t r21;
547    uint32_t r22;
548    uint32_t r23;
549    uint32_t gp;
550    uint32_t fp;
551    uint32_t sp;
552    uint32_t ra;
553    uint32_t et;
554    uint32_t ea;
555    uint32_t status;
556    uint32_t ienable;
557    uint32_t ipending;
558} CPU_Exception_frame;
559
560/**
561 *  This variable is optional.  It is used on CPUs on which it is difficult
562 *  to generate an "uninitialized" FP context.  It is filled in by
563 *  @ref _CPU_Initialize and copied into the task's FP context area during
564 *  @ref _CPU_Context_Initialize.
565 *
566 *  Port Specific Information:
567 *
568 *  XXX document implementation including references if appropriate
569 */
570#if 0
571SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
572#endif
573
574/**
575 *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
576 *
577 *  On some CPUs, RTEMS supports a software managed interrupt stack.
578 *  This stack is allocated by the Interrupt Manager and the switch
579 *  is performed in @ref _ISR_Handler.  These variables contain pointers
580 *  to the lowest and highest addresses in the chunk of memory allocated
581 *  for the interrupt stack.  Since it is unknown whether the stack
582 *  grows up or down (in general), this give the CPU dependent
583 *  code the option of picking the version it wants to use.
584 *
585 *  @note These two variables are required if the macro
586 *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
587 *
588 *  Port Specific Information:
589 *
590 *  XXX document implementation including references if appropriate
591 */
592
593/**
594 *  @ingroup CPUInterrupt
595 *  This variable points to the lowest physical address of the interrupt
596 *  stack.
597 */
598SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
599
600/**
601 *  @ingroup CPUInterrupt
602 *  This variable points to the lowest physical address of the interrupt
603 *  stack.
604 */
605SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
606
607/*
608 *  Nothing prevents the porter from declaring more CPU specific variables.
609 *
610 *  Port Specific Information:
611 *
612 *  XXX document implementation including references if appropriate
613 */
614
615/* XXX: if needed, put more variables here */
616
617/**
618 *  @ingroup CPUContext
619 *  The size of the floating point context area.  On some CPUs this
620 *  will not be a "sizeof" because the format of the floating point
621 *  area is not defined -- only the size is.  This is usually on
622 *  CPUs with a "floating point save context" instruction.
623 *
624 *  Port Specific Information:
625 *
626 *  XXX document implementation including references if appropriate
627 */
628#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
629
630/**
631 *  Amount of extra stack (above minimum stack size) required by
632 *  MPCI receive server thread.  Remember that in a multiprocessor
633 *  system this thread must exist and be able to process all directives.
634 *
635 *  Port Specific Information:
636 *
637 *  XXX document implementation including references if appropriate
638 */
639#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
640
641/**
642 *  @ingroup CPUInterrupt
643 *  This defines the number of entries in the @ref _ISR_Vector_table managed
644 *  by RTEMS.
645 *
646 *  Port Specific Information:
647 *
648 *  XXX document implementation including references if appropriate
649 */
650#define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
651
652/**
653 *  @ingroup CPUInterrupt
654 *  This defines the highest interrupt vector number for this port.
655 */
656#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
657
658/**
659 *  @ingroup CPUInterrupt
660 *  This is defined if the port has a special way to report the ISR nesting
661 *  level.  Most ports maintain the variable @a _ISR_Nest_level.
662 */
663#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
664
665/**
666 *  @ingroup CPUContext
667 *  Should be large enough to run all RTEMS tests.  This ensures
668 *  that a "reasonable" small application should not have any problems.
669 *
670 *  Port Specific Information:
671 *
672 *  XXX document implementation including references if appropriate
673 */
674#define CPU_STACK_MINIMUM_SIZE          (1024*4)
675/* kawk: was *4 */
676
677/**
678 *  CPU's worst alignment requirement for data types on a byte boundary.  This
679 *  alignment does not take into account the requirements for the stack.
680 *
681 *  Port Specific Information:
682 *
683 *  XXX document implementation including references if appropriate
684 */
685#define CPU_ALIGNMENT              4
686
687/**
688 *  This number corresponds to the byte alignment requirement for the
689 *  heap handler.  This alignment requirement may be stricter than that
690 *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
691 *  common for the heap to follow the same alignment requirement as
692 *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
693 *  the heap, then this should be set to @ref CPU_ALIGNMENT.
694 *
695 *  @note  This does not have to be a power of 2 although it should be
696 *         a multiple of 2 greater than or equal to 2.  The requirement
697 *         to be a multiple of 2 is because the heap uses the least
698 *         significant field of the front and back flags to indicate
699 *         that a block is in use or free.  So you do not want any odd
700 *         length blocks really putting length data in that bit.
701 *
702 *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
703 *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
704 *         elements allocated from the heap meet all restrictions.
705 *
706 *  Port Specific Information:
707 *
708 *  XXX document implementation including references if appropriate
709 */
710#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
711
712/**
713 *  This number corresponds to the byte alignment requirement for memory
714 *  buffers allocated by the partition manager.  This alignment requirement
715 *  may be stricter than that for the data types alignment specified by
716 *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
717 *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
718 *  strict enough for the partition, then this should be set to
719 *  @ref CPU_ALIGNMENT.
720 *
721 *  @note  This does not have to be a power of 2.  It does have to
722 *         be greater or equal to than @ref CPU_ALIGNMENT.
723 *
724 *  Port Specific Information:
725 *
726 *  XXX document implementation including references if appropriate
727 */
728#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
729
730/**
731 *  This number corresponds to the byte alignment requirement for the
732 *  stack.  This alignment requirement may be stricter than that for the
733 *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
734 *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
735 *  set to 0.
736 *
737 *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
738 *
739 *  Port Specific Information:
740 *
741 *  XXX document implementation including references if appropriate
742 */
743#define CPU_STACK_ALIGNMENT        0
744
745/*
746 *  ISR handler macros
747 */
748
749/**
750 *  @ingroup CPUInterrupt
751 *  Support routine to initialize the RTEMS vector table after it is allocated.
752 *
753 *  Port Specific Information:
754 *
755 *  XXX document implementation including references if appropriate
756 */
757#define _CPU_Initialize_vectors()
758
759/**
760 *  @ingroup CPUInterrupt
761 *  Disable all interrupts for an RTEMS critical section.  The previous
762 *  level is returned in @a _isr_cookie.
763 *
764 *  @param _isr_cookie (out) will contain the previous level cookie
765 *
766 *  Port Specific Information:
767 *
768 *  XXX document implementation including references if appropriate
769 */
770#define _CPU_ISR_Disable( _isr_cookie ) \
771  { \
772    _isr_cookie = __builtin_rdctl(0); /* read status register */ \
773    __builtin_wrctl(0, 0); /* write 0 to status register */ \
774  }
775
776/**
777 *  @ingroup CPUInterrupt
778 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
779 *  This indicates the end of an RTEMS critical section.  The parameter
780 *  @a _isr_cookie is not modified.
781 *
782 *  @param _isr_cookie (in) contain the previous level cookie
783 *
784 *  Port Specific Information:
785 *
786 *  XXX document implementation including references if appropriate
787 */
788#define _CPU_ISR_Enable( _isr_cookie )  \
789  { \
790    __builtin_wrctl( 0, _isr_cookie ); \
791  }
792
793/**
794 *  @ingroup CPUInterrupt
795 *  This temporarily restores the interrupt to @a _isr_cookie before immediately
796 *  disabling them again.  This is used to divide long RTEMS critical
797 *  sections into two or more parts.  The parameter @a _isr_cookie is not
798 *  modified.
799 *
800 *  @param _isr_cookie (in) contain the previous level cookie
801 *
802 *  Port Specific Information:
803 *
804 *  XXX document implementation including references if appropriate
805 */
806#define _CPU_ISR_Flash( _isr_cookie ) \
807  { \
808    __builtin_wrctl( 0, _isr_cookie ); \
809    /* TODO: Does NIOS2 get a chance to \
810    process IRQ between these statements? */ \
811    __builtin_wrctl( 0, 0 ); \
812  }
813
814/**
815 *  @ingroup CPUInterrupt
816 *
817 *  This routine and @ref _CPU_ISR_Get_level
818 *  Map the interrupt level in task mode onto the hardware that the CPU
819 *  actually provides.  Currently, interrupt levels which do not
820 *  map onto the CPU in a generic fashion are undefined.  Someday,
821 *  it would be nice if these were "mapped" by the application
822 *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
823 *  8 - 255 would be available for bsp/application specific meaning.
824 *  This could be used to manage a programmable interrupt controller
825 *  via the rtems_task_mode directive.
826 *
827 *  Port Specific Information:
828 *
829 *  XXX document implementation including references if appropriate
830 */
831#define _CPU_ISR_Set_level( new_level ) \
832        _CPU_ISR_Enable( ( new_level==0 ) ? 1 : 0 );
833
834/**
835 *  @ingroup CPUInterrupt
836 *  Return the current interrupt disable level for this task in
837 *  the format used by the interrupt level portion of the task mode.
838 *
839 *  @note This routine usually must be implemented as a subroutine.
840 *
841 *  Port Specific Information:
842 *
843 *  XXX document implementation including references if appropriate
844 */
845uint32_t   _CPU_ISR_Get_level( void );
846
847/* end of ISR handler macros */
848
849/* Context handler macros */
850
851/**
852 *  @ingroup CPUContext
853 *  Initialize the context to a state suitable for starting a
854 *  task after a context restore operation.  Generally, this
855 *  involves:
856 *
857 *     - setting a starting address
858 *     - preparing the stack
859 *     - preparing the stack and frame pointers
860 *     - setting the proper interrupt level in the context
861 *     - initializing the floating point context
862 *
863 *  This routine generally does not set any unnecessary register
864 *  in the context.  The state of the "general data" registers is
865 *  undefined at task start time.
866 *
867 *  @param _the_context (in) is the context structure to be initialized
868 *  @param _stack_base (in) is the lowest physical address of this task's stack
869 *  @param _size (in) is the size of this task's stack
870 *  @param _isr (in) is the interrupt disable level
871 *  @param _entry_point (in) is the thread's entry point.  This is
872 *         always @a _Thread_Handler
873 *  @param _is_fp (in) is TRUE if the thread is to be a floating
874 *        point thread.  This is typically only used on CPUs where the
875 *        FPU may be easily disabled by software such as on the SPARC
876 *        where the PSR contains an enable FPU bit.
877 *
878 *  Port Specific Information:
879 *
880 *  XXX document implementation including references if appropriate
881 */
882#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
883                                 _isr, _entry_point, _is_fp ) \
884   do { \
885     extern char _gp[]; \
886     uint32_t _stack = (uint32_t)(_stack_base) + (_size) - 4; \
887     (_the_context)->gp = (void *)_gp; \
888     (_the_context)->fp = (void *)_stack; \
889     (_the_context)->sp = (void *)_stack; \
890     (_the_context)->ra = (void *)(_entry_point); \
891     (_the_context)->status  = 0x1; /* IRQs enabled */ \
892   } while ( 0 )
893
894/*
895 *  This routine is responsible for somehow restarting the currently
896 *  executing task.  If you are lucky, then all that is necessary
897 *  is restoring the context.  Otherwise, there will need to be
898 *  a special assembly routine which does something special in this
899 *  case.  @ref _CPU_Context_Restore should work most of the time.  It will
900 *  not work if restarting self conflicts with the stack frame
901 *  assumptions of restoring a context.
902 *
903 *  Port Specific Information:
904 *
905 *  XXX document implementation including references if appropriate
906 */
907#define _CPU_Context_Restart_self( _the_context ) \
908   _CPU_Context_restore( (_the_context) );
909
910/**
911 *  @ingroup CPUContext
912 *  The purpose of this macro is to allow the initial pointer into
913 *  a floating point context area (used to save the floating point
914 *  context) to be at an arbitrary place in the floating point
915 *  context area.
916 *
917 *  This is necessary because some FP units are designed to have
918 *  their context saved as a stack which grows into lower addresses.
919 *  Other FP units can be saved by simply moving registers into offsets
920 *  from the base of the context area.  Finally some FP units provide
921 *  a "dump context" instruction which could fill in from high to low
922 *  or low to high based on the whim of the CPU designers.
923 *
924 *  @param _base (in) is the lowest physical address of the floating point
925 *         context area
926 *  @param _offset (in) is the offset into the floating point area
927 *
928 *  Port Specific Information:
929 *
930 *  XXX document implementation including references if appropriate
931 */
932#if 1
933#define _CPU_Context_Fp_start( _base, _offset )
934#else
935#define _CPU_Context_Fp_start( _base, _offset ) \
936   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
937#endif
938
939/**
940 *  This routine initializes the FP context area passed to it to.
941 *  There are a few standard ways in which to initialize the
942 *  floating point context.  The code included for this macro assumes
943 *  that this is a CPU in which a "initial" FP context was saved into
944 *  @a _CPU_Null_fp_context and it simply copies it to the destination
945 *  context passed to it.
946 *
947 *  Other floating point context save/restore models include:
948 *    -# not doing anything, and
949 *    -# putting a "null FP status word" in the correct place in the FP context.
950 *
951 *  @param _destination (in) is the floating point context area
952 *
953 *  Port Specific Information:
954 *
955 *  XXX document implementation including references if appropriate
956 */
957#if 1
958#define _CPU_Context_Initialize_fp( _destination )
959#else
960#define _CPU_Context_Initialize_fp( _destination ) \
961  { \
962   *(*(_destination)) = _CPU_Null_fp_context; \
963  }
964#endif
965
966/* end of Context handler macros */
967
968/* Fatal Error manager macros */
969
970/**
971 *  This routine copies _error into a known place -- typically a stack
972 *  location or a register, optionally disables interrupts, and
973 *  halts/stops the CPU.
974 *
975 *  Port Specific Information:
976 *
977 *  XXX document implementation including references if appropriate
978 */
979#define _CPU_Fatal_halt( _error ) \
980  { \
981    __builtin_wrctl(0, 0); /* write 0 to status register (disable interrupts) */ \
982    __asm volatile ("mov et, %z0" : : "rM" (_error)); /* write error code to ET register */ \
983    for(;;); \
984  }
985
986/* end of Fatal Error manager macros */
987
988/* Bitfield handler macros */
989
990/**
991 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
992 *
993 *  This set of routines are used to implement fast searches for
994 *  the most important ready task.
995 */
996
997/**
998 *  @ingroup CPUBitfield
999 *  This definition is set to TRUE if the port uses the generic bitfield
1000 *  manipulation implementation.
1001 */
1002#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
1003
1004/**
1005 *  @ingroup CPUBitfield
1006 *  This definition is set to TRUE if the port uses the data tables provided
1007 *  by the generic bitfield manipulation implementation.
1008 *  This can occur when actually using the generic bitfield manipulation
1009 *  implementation or when implementing the same algorithm in assembly
1010 *  language for improved performance.  It is unlikely that a port will use
1011 *  the data if it has a bitfield scan instruction.
1012 */
1013#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
1014
1015/**
1016 *  @ingroup CPUBitfield
1017 *  This routine sets @a _output to the bit number of the first bit
1018 *  set in @a _value.  @a _value is of CPU dependent type
1019 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
1020 *  wide although only the 16 least significant bits will be used.
1021 *
1022 *  There are a number of variables in using a "find first bit" type
1023 *  instruction.
1024 *
1025 *    -# What happens when run on a value of zero?
1026 *    -# Bits may be numbered from MSB to LSB or vice-versa.
1027 *    -# The numbering may be zero or one based.
1028 *    -# The "find first bit" instruction may search from MSB or LSB.
1029 *
1030 *  RTEMS guarantees that (1) will never happen so it is not a concern.
1031 *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
1032 *  @ref _CPU_Priority_bits_index.  These three form a set of routines
1033 *  which must logically operate together.  Bits in the _value are
1034 *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
1035 *  The basic major and minor values calculated by @ref _Priority_Major
1036 *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
1037 *  to properly range between the values returned by the "find first bit"
1038 *  instruction.  This makes it possible for @ref _Priority_Get_highest to
1039 *  calculate the major and directly index into the minor table.
1040 *  This mapping is necessary to ensure that 0 (a high priority major/minor)
1041 *  is the first bit found.
1042 *
1043 *  This entire "find first bit" and mapping process depends heavily
1044 *  on the manner in which a priority is broken into a major and minor
1045 *  components with the major being the 4 MSB of a priority and minor
1046 *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
1047 *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
1048 *  to the lowest priority.
1049 *
1050 *  If your CPU does not have a "find first bit" instruction, then
1051 *  there are ways to make do without it.  Here are a handful of ways
1052 *  to implement this in software:
1053 *
1054@verbatim
1055      - a series of 16 bit test instructions
1056      - a "binary search using if's"
1057      - _number = 0
1058        if _value > 0x00ff
1059          _value >>=8
1060          _number = 8;
1061 
1062        if _value > 0x0000f
1063          _value >=8
1064          _number += 4
1065 
1066        _number += bit_set_table[ _value ]
1067@endverbatim
1068 
1069 *    where bit_set_table[ 16 ] has values which indicate the first
1070 *      bit set
1071 *
1072 *  @param _value (in) is the value to be scanned
1073 *  @param _output (in) is the first bit set
1074 *
1075 *  Port Specific Information:
1076 *
1077 *  XXX document implementation including references if appropriate
1078 */
1079
1080#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1081#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
1082  { \
1083    (_output) = 0;   /* do something to prevent warnings */ \
1084  }
1085#endif
1086
1087/* end of Bitfield handler macros */
1088
1089/**
1090 *  This routine builds the mask which corresponds to the bit fields
1091 *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
1092 *  for that routine.
1093 *
1094 *  Port Specific Information:
1095 *
1096 *  XXX document implementation including references if appropriate
1097 */
1098#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1099
1100#define _CPU_Priority_Mask( _bit_number ) \
1101  ( 1 << (_bit_number) )
1102
1103#endif
1104
1105/**
1106 *  @ingroup CPUBitfield
1107 *  This routine translates the bit numbers returned by
1108 *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
1109 *  a major or minor component of a priority.  See the discussion
1110 *  for that routine.
1111 *
1112 *  @param _priority (in) is the major or minor number to translate
1113 *
1114 *  Port Specific Information:
1115 *
1116 *  XXX document implementation including references if appropriate
1117 */
1118#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
1119
1120#define _CPU_Priority_bits_index( _priority ) \
1121  (_priority)
1122
1123#endif
1124
1125/* end of Priority handler macros */
1126
1127/* functions */
1128
1129/**
1130 *  This routine performs CPU dependent initialization.
1131 *
1132 *  Port Specific Information:
1133 *
1134 *  XXX document implementation including references if appropriate
1135 */
1136void _CPU_Initialize(void);
1137
1138/**
1139 *  @ingroup CPUInterrupt
1140 *  This routine installs a "raw" interrupt handler directly into the
1141 *  processor's vector table.
1142 *
1143 *  @param vector (in) is the vector number
1144 *  @param new_handler (in) is the raw ISR handler to install
1145 *  @param old_handler (in) is the previously installed ISR Handler
1146 *
1147 *  Port Specific Information:
1148 *
1149 *  XXX document implementation including references if appropriate
1150 */
1151void _CPU_ISR_install_raw_handler(
1152  uint32_t    vector,
1153  proc_ptr    new_handler,
1154  proc_ptr   *old_handler
1155);
1156
1157/**
1158 *  @ingroup CPUInterrupt
1159 *  This routine installs an interrupt vector.
1160 *
1161 *  @param vector (in) is the vector number
1162 *  @param new_handler (in) is the RTEMS ISR handler to install
1163 *  @param old_handler (in) is the previously installed ISR Handler
1164 *
1165 *  Port Specific Information:
1166 *
1167 *  XXX document implementation including references if appropriate
1168 */
1169void _CPU_ISR_install_vector(
1170  uint32_t    vector,
1171  proc_ptr    new_handler,
1172  proc_ptr   *old_handler
1173);
1174
1175/**
1176 *  @ingroup CPUInterrupt
1177 *  This routine installs the hardware interrupt stack pointer.
1178 *
1179 *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
1180 *         is TRUE.
1181 *
1182 *  Port Specific Information:
1183 *
1184 *  XXX document implementation including references if appropriate
1185 */
1186void _CPU_Install_interrupt_stack( void );
1187
1188/**
1189 *  This routine is the CPU dependent IDLE thread body.
1190 *
1191 *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
1192 *         is TRUE.
1193 *
1194 *  Port Specific Information:
1195 *
1196 *  XXX document implementation including references if appropriate
1197 */
1198void *_CPU_Thread_Idle_body( uint32_t );
1199
1200/**
1201 *  @ingroup CPUContext
1202 *  This routine switches from the run context to the heir context.
1203 *
1204 *  @param run (in) points to the context of the currently executing task
1205 *  @param heir (in) points to the context of the heir task
1206 *
1207 *  Port Specific Information:
1208 *
1209 *  XXX document implementation including references if appropriate
1210 */
1211void _CPU_Context_switch(
1212  Context_Control  *run,
1213  Context_Control  *heir
1214);
1215
1216/**
1217 *  @ingroup CPUContext
1218 *  This routine is generally used only to restart self in an
1219 *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
1220 *
1221 *  @param new_context (in) points to the context to be restored.
1222 *
1223 *  @note May be unnecessary to reload some registers.
1224 *
1225 *  Port Specific Information:
1226 *
1227 *  XXX document implementation including references if appropriate
1228 */
1229void _CPU_Context_restore(
1230  Context_Control *new_context
1231);
1232
1233/**
1234 *  @ingroup CPUContext
1235 *  This routine saves the floating point context passed to it.
1236 *
1237 *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
1238 *  point context area
1239 *
1240 *  @return on output @a *fp_context_ptr will contain the address that
1241 *  should be used with @ref _CPU_Context_restore_fp to restore this context.
1242 *
1243 *  Port Specific Information:
1244 *
1245 *  XXX document implementation including references if appropriate
1246 */
1247void _CPU_Context_save_fp(
1248  Context_Control_fp **fp_context_ptr
1249);
1250
1251/**
1252 *  @ingroup CPUContext
1253 *  This routine restores the floating point context passed to it.
1254 *
1255 *  @param fp_context_ptr (in) is a pointer to a pointer to a floating
1256 *  point context area to restore
1257 *
1258 *  @return on output @a *fp_context_ptr will contain the address that
1259 *  should be used with @ref _CPU_Context_save_fp to save this context.
1260 *
1261 *  Port Specific Information:
1262 *
1263 *  XXX document implementation including references if appropriate
1264 */
1265void _CPU_Context_restore_fp(
1266  Context_Control_fp **fp_context_ptr
1267);
1268
1269/**
1270 *  @ingroup CPUEndian
1271 *  The following routine swaps the endian format of an unsigned int.
1272 *  It must be static because it is referenced indirectly.
1273 *
1274 *  This version will work on any processor, but if there is a better
1275 *  way for your CPU PLEASE use it.  The most common way to do this is to:
1276 *
1277 *     swap least significant two bytes with 16-bit rotate
1278 *     swap upper and lower 16-bits
1279 *     swap most significant two bytes with 16-bit rotate
1280 *
1281 *  Some CPUs have special instructions which swap a 32-bit quantity in
1282 *  a single instruction (e.g. i486).  It is probably best to avoid
1283 *  an "endian swapping control bit" in the CPU.  One good reason is
1284 *  that interrupts would probably have to be disabled to insure that
1285 *  an interrupt does not try to access the same "chunk" with the wrong
1286 *  endian.  Another good reason is that on some CPUs, the endian bit
1287 *  endianness for ALL fetches -- both code and data -- so the code
1288 *  will be fetched incorrectly.
1289 *
1290 *  @param value (in) is the value to be swapped
1291 *  @return the value after being endian swapped
1292 *
1293 *  Port Specific Information:
1294 *
1295 *  XXX document implementation including references if appropriate
1296 */
1297static inline uint32_t CPU_swap_u32(
1298  uint32_t value
1299)
1300{
1301  uint32_t   byte1, byte2, byte3, byte4, swapped;
1302 
1303  byte4 = (value >> 24) & 0xff;
1304  byte3 = (value >> 16) & 0xff;
1305  byte2 = (value >> 8)  & 0xff;
1306  byte1 =  value        & 0xff;
1307 
1308  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
1309  return( swapped );
1310}
1311
1312/**
1313 *  @ingroup CPUEndian
1314 *  This routine swaps a 16 bir quantity.
1315 *
1316 *  @param value (in) is the value to be swapped
1317 *  @return the value after being endian swapped
1318 */
1319#define CPU_swap_u16( value ) \
1320  (((value&0xff) << 8) | ((value >> 8)&0xff))
1321
1322#ifdef __cplusplus
1323}
1324#endif
1325
1326#endif
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