source: rtems/cpukit/score/cpu/nios2/rtems/score/cpu.h @ 815994f

4.11
Last change on this file since 815994f was 815994f, checked in by Sebastian Huber <sebastian.huber@…>, on Nov 25, 2012 at 4:48:11 PM

score: Add CPU_Exception_frame

Add CPU port type CPU_Exception_frame and function
_CPU_Exception_frame_print().

The CPU ports of avr, bfin, h8300, lm32, m32c, m32r, m68k, nios2, sh,
sparc64, and v850 use an empty default implementation of
_CPU_Exception_frame_print().

Add rtems_exception_frame and rtems_exception_frame_print().

Add RTEMS_FATAL_SOURCE_EXCEPTION for CPU exceptions. Use rtems_fatal()
with source RTEMS_FATAL_SOURCE_EXCEPTION in CPU ports of i386, powerpc,
and sparc for unexpected exceptions.

Add third parameter to RTEMS_BSP_CLEANUP_OPTIONS() which controls the
BSP_PRINT_EXCEPTION_CONTEXT define used in the default
bsp_fatal_extension().

Add test sptests/spfatal26.

  • Property mode set to 100644
File size: 9.3 KB
Line 
1/*
2 *  Copyright (c) 2011 embedded brains GmbH
3 *
4 *  Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de)
5 *
6 *  COPYRIGHT (c) 1989-2004.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.rtems.com/license/LICENSE.
12 */
13
14#ifndef _RTEMS_SCORE_CPU_H
15#define _RTEMS_SCORE_CPU_H
16
17#ifdef __cplusplus
18extern "C" {
19#endif
20
21#include <rtems/score/types.h>
22#include <rtems/score/nios2.h>
23
24/*
25 * TODO: Run the timing tests and figure out what is better.
26 */
27#define CPU_INLINE_ENABLE_DISPATCH FALSE
28
29/*
30 * TODO: Run the timing tests and figure out what is better.
31 */
32#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE
33
34#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
35
36#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
37
38#define CPU_INTERRUPT_NUMBER_OF_VECTORS 32
39
40#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
41
42#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
43
44#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
45
46#define CPU_ALLOCATE_INTERRUPT_STACK TRUE
47
48#define CPU_ISR_PASSES_FRAME_POINTER 1
49
50#define CPU_HARDWARE_FP FALSE
51
52#define CPU_SOFTWARE_FP FALSE
53
54#define CPU_CONTEXT_FP_SIZE 0
55
56#define CPU_ALL_TASKS_ARE_FP FALSE
57
58#define CPU_IDLE_TASK_IS_FP FALSE
59
60#define CPU_USE_DEFERRED_FP_SWITCH FALSE
61
62#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE
63
64#define CPU_STACK_GROWS_UP FALSE
65
66#define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32)))
67
68#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
69
70#define CPU_BIG_ENDIAN FALSE
71
72#define CPU_LITTLE_ENDIAN TRUE
73
74#define CPU_STACK_MINIMUM_SIZE (4 * 1024)
75
76#define CPU_SIZEOF_POINTER 4
77
78/*
79 * Alignment value according to "Nios II Processor Reference" chapter 7
80 * "Application Binary Interface" section "Memory Alignment".
81 */
82#define CPU_ALIGNMENT 4
83
84#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT
85
86#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
87
88/*
89 * Alignment value according to "Nios II Processor Reference" chapter 7
90 * "Application Binary Interface" section "Stacks".
91 */
92#define CPU_STACK_ALIGNMENT 4
93
94/*
95 * A Nios II configuration with an external interrupt controller (EIC) supports
96 * up to 64 interrupt levels.  A Nios II configuration with an internal
97 * interrupt controller (IIC) has only two interrupt levels (enabled and
98 * disabled).  The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
99 * take care about configuration specific mappings.
100 */
101#define CPU_MODES_INTERRUPT_MASK 0x3f
102
103#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
104
105#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
106
107#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
108
109#ifndef ASM
110
111/**
112 * @brief Thread register context.
113 *
114 * The thread register context covers the non-volatile registers, the thread
115 * stack pointer, the return address, and the processor status.
116 *
117 * There is no need to save the global pointer (gp) since it is a system wide
118 * constant and set-up with the C runtime environment.
119 *
120 * The @a thread_dispatch_disabled field is used for the external interrupt
121 * controller (EIC) support.
122 *
123 * @see _Nios2_Thread_dispatch_disabled
124 */
125typedef struct {
126  uint32_t r16;
127  uint32_t r17;
128  uint32_t r18;
129  uint32_t r19;
130  uint32_t r20;
131  uint32_t r21;
132  uint32_t r22;
133  uint32_t r23;
134  uint32_t fp;
135  uint32_t status;
136  uint32_t sp;
137  uint32_t ra;
138  uint32_t thread_dispatch_disabled;
139  uint32_t stack_mpubase;
140  uint32_t stack_mpuacc;
141} Context_Control;
142
143#define _CPU_Context_Get_SP( _context ) \
144  (_context)->sp
145
146typedef struct {
147  uint32_t r1;
148  uint32_t r2;
149  uint32_t r3;
150  uint32_t r4;
151  uint32_t r5;
152  uint32_t r6;
153  uint32_t r7;
154  uint32_t r8;
155  uint32_t r9;
156  uint32_t r10;
157  uint32_t r11;
158  uint32_t r12;
159  uint32_t r13;
160  uint32_t r14;
161  uint32_t r15;
162  uint32_t ra;
163  uint32_t gp;
164  uint32_t et;
165  uint32_t ea;
166} CPU_Interrupt_frame;
167
168typedef struct {
169  uint32_t r1;
170  uint32_t r2;
171  uint32_t r3;
172  uint32_t r4;
173  uint32_t r5;
174  uint32_t r6;
175  uint32_t r7;
176  uint32_t r8;
177  uint32_t r9;
178  uint32_t r10;
179  uint32_t r11;
180  uint32_t r12;
181  uint32_t r13;
182  uint32_t r14;
183  uint32_t r15;
184  uint32_t r16;
185  uint32_t r17;
186  uint32_t r18;
187  uint32_t r19;
188  uint32_t r20;
189  uint32_t r21;
190  uint32_t r22;
191  uint32_t r23;
192  uint32_t gp;
193  uint32_t fp;
194  uint32_t sp;
195  uint32_t ra;
196  uint32_t et;
197  uint32_t ea;
198  uint32_t status;
199  uint32_t ienable;
200  uint32_t ipending;
201} CPU_Exception_frame;
202
203void _CPU_Initialize_vectors( void );
204
205/**
206 * @brief Macro to disable interrupts.
207 *
208 * The processor status before disabling the interrupts will be stored in
209 * @a _isr_cookie.  This value will be used in _CPU_ISR_Flash() and
210 * _CPU_ISR_Enable().
211 *
212 * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in
213 * the status register representing the interrupt level.  The global symbol
214 * _Nios2_ISR_Status_bits will be used to set the bits representing an
215 * interrupt level that disables interrupts.  Both global symbols must be
216 * provided by the board support package.
217 *
218 * In case the Nios II uses the internal interrupt controller (IIC), then only
219 * the PIE status bit is used.
220 *
221 * In case the Nios II uses the external interrupt controller (EIC), then the
222 * RSIE status bit or the IL status field is used depending on the interrupt
223 * handling variant and the shadow register usage.
224 */
225#define _CPU_ISR_Disable( _isr_cookie ) \
226  do { \
227    int _tmp; \
228    __asm__ volatile ( \
229      "rdctl %0, status\n" \
230      "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
231      "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
232      "and %1, %0, %1\n" \
233      "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
234      "wrctl status, %1" \
235      : "=&r" (_isr_cookie), "=&r" (_tmp) \
236    ); \
237  } while ( 0 )
238
239/**
240 * @brief Macro to restore the processor status.
241 *
242 * The @a _isr_cookie must contain the processor status returned by
243 * _CPU_ISR_Disable().  The value is not modified.
244 */
245#define _CPU_ISR_Enable( _isr_cookie ) \
246  __builtin_wrctl( 0, (int) _isr_cookie )
247
248/**
249 * @brief Macro to restore the processor status and disable the interrupts
250 * again.
251 *
252 * The @a _isr_cookie must contain the processor status returned by
253 * _CPU_ISR_Disable().  The value is not modified.
254 *
255 * This flash code is optimal for all Nios II configurations.  The rdctl does
256 * not flush the pipeline and has only a late result penalty.  The wrctl on the
257 * other hand leads to a pipeline flush.
258 */
259#define _CPU_ISR_Flash( _isr_cookie ) \
260  do { \
261    int _status = __builtin_rdctl( 0 ); \
262    __builtin_wrctl( 0, (int) _isr_cookie ); \
263    __builtin_wrctl( 0, _status ); \
264  } while ( 0 )
265
266/**
267 * @brief Sets the interrupt level for the executing thread.
268 *
269 * The valid values of @a new_level depend on the Nios II configuration.  A
270 * value of zero represents enabled interrupts in all configurations.
271 *
272 * @see _CPU_ISR_Get_level()
273 */
274void _CPU_ISR_Set_level( uint32_t new_level );
275
276/**
277 * @brief Returns the interrupt level of the executing thread.
278 *
279 * @retval 0 Interrupts are enabled.
280 * @retval otherwise The value depends on the Nios II configuration.  In case
281 * of an internal interrupt controller (IIC) the only valid value is one which
282 * indicates disabled interrupts.  In case of an external interrupt controller
283 * (EIC) there are two possibilities.  Firstly if the RSIE status bit is used
284 * to disable interrupts, then one is the only valid value indicating disabled
285 * interrupts.  Secondly if the IL status field is used to disable interrupts,
286 * then this value will be returned.  Interrupts are disabled at the maximum
287 * level specified by the _Nios2_ISR_Status_bits.
288 */
289uint32_t _CPU_ISR_Get_level( void );
290
291/**
292 * @brief Initializes the CPU context.
293 *
294 * The following steps are performed:
295 *  - setting a starting address
296 *  - preparing the stack
297 *  - preparing the stack and frame pointers
298 *  - setting the proper interrupt level in the context
299 *
300 * @param[in] context points to the context area
301 * @param[in] stack_area_begin is the low address of the allocated stack area
302 * @param[in] stack_area_size is the size of the stack area in bytes
303 * @param[in] new_level is the interrupt level for the task
304 * @param[in] entry_point is the task's entry point
305 * @param[in] is_fp is set to @c true if the task is a floating point task
306 */
307void _CPU_Context_Initialize(
308  Context_Control *context,
309  void *stack_area_begin,
310  size_t stack_area_size,
311  uint32_t new_level,
312  void (*entry_point)( void ),
313  bool is_fp
314);
315
316#define _CPU_Context_Restart_self( _the_context ) \
317  _CPU_Context_restore( (_the_context) );
318
319void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
320
321void _CPU_Initialize( void );
322
323void _CPU_ISR_install_raw_handler(
324  uint32_t vector,
325  proc_ptr new_handler,
326  proc_ptr *old_handler
327);
328
329void _CPU_ISR_install_vector(
330  uint32_t vector,
331  proc_ptr new_handler,
332  proc_ptr *old_handler
333);
334
335void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
336
337void _CPU_Context_restore(
338  Context_Control *new_context
339) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
340
341void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
342
343static inline uint32_t CPU_swap_u32( uint32_t value )
344{
345  uint32_t byte1, byte2, byte3, byte4, swapped;
346
347  byte4 = (value >> 24) & 0xff;
348  byte3 = (value >> 16) & 0xff;
349  byte2 = (value >> 8)  & 0xff;
350  byte1 =  value        & 0xff;
351
352  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
353
354  return swapped;
355}
356
357#define CPU_swap_u16( value ) \
358  (((value&0xff) << 8) | ((value >> 8)&0xff))
359
360#endif /* ASM */
361
362#ifdef __cplusplus
363}
364#endif
365
366#endif
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