[4f5740f] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief Altera Nios II CPU Department Source |
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| 5 | */ |
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| 6 | |
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[7a28ac8] | 7 | /* |
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[2a5880f1] | 8 | * Copyright (c) 2011 embedded brains GmbH |
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[7a28ac8] | 9 | * |
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[2a5880f1] | 10 | * Copyright (c) 2006 Kolja Waschk (rtemsdev/ixo.de) |
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[80f7732] | 11 | * |
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[2a5880f1] | 12 | * COPYRIGHT (c) 1989-2004. |
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[7a28ac8] | 13 | * On-Line Applications Research Corporation (OAR). |
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| 14 | * |
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| 15 | * The license and distribution terms for this file may be |
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| 16 | * found in the file LICENSE in this distribution or at |
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[c499856] | 17 | * http://www.rtems.org/license/LICENSE. |
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[7a28ac8] | 18 | */ |
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| 19 | |
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| 20 | #ifndef _RTEMS_SCORE_CPU_H |
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| 21 | #define _RTEMS_SCORE_CPU_H |
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| 22 | |
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| 23 | #ifdef __cplusplus |
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| 24 | extern "C" { |
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| 25 | #endif |
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| 26 | |
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| 27 | #include <rtems/score/types.h> |
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[89b85e51] | 28 | #include <rtems/score/nios2.h> |
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[7a28ac8] | 29 | |
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[2a5880f1] | 30 | /* |
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| 31 | * TODO: Run the timing tests and figure out what is better. |
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[7a28ac8] | 32 | */ |
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[2a5880f1] | 33 | #define CPU_INLINE_ENABLE_DISPATCH FALSE |
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[7a28ac8] | 34 | |
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[2a5880f1] | 35 | /* |
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| 36 | * TODO: Run the timing tests and figure out what is better. |
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[7a28ac8] | 37 | */ |
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[2a5880f1] | 38 | #define CPU_UNROLL_ENQUEUE_PRIORITY TRUE |
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[7a28ac8] | 39 | |
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| 40 | #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE |
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| 41 | |
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| 42 | #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE |
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| 43 | |
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[2a5880f1] | 44 | #define CPU_INTERRUPT_NUMBER_OF_VECTORS 32 |
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| 45 | |
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| 46 | #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) |
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| 47 | |
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[e2d0c68] | 48 | #define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE |
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[2a5880f1] | 49 | |
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[7a28ac8] | 50 | #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE |
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| 51 | |
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| 52 | #define CPU_ALLOCATE_INTERRUPT_STACK TRUE |
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| 53 | |
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[8b94c03] | 54 | #define CPU_ISR_PASSES_FRAME_POINTER FALSE |
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[7a28ac8] | 55 | |
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[2a5880f1] | 56 | #define CPU_HARDWARE_FP FALSE |
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[7a28ac8] | 57 | |
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[2a5880f1] | 58 | #define CPU_SOFTWARE_FP FALSE |
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[7a28ac8] | 59 | |
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[2a5880f1] | 60 | #define CPU_CONTEXT_FP_SIZE 0 |
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[7a28ac8] | 61 | |
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[2a5880f1] | 62 | #define CPU_ALL_TASKS_ARE_FP FALSE |
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[7a28ac8] | 63 | |
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[2a5880f1] | 64 | #define CPU_IDLE_TASK_IS_FP FALSE |
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[7a28ac8] | 65 | |
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[2a5880f1] | 66 | #define CPU_USE_DEFERRED_FP_SWITCH FALSE |
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[7a28ac8] | 67 | |
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[2a5880f1] | 68 | #define CPU_PROVIDES_IDLE_THREAD_BODY FALSE |
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[7a28ac8] | 69 | |
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[2a5880f1] | 70 | #define CPU_STACK_GROWS_UP FALSE |
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| 71 | |
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[e41cec3] | 72 | #define CPU_STRUCTURE_ALIGNMENT __attribute__((section(".sdata"), aligned(32))) |
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[7a28ac8] | 73 | |
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[9c121991] | 74 | #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE |
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| 75 | |
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[2a5880f1] | 76 | #define CPU_BIG_ENDIAN FALSE |
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[7a28ac8] | 77 | |
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[2a5880f1] | 78 | #define CPU_LITTLE_ENDIAN TRUE |
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[7a28ac8] | 79 | |
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[2a5880f1] | 80 | #define CPU_STACK_MINIMUM_SIZE (4 * 1024) |
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[7a28ac8] | 81 | |
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[f1738ed] | 82 | #define CPU_SIZEOF_POINTER 4 |
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| 83 | |
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[7a28ac8] | 84 | /* |
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[2a5880f1] | 85 | * Alignment value according to "Nios II Processor Reference" chapter 7 |
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| 86 | * "Application Binary Interface" section "Memory Alignment". |
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[7a28ac8] | 87 | */ |
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[2a5880f1] | 88 | #define CPU_ALIGNMENT 4 |
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[7a28ac8] | 89 | |
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[2a5880f1] | 90 | #define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT |
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[7a28ac8] | 91 | |
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[2a5880f1] | 92 | #define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT |
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| 93 | |
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[e2d0c68] | 94 | /* |
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| 95 | * Alignment value according to "Nios II Processor Reference" chapter 7 |
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| 96 | * "Application Binary Interface" section "Stacks". |
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| 97 | */ |
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| 98 | #define CPU_STACK_ALIGNMENT 4 |
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[2a5880f1] | 99 | |
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[e2d0c68] | 100 | /* |
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| 101 | * A Nios II configuration with an external interrupt controller (EIC) supports |
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| 102 | * up to 64 interrupt levels. A Nios II configuration with an internal |
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| 103 | * interrupt controller (IIC) has only two interrupt levels (enabled and |
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| 104 | * disabled). The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will |
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| 105 | * take care about configuration specific mappings. |
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| 106 | */ |
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| 107 | #define CPU_MODES_INTERRUPT_MASK 0x3f |
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[2a5880f1] | 108 | |
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| 109 | #define CPU_USE_GENERIC_BITFIELD_CODE TRUE |
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| 110 | |
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| 111 | #define CPU_USE_GENERIC_BITFIELD_DATA TRUE |
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| 112 | |
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| 113 | #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0 |
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| 114 | |
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[10fd4aac] | 115 | #define CPU_PER_CPU_CONTROL_SIZE 0 |
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| 116 | |
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[2a5880f1] | 117 | #ifndef ASM |
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[7a28ac8] | 118 | |
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[10fd4aac] | 119 | typedef struct { |
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| 120 | /* There is no CPU specific per-CPU state */ |
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| 121 | } CPU_Per_CPU_control; |
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| 122 | |
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[7a28ac8] | 123 | /** |
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[40ae1fd] | 124 | * @brief Thread register context. |
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| 125 | * |
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| 126 | * The thread register context covers the non-volatile registers, the thread |
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| 127 | * stack pointer, the return address, and the processor status. |
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| 128 | * |
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| 129 | * There is no need to save the global pointer (gp) since it is a system wide |
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| 130 | * constant and set-up with the C runtime environment. |
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[e2d0c68] | 131 | * |
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| 132 | * The @a thread_dispatch_disabled field is used for the external interrupt |
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| 133 | * controller (EIC) support. |
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| 134 | * |
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| 135 | * @see _Nios2_Thread_dispatch_disabled |
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[7a28ac8] | 136 | */ |
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| 137 | typedef struct { |
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[40ae1fd] | 138 | uint32_t r16; |
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| 139 | uint32_t r17; |
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| 140 | uint32_t r18; |
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| 141 | uint32_t r19; |
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| 142 | uint32_t r20; |
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| 143 | uint32_t r21; |
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| 144 | uint32_t r22; |
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| 145 | uint32_t r23; |
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| 146 | uint32_t fp; |
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[e2d0c68] | 147 | uint32_t status; |
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[40ae1fd] | 148 | uint32_t sp; |
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| 149 | uint32_t ra; |
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[e2d0c68] | 150 | uint32_t thread_dispatch_disabled; |
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[9f1412b9] | 151 | uint32_t stack_mpubase; |
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| 152 | uint32_t stack_mpuacc; |
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[7a28ac8] | 153 | } Context_Control; |
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| 154 | |
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| 155 | #define _CPU_Context_Get_SP( _context ) \ |
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| 156 | (_context)->sp |
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| 157 | |
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[8b94c03] | 158 | typedef void CPU_Interrupt_frame; |
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[7a28ac8] | 159 | |
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| 160 | typedef struct { |
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[2a5880f1] | 161 | uint32_t r1; |
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| 162 | uint32_t r2; |
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| 163 | uint32_t r3; |
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| 164 | uint32_t r4; |
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| 165 | uint32_t r5; |
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| 166 | uint32_t r6; |
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| 167 | uint32_t r7; |
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| 168 | uint32_t r8; |
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| 169 | uint32_t r9; |
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| 170 | uint32_t r10; |
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| 171 | uint32_t r11; |
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| 172 | uint32_t r12; |
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| 173 | uint32_t r13; |
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| 174 | uint32_t r14; |
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| 175 | uint32_t r15; |
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| 176 | uint32_t r16; |
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| 177 | uint32_t r17; |
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| 178 | uint32_t r18; |
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| 179 | uint32_t r19; |
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| 180 | uint32_t r20; |
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| 181 | uint32_t r21; |
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| 182 | uint32_t r22; |
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| 183 | uint32_t r23; |
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| 184 | uint32_t gp; |
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| 185 | uint32_t fp; |
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| 186 | uint32_t sp; |
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| 187 | uint32_t ra; |
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| 188 | uint32_t et; |
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| 189 | uint32_t ea; |
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| 190 | uint32_t status; |
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| 191 | uint32_t ienable; |
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| 192 | uint32_t ipending; |
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[7a28ac8] | 193 | } CPU_Exception_frame; |
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| 194 | |
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[e2d0c68] | 195 | void _CPU_Initialize_vectors( void ); |
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[a385489] | 196 | |
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| 197 | /** |
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[e2d0c68] | 198 | * @brief Macro to disable interrupts. |
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| 199 | * |
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| 200 | * The processor status before disabling the interrupts will be stored in |
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| 201 | * @a _isr_cookie. This value will be used in _CPU_ISR_Flash() and |
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| 202 | * _CPU_ISR_Enable(). |
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| 203 | * |
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| 204 | * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in |
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| 205 | * the status register representing the interrupt level. The global symbol |
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| 206 | * _Nios2_ISR_Status_bits will be used to set the bits representing an |
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| 207 | * interrupt level that disables interrupts. Both global symbols must be |
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| 208 | * provided by the board support package. |
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| 209 | * |
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| 210 | * In case the Nios II uses the internal interrupt controller (IIC), then only |
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| 211 | * the PIE status bit is used. |
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| 212 | * |
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| 213 | * In case the Nios II uses the external interrupt controller (EIC), then the |
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| 214 | * RSIE status bit or the IL status field is used depending on the interrupt |
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| 215 | * handling variant and the shadow register usage. |
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[a385489] | 216 | */ |
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[7a28ac8] | 217 | #define _CPU_ISR_Disable( _isr_cookie ) \ |
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[2a5880f1] | 218 | do { \ |
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[e2d0c68] | 219 | int _tmp; \ |
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| 220 | __asm__ volatile ( \ |
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| 221 | "rdctl %0, status\n" \ |
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| 222 | "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \ |
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| 223 | "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \ |
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| 224 | "and %1, %0, %1\n" \ |
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| 225 | "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \ |
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| 226 | "wrctl status, %1" \ |
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| 227 | : "=&r" (_isr_cookie), "=&r" (_tmp) \ |
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| 228 | ); \ |
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[2a5880f1] | 229 | } while ( 0 ) |
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[7a28ac8] | 230 | |
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[a385489] | 231 | /** |
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[e2d0c68] | 232 | * @brief Macro to restore the processor status. |
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| 233 | * |
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| 234 | * The @a _isr_cookie must contain the processor status returned by |
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| 235 | * _CPU_ISR_Disable(). The value is not modified. |
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[a385489] | 236 | */ |
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[2a5880f1] | 237 | #define _CPU_ISR_Enable( _isr_cookie ) \ |
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[e2d0c68] | 238 | __builtin_wrctl( 0, (int) _isr_cookie ) |
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[7a28ac8] | 239 | |
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[a385489] | 240 | /** |
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[e2d0c68] | 241 | * @brief Macro to restore the processor status and disable the interrupts |
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| 242 | * again. |
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| 243 | * |
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| 244 | * The @a _isr_cookie must contain the processor status returned by |
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| 245 | * _CPU_ISR_Disable(). The value is not modified. |
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| 246 | * |
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| 247 | * This flash code is optimal for all Nios II configurations. The rdctl does |
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[4f5740f] | 248 | * not flush the pipeline and has only a late result penalty. The wrctl on |
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| 249 | * the other hand leads to a pipeline flush. |
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[a385489] | 250 | */ |
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[7a28ac8] | 251 | #define _CPU_ISR_Flash( _isr_cookie ) \ |
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[2a5880f1] | 252 | do { \ |
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[e2d0c68] | 253 | int _status = __builtin_rdctl( 0 ); \ |
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[2a5880f1] | 254 | __builtin_wrctl( 0, (int) _isr_cookie ); \ |
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[e2d0c68] | 255 | __builtin_wrctl( 0, _status ); \ |
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[2a5880f1] | 256 | } while ( 0 ) |
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[7a28ac8] | 257 | |
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[a385489] | 258 | /** |
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[e2d0c68] | 259 | * @brief Sets the interrupt level for the executing thread. |
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| 260 | * |
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| 261 | * The valid values of @a new_level depend on the Nios II configuration. A |
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| 262 | * value of zero represents enabled interrupts in all configurations. |
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| 263 | * |
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| 264 | * @see _CPU_ISR_Get_level() |
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[a385489] | 265 | */ |
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[e2d0c68] | 266 | void _CPU_ISR_Set_level( uint32_t new_level ); |
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[7a28ac8] | 267 | |
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[a385489] | 268 | /** |
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[e2d0c68] | 269 | * @brief Returns the interrupt level of the executing thread. |
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[a385489] | 270 | * |
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[e2d0c68] | 271 | * @retval 0 Interrupts are enabled. |
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| 272 | * @retval otherwise The value depends on the Nios II configuration. In case |
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| 273 | * of an internal interrupt controller (IIC) the only valid value is one which |
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| 274 | * indicates disabled interrupts. In case of an external interrupt controller |
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| 275 | * (EIC) there are two possibilities. Firstly if the RSIE status bit is used |
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| 276 | * to disable interrupts, then one is the only valid value indicating disabled |
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| 277 | * interrupts. Secondly if the IL status field is used to disable interrupts, |
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| 278 | * then this value will be returned. Interrupts are disabled at the maximum |
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| 279 | * level specified by the _Nios2_ISR_Status_bits. |
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[a385489] | 280 | */ |
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[2a5880f1] | 281 | uint32_t _CPU_ISR_Get_level( void ); |
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[7a28ac8] | 282 | |
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[a385489] | 283 | /** |
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[e2d0c68] | 284 | * @brief Initializes the CPU context. |
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[43e0599] | 285 | * |
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[e2d0c68] | 286 | * The following steps are performed: |
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[a385489] | 287 | * - setting a starting address |
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| 288 | * - preparing the stack |
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| 289 | * - preparing the stack and frame pointers |
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| 290 | * - setting the proper interrupt level in the context |
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| 291 | * |
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[e2d0c68] | 292 | * @param[in] context points to the context area |
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| 293 | * @param[in] stack_area_begin is the low address of the allocated stack area |
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| 294 | * @param[in] stack_area_size is the size of the stack area in bytes |
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[a385489] | 295 | * @param[in] new_level is the interrupt level for the task |
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| 296 | * @param[in] entry_point is the task's entry point |
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[e2d0c68] | 297 | * @param[in] is_fp is set to @c true if the task is a floating point task |
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[022851a] | 298 | * @param[in] tls_area is the thread-local storage (TLS) area |
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[7a28ac8] | 299 | */ |
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[a385489] | 300 | void _CPU_Context_Initialize( |
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[e2d0c68] | 301 | Context_Control *context, |
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| 302 | void *stack_area_begin, |
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| 303 | size_t stack_area_size, |
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| 304 | uint32_t new_level, |
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| 305 | void (*entry_point)( void ), |
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[022851a] | 306 | bool is_fp, |
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| 307 | void *tls_area |
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[a385489] | 308 | ); |
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[7a28ac8] | 309 | |
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| 310 | #define _CPU_Context_Restart_self( _the_context ) \ |
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[2a5880f1] | 311 | _CPU_Context_restore( (_the_context) ); |
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[7a28ac8] | 312 | |
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[e2d0c68] | 313 | void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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[7a28ac8] | 314 | |
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[43e0599] | 315 | /** |
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[4f5740f] | 316 | * @brief CPU initialization. |
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[43e0599] | 317 | */ |
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[2a5880f1] | 318 | void _CPU_Initialize( void ); |
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[7a28ac8] | 319 | |
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[43e0599] | 320 | /** |
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[4f5740f] | 321 | * @brief CPU ISR install raw handler. |
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[43e0599] | 322 | */ |
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[7a28ac8] | 323 | void _CPU_ISR_install_raw_handler( |
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[2a5880f1] | 324 | uint32_t vector, |
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| 325 | proc_ptr new_handler, |
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| 326 | proc_ptr *old_handler |
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[7a28ac8] | 327 | ); |
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| 328 | |
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[43e0599] | 329 | /** |
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[4f5740f] | 330 | * @brief CPU ISR install vector. |
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[43e0599] | 331 | */ |
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[7a28ac8] | 332 | void _CPU_ISR_install_vector( |
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[2a5880f1] | 333 | uint32_t vector, |
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| 334 | proc_ptr new_handler, |
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| 335 | proc_ptr *old_handler |
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[7a28ac8] | 336 | ); |
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| 337 | |
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[2a5880f1] | 338 | void _CPU_Context_switch( Context_Control *run, Context_Control *heir ); |
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[7a28ac8] | 339 | |
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| 340 | void _CPU_Context_restore( |
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| 341 | Context_Control *new_context |
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[479cbaf8] | 342 | ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE; |
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[7a28ac8] | 343 | |
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[39993d6] | 344 | void _CPU_Context_volatile_clobber( uintptr_t pattern ); |
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| 345 | |
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| 346 | void _CPU_Context_validate( uintptr_t pattern ); |
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| 347 | |
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[815994f] | 348 | void _CPU_Exception_frame_print( const CPU_Exception_frame *frame ); |
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| 349 | |
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[2a5880f1] | 350 | static inline uint32_t CPU_swap_u32( uint32_t value ) |
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[7a28ac8] | 351 | { |
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[2a5880f1] | 352 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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[80f7732] | 353 | |
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[7a28ac8] | 354 | byte4 = (value >> 24) & 0xff; |
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| 355 | byte3 = (value >> 16) & 0xff; |
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| 356 | byte2 = (value >> 8) & 0xff; |
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| 357 | byte1 = value & 0xff; |
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[80f7732] | 358 | |
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[7a28ac8] | 359 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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[2a5880f1] | 360 | |
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| 361 | return swapped; |
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[7a28ac8] | 362 | } |
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| 363 | |
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| 364 | #define CPU_swap_u16( value ) \ |
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| 365 | (((value&0xff) << 8) | ((value >> 8)&0xff)) |
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| 366 | |
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[24bf11e] | 367 | typedef uint32_t CPU_Counter_ticks; |
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| 368 | |
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| 369 | CPU_Counter_ticks _CPU_Counter_read( void ); |
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| 370 | |
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| 371 | static inline CPU_Counter_ticks _CPU_Counter_difference( |
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| 372 | CPU_Counter_ticks second, |
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| 373 | CPU_Counter_ticks first |
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| 374 | ) |
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| 375 | { |
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| 376 | return second - first; |
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| 377 | } |
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| 378 | |
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[2a5880f1] | 379 | #endif /* ASM */ |
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| 380 | |
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[7a28ac8] | 381 | #ifdef __cplusplus |
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| 382 | } |
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| 383 | #endif |
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| 384 | |
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| 385 | #endif |
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